2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
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21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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36 #ifndef _DEV_ATH_DESC_H
37 #define _DEV_ATH_DESC_H
39 #include <asf_queue.h>
42 #define HAL_TXSTAT_ALTRATE 0x80
43 #define ts_rssi ts_rssi_combined
45 struct ath_tx_status {
51 int8_t ts_rssi_combined;
58 a_uint8_t ts_shortretry;
59 a_uint8_t ts_longretry;
69 #define HAL_TXERR_XRETRY 0x01
70 #define HAL_TXERR_FILT 0x02
71 #define HAL_TXERR_FIFO 0x04
72 #define HAL_TXERR_XTXOP 0x08
73 #define HAL_TXERR_TIMER_EXPIRED 0x10
75 #define HAL_TX_BA 0x01
76 #define HAL_TX_PWRMGMT 0x02
77 #define HAL_TX_DESC_CFG_ERR 0x04
78 #define HAL_TX_DATA_UNDERRUN 0x08
79 #define HAL_TX_DELIM_UNDERRUN 0x10
80 #define HAL_TX_SW_FILTERED 0x80
82 struct ath_rx_status {
84 a_uint16_t rs_datalen;
87 int8_t rs_rssi_combined;
99 a_uint8_t rs_moreaggr;
100 a_uint8_t rs_num_delims;
108 #define rs_rssi rs_rssi_combined
110 #define HAL_RXERR_CRC 0x01
111 #define HAL_RXERR_PHY 0x02
112 #define HAL_RXERR_FIFO 0x04
113 #define HAL_RXERR_DECRYPT 0x08
114 #define HAL_RXERR_MIC 0x10
116 #define HAL_RX_MORE 0x01
117 #define HAL_RX_MORE_AGGR 0x02
118 #define HAL_RX_GI 0x04
119 #define HAL_RX_2040 0x08
120 #define HAL_RX_DELIM_CRC_PRE 0x10
121 #define HAL_RX_DELIM_CRC_POST 0x20
122 #define HAL_RX_DECRYPT_BUSY 0x40
126 #define HAL_RXKEYIX_INVALID ((a_uint8_t) -1)
128 #define HAL_TXKEYIX_INVALID ((a_uint8_t) -1)
131 * The following definitions are passed directly
132 * the hardware and managed by the HAL. Drivers
133 * should not touch those elements marked opaque.
135 #define ATH_GENERIC_DESC \
136 a_uint32_t ds_link; \
137 a_uint32_t ds_data; \
138 a_uint32_t ds_ctl0; \
149 adf_os_dma_map_t ds_dmap;
150 adf_os_dmamap_info_t ds_dmap_info;
151 adf_os_dma_addr_t ds_daddr;
152 asf_tailq_entry(ath_rx_desc) ds_list;
157 a_uint32_t ds_hw[20];
159 struct ath_tx_status tx;
163 #define ds_txstat ds_us.tx
166 #define HAL_TXDESC_CLRDMASK 0x0001
167 #define HAL_TXDESC_NOACK 0x0002
168 #define HAL_TXDESC_RTSENA 0x0004
169 #define HAL_TXDESC_CTSENA 0x0008
170 #define HAL_TXDESC_INTREQ 0x0010
171 #define HAL_TXDESC_VEOL 0x0020
172 #define HAL_TXDESC_EXT_ONLY 0x0040
173 #define HAL_TXDESC_EXT_AND_CTL 0x0080
174 #define HAL_TXDESC_VMF 0x0100
177 #define HAL_RXDESC_INTREQ 0x0020