2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include "athos_api.h"
42 // @TODO: Should define the memory region later~
43 #define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4)
44 #define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE)
46 // support for more than 64 bytes on command pipe
47 extern void vUsb_Reg_Out_patch(void);
48 extern int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe);
49 extern void _HIFusb_isr_handler_patch(hif_handle_t h);
50 extern BOOLEAN bSet_configuration_patch(void);
51 extern void vUSBFIFO_EP6Cfg_FS_patch(void);
52 extern void vUsb_Status_In_patch(void);
53 extern void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig);
54 extern void zfTurnOffPower_patch(void);
55 extern void zfResetUSBFIFO_patch(void);
56 extern void _HIFusb_start_patch(hif_handle_t handle);
57 extern void hif_pci_patch_install(struct hif_api *apis);
58 extern BOOLEAN bGet_descriptor_patch(void);
59 extern BOOLEAN bStandardCommand_patch(void);
62 extern void cmnos_clock_init_patch(a_uint32_t refclk);
63 extern a_uint32_t cmnos_refclk_speed_get_patch(void);
64 extern void cmnos_delay_us_patch(int us);
65 extern void cmnos_tick_patch(void);
66 extern a_uint32_t cmnos_milliseconds_patch(void);
68 extern BOOLEAN bJumptoFlash;
69 extern BOOLEAN bEepromExist;
74 #if defined(PROJECT_MAGPIE)
78 /* Zero BSS segment & dynamic memory section. */
81 #if defined(PROJECT_MAGPIE)
82 fatal_exception_func();
85 if( IS_FLASHBOOT() ) {
86 athos_indirection_table_install();
88 A_CLOCK_INIT(SYSTEM_CLK);
94 _indir_tbl.cmnos.timer._timer_init();
96 #if defined(PROJECT_K2)
98 * WAR: these variable is not initialized when boot from flash
99 * either re-enumeration or config them to default value = 0 would fix the issue
101 u8UsbInterfaceAlternateSetting = u8UsbConfigValue = u8UsbInterfaceValue = 0;
106 A_EEP_INIT(); /*Required for 1_1*/
109 #if defined(PROJECT_MAGPIE)
110 retEEP = A_EEP_IS_EXIST();
111 bJumptoFlash = FALSE;
112 if ( RET_SUCCESS == retEEP ) {
115 bEepromExist = FALSE;
119 hostif = A_IS_HOST_PRESENT();
121 #if defined(PROJECT_MAGPIE)
122 rst_status = *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR);
123 #elif defined(PROJECT_K2)
124 rst_status = HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR);
125 #endif /* #if defined(PROJECT_MAGPIE) */
128 A_PRINTF(" A_WDT_INIT()\n\r");
130 #if defined(PROJECT_K2)
131 save_cmnos_printf = fw_cmnos_printf;
134 if( hostif == HIF_USB ) {
135 #if defined(PROJECT_K2)
136 #if MOVE_PRINT_TO_RAM
137 save_cmnos_printf = _indir_tbl.cmnos.printf._printf;
138 _indir_tbl.cmnos.printf._printf = fw_cmnos_printf;
140 _indir_tbl.cmnos.usb._usb_fw_task = _fw_usb_fw_task;
141 _indir_tbl.cmnos.usb._usb_reset_fifo = _fw_usb_reset_fifo;
145 if( rst_status == WDT_MAGIC_PATTERN ) {
146 A_PRINTF(" ==>WDT reset<==\n");
147 #if defined(PROJECT_MAGPIE)
150 *((volatile uint32_t*)WATCH_DOG_RESET_COUNTER_ADDR)+=1;
151 } else if (rst_status == SUS_MAGIC_PATTERN) {
152 A_PRINTF(" ==>warm start<==\n");
154 A_PRINTF(" ==>cold start<==\n");
156 #if defined(PROJECT_MAGPIE)
157 *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR)=WDT_MAGIC_PATTERN;
158 #elif defined(PROJECT_K2)
159 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, WDT_MAGIC_PATTERN);
160 #endif /* #if defined(PROJECT_MAGPIE) */
162 /* intr enable would left for firmware */
163 /* athos_interrupt_init(); */
165 DBG_MODULE_INSTALL();
166 #if defined(PROJECT_K2)
170 #if defined(PROJECT_K2)
171 #if SYSTEM_MODULE_SFLASH
172 SFLASH_MODULE_INSTALL();
177 HIF_MODULE_INSTALL();
178 HTC_MODULE_INSTALL();
179 WMI_SERVICE_MODULE_INSTALL();
180 BUF_POOL_MODULE_INSTALL();
181 VBUF_MODULE_INSTALL();
182 VDESC_MODULE_INSTALL();
184 //init each module, should be put together..
185 A_PRINTF("ALLOCRAM start 0x%x size %d\n", ALLOCRAM_START, ALLOCRAM_SIZE);
186 A_ALLOCRAM_INIT(ALLOCRAM_START, ALLOCRAM_SIZE);
188 if( hostif == HIF_USB ) {
189 _indir_tbl.hif._get_max_msg_len = _HIFusb_get_max_msg_len_patch;
190 _indir_tbl.cmnos.usb._usb_reg_out = vUsb_Reg_Out_patch;
191 _indir_tbl.hif._isr_handler = _HIFusb_isr_handler_patch;
192 _indir_tbl.cmnos.usb._usb_set_configuration = bSet_configuration_patch;
193 _indir_tbl.cmnos.usb._usb_status_in = vUsb_Status_In_patch;
194 _indir_tbl.cmnos.usb._usb_get_descriptor = bGet_descriptor_patch;
195 _indir_tbl.cmnos.usb._usb_standard_cmd = bStandardCommand_patch;
196 _indir_tbl.usbfifo_api._init = _fw_usbfifo_init;
198 #if defined(PROJECT_MAGPIE)
199 _indir_tbl.cmnos.usb._usb_power_off = zfTurnOffPower_patch;
200 _indir_tbl.cmnos.usb._usb_reset_fifo = zfResetUSBFIFO_patch;
201 _indir_tbl.hif._start = _HIFusb_start_patch;
202 _indir_tbl.htc._HTC_MsgRecvHandler = HTCMsgRecvHandler_patch;
203 _indir_tbl.htc._HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg_patch;
206 if (!(USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT6)) {
207 vUSBFIFO_EP6Cfg_FS_patch();
210 #ifdef FUSION_USB_ENABLE_TX_STREAM
211 // For K2, enable tx stream mode
212 A_PRINTF("Enable Tx Stream mode\r\n");
214 // Patch for K2 USB STREAM mode
215 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
216 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))); // disable down stream DMA mode
218 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
219 ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)));
221 #if SYSTEM_MODULE_HP_EP5
222 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
223 ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)));
226 #if SYSTEM_MODULE_HP_EP6
227 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
228 ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)));
230 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
231 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0))); // enable down stream DMA mode
234 #ifdef FUSION_USB_ENABLE_RX_STREAM
235 // Patch for K2 USB STREAM mode
236 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
237 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))); // disable upstream DMA mode
238 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
239 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))); // enable upstream stream mode
241 // K2, Set maximum IN transfer to 8K
242 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
243 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(0xcf)));
244 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
245 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(0x20)));
247 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
248 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1))); // enable upstream DMA mode
250 USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, 0xa0); // set stream mode timeout critirea
251 #if defined(PROJECT_K2)
252 /*0x10004020 is vaild in k2 but could be invaild in other chip*/
253 if ((HAL_WORD_REG_READ(0x10004020) & 0x2000) != 0) {
254 /* disable stream mode for AR9270 */
255 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 0);
257 /* enable stream mode for AR9271 */
258 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
261 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
265 #if defined(PROJECT_MAGPIE) && !defined(ROM_VER_1_1)
266 else if (hostif == HIF_PCI )
267 hif_pci_patch_install(&_indir_tbl.hif);
270 // patch the clock function
272 _indir_tbl.cmnos.clock._clock_init = cmnos_clock_init_patch;
273 _indir_tbl.cmnos.clock._refclk_speed_get = cmnos_refclk_speed_get_patch;
274 _indir_tbl.cmnos.clock._delay_us = cmnos_delay_us_patch;
275 _indir_tbl.cmnos.clock._clock_tick = cmnos_tick_patch;
276 _indir_tbl.cmnos.clock._milliseconds = cmnos_milliseconds_patch;
278 //default clock, setup initial variable, SYSTEM_FREQ=40
279 A_CLOCK_INIT(SYSTEM_FREQ);
284 #if MAGPIE_ENABLE_WLAN == 1
286 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,
287 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT10|BIT8|BIT7|BIT6))));
288 #if defined(PROJECT_MAGPIE)
289 HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,
290 (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
293 wlan_pci_module_init();
298 A_PRINTF("Tgt running\n\r");
300 #if defined(PROJECT_MAGPIE)
302 A_PRINTF("======= Apply MISC Assert patch\n\r");
303 _assfail_ori = _indir_tbl.cmnos.misc._assfail;
304 _indir_tbl.cmnos.misc._assfail = exception_reset;
309 wlan_task(); //never return