2 * Copyright (c) 2013 Tensilica Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 xtensa/hal.h -- contains a definition of the Core HAL interface
27 All definitions in this header file are independent of any specific
28 Xtensa processor configuration. Thus software (eg. OS, application,
29 etc) can include this header file and be compiled into configuration-
30 independent objects that can be distributed and eventually linked
31 to the HAL library (libhal.a) to create a configuration-specific
34 Certain definitions, however, are release/version-specific -- such as
35 the XTHAL_RELEASE_xxx macros (or additions made in later versions).
42 /****************************************************************************
43 Definitions Useful for Any Code, USER or PRIVILEGED
44 ****************************************************************************/
47 /*----------------------------------------------------------------------
48 Constant Definitions (shared with assembly)
49 ----------------------------------------------------------------------*/
52 * Software (Xtensa Tools) version information. Not configuration-specific!
54 * NOTE: "release" is a misnomer here, these are really product "version"
55 * numbers. A "release" is a collection of product versions
56 * made available at once (together) to customers.
57 * In the past, release and version names all matched in T####.# form,
58 * making the distinction irrelevant. This is no longer the case.
60 #define XTHAL_RELEASE_MAJOR 7010
61 #define XTHAL_RELEASE_MINOR 0
62 #define XTHAL_RELEASE_NAME "7.1.0"
64 #define XTHAL_REL_7_1 1
65 #define XTHAL_REL_7_1_0 1
67 /* HAL version numbers (these names are for backward compatibility): */
68 #define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
69 #define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
71 * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
73 * SW Version MAJOR MINOR Comment
74 * ======= ===== ===== =======
75 * T1015.n n/a n/a (HAL not yet available)
76 * T1020.{0,1,2} 0 1 (HAL beta)
77 * T1020.{3,4} 0 2 First release.
78 * T1020.n (n>4) 0 2 or >3 (TBD)
79 * T1030.0 0 1 (HAL beta)
80 * T1030.{1,2} 0 3 Equivalent to first release.
81 * T1030.n (n>=3) 0 >= 3 (TBD)
82 * T1040.n 1040 n Full CHAL available from T1040.2
84 * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n)
85 * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n)
86 * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2))
89 * Note: there is a distinction between the software version with
90 * which something is compiled (accessible using XTHAL_RELEASE_* macros)
91 * and the software version with which the HAL library was compiled
92 * (accessible using Xthal_release_* global variables). This
93 * distinction is particularly relevant for vendors that distribute
94 * configuration-independent binaries (eg. an OS), where their customer
95 * might link it with a HAL of a different Xtensa software version.
96 * In this case, it may be appropriate for the OS to verify at run-time
97 * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
98 * [Guidelines as to which version is compatible with which are not
99 * currently provided explicitly, but might be inferred from reading
100 * OSKit documentation for all releases -- compatibility is also highly
101 * dependent on which HAL features are used. Each version is usually
102 * backward compatible, with very few exceptions if any.]
105 * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
106 * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0.
107 * Compile-time HAL port of NucleusPlus supported by T1040.2 and later.
110 /* Version comparison operators (among major/minor pairs): */
111 #define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \
112 ((maja) == (majb) && (mina) >= (minb)))
113 #define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \
114 ((maja) == (majb) && (mina) > (minb)))
115 #define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \
116 ((maja) == (majb) && (mina) <= (minb)))
117 #define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \
118 ((maja) == (majb) && (mina) < (minb)))
119 #define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb))
121 /* Fuzzy (3-way) logic operators: */
122 #define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */
123 #define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
124 #define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
125 #define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
129 * Architectural limit, independent of configuration:
131 #define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
134 #define XTHAL_LITTLEENDIAN 0
135 #define XTHAL_BIGENDIAN 1
139 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
144 /*----------------------------------------------------------------------
146 ----------------------------------------------------------------------*/
148 /* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
149 extern const unsigned int Xthal_rev_no;
152 /*----------------------------------------------------------------------
153 Optional/Custom Processor State
154 ----------------------------------------------------------------------*/
156 /* save & restore the extra processor state */
157 extern void xthal_save_extra(void *base);
158 extern void xthal_restore_extra(void *base);
160 extern void xthal_save_cpregs(void *base, int);
161 extern void xthal_restore_cpregs(void *base, int);
162 /* versions specific to each coprocessor id */
163 extern void xthal_save_cp0(void *base);
164 extern void xthal_save_cp1(void *base);
165 extern void xthal_save_cp2(void *base);
166 extern void xthal_save_cp3(void *base);
167 extern void xthal_save_cp4(void *base);
168 extern void xthal_save_cp5(void *base);
169 extern void xthal_save_cp6(void *base);
170 extern void xthal_save_cp7(void *base);
171 extern void xthal_restore_cp0(void *base);
172 extern void xthal_restore_cp1(void *base);
173 extern void xthal_restore_cp2(void *base);
174 extern void xthal_restore_cp3(void *base);
175 extern void xthal_restore_cp4(void *base);
176 extern void xthal_restore_cp5(void *base);
177 extern void xthal_restore_cp6(void *base);
178 extern void xthal_restore_cp7(void *base);
179 /* pointers to each of the functions above */
180 extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
181 extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
182 /* similarly for non-windowed ABI (may be same or different) */
183 extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
184 extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
186 /*extern void xthal_save_all_extra(void *base);*/
187 /*extern void xthal_restore_all_extra(void *base);*/
189 /* space for processor state */
190 extern const unsigned int Xthal_extra_size;
191 extern const unsigned int Xthal_extra_align;
192 extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
193 extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
194 extern const unsigned int Xthal_all_extra_size;
195 extern const unsigned int Xthal_all_extra_align;
196 /* coprocessor names */
197 extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
199 /* initialize the extra processor */
200 /*extern void xthal_init_extra(void);*/
201 /* initialize the TIE coprocessor */
202 /*extern void xthal_init_cp(int);*/
204 /* initialize the extra processor */
205 extern void xthal_init_mem_extra(void *);
206 /* initialize the TIE coprocessor */
207 extern void xthal_init_mem_cp(void *, int);
209 /* the number of TIE coprocessors contiguous from zero (for Tor2) */
210 extern const unsigned int Xthal_num_coprocessors;
212 /* actual number of coprocessors */
213 extern const unsigned char Xthal_cp_num;
214 /* index of highest numbered coprocessor, plus one */
215 extern const unsigned char Xthal_cp_max;
216 /* index of highest allowed coprocessor number, per cfg, plus one */
217 /*extern const unsigned char Xthal_cp_maxcfg;*/
218 /* bitmask of which coprocessors are present */
219 extern const unsigned int Xthal_cp_mask;
221 /* read & write extra state register */
222 /*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
223 /*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
225 /* read & write a TIE coprocessor register */
226 /*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
227 /*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
229 /* return coprocessor number based on register */
230 /*extern int xthal_which_cp(unsigned reg);*/
233 /*----------------------------------------------------------------------
235 ----------------------------------------------------------------------*/
237 /* number of registers in register window */
238 extern const unsigned int Xthal_num_aregs;
239 extern const unsigned char Xthal_num_aregs_log2;
242 /*----------------------------------------------------------------------
244 ----------------------------------------------------------------------*/
246 /* size of the cache lines in log2(bytes) */
247 extern const unsigned char Xthal_icache_linewidth;
248 extern const unsigned char Xthal_dcache_linewidth;
249 /* size of the cache lines in bytes (2^linewidth) */
250 extern const unsigned short Xthal_icache_linesize;
251 extern const unsigned short Xthal_dcache_linesize;
253 /* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
254 extern const unsigned int Xthal_icache_size;
255 extern const unsigned int Xthal_dcache_size;
257 extern const unsigned char Xthal_dcache_is_writeback;
259 /* invalidate the caches */
260 extern void xthal_icache_region_invalidate( void *addr, unsigned size );
261 extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
262 extern void xthal_icache_line_invalidate(void *addr);
263 extern void xthal_dcache_line_invalidate(void *addr);
264 /* write dirty data back */
265 extern void xthal_dcache_region_writeback( void *addr, unsigned size );
266 extern void xthal_dcache_line_writeback(void *addr);
267 /* write dirty data back and invalidate */
268 extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
269 extern void xthal_dcache_line_writeback_inv(void *addr);
271 /* sync icache and memory */
272 extern void xthal_icache_sync( void );
273 /* sync dcache and memory */
274 extern void xthal_dcache_sync( void );
277 /*----------------------------------------------------------------------
279 ----------------------------------------------------------------------*/
281 /* 1 if debug option configured, 0 if not: */
282 extern const int Xthal_debug_configured;
284 /* Set (plant) and remove software breakpoint, both synchronizing cache: */
285 extern unsigned int xthal_set_soft_break(void *addr);
286 extern void xthal_remove_soft_break(void *addr, unsigned int);
289 /*----------------------------------------------------------------------
291 ----------------------------------------------------------------------*/
293 /* Max expected size of the return buffer for a disassembled instruction (hint only): */
294 #define XTHAL_DISASM_BUFSIZE 80
296 /* Disassembly option bits for selecting what to return: */
297 #define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
298 #define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
299 #define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
300 #define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
301 #define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
303 /* routine to get a string for the disassembled instruction */
304 extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
305 char *buffer, unsigned buflen, unsigned options );
307 /* routine to get the size of the next instruction. Returns 0 for
308 illegal instruction */
309 extern int xthal_disassemble_size( unsigned char *instr_buf );
312 /*----------------------------------------------------------------------
313 Instruction/Data RAM/ROM Access
314 ----------------------------------------------------------------------*/
316 extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
317 extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
320 /*----------------------------------------------------------------------
322 ----------------------------------------------------------------------*/
324 extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
326 /*extern const char Xthal_have_s32c1i;*/
329 /*----------------------------------------------------------------------
331 ----------------------------------------------------------------------*/
333 extern const unsigned int Xthal_release_major;
334 extern const unsigned int Xthal_release_minor;
335 extern const char * const Xthal_release_name;
336 extern const char * const Xthal_release_internal;
338 extern const unsigned char Xthal_memory_order;
339 extern const unsigned char Xthal_have_windowed;
340 extern const unsigned char Xthal_have_density;
341 extern const unsigned char Xthal_have_booleans;
342 extern const unsigned char Xthal_have_loops;
343 extern const unsigned char Xthal_have_nsa;
344 extern const unsigned char Xthal_have_minmax;
345 extern const unsigned char Xthal_have_sext;
346 extern const unsigned char Xthal_have_clamps;
347 extern const unsigned char Xthal_have_mac16;
348 extern const unsigned char Xthal_have_mul16;
349 extern const unsigned char Xthal_have_fp;
350 extern const unsigned char Xthal_have_speculation;
351 extern const unsigned char Xthal_have_threadptr;
353 extern const unsigned char Xthal_have_pif;
354 extern const unsigned short Xthal_num_writebuffer_entries;
356 extern const unsigned int Xthal_build_unique_id;
357 /* Version info for hardware targeted by software upgrades: */
358 extern const unsigned int Xthal_hw_configid0;
359 extern const unsigned int Xthal_hw_configid1;
360 extern const unsigned int Xthal_hw_release_major;
361 extern const unsigned int Xthal_hw_release_minor;
362 extern const char * const Xthal_hw_release_name;
363 extern const char * const Xthal_hw_release_internal;
368 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
374 /****************************************************************************
375 Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
376 ****************************************************************************/
379 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
381 /*----------------------------------------------------------------------
382 Constant Definitions (shared with assembly)
383 ----------------------------------------------------------------------*/
386 * Architectural limits, independent of configuration.
387 * Note that these are ISA-defined limits, not micro-architecture implementation
388 * limits enforced by the Xtensa Processor Generator (which may be stricter than
391 #define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
392 #define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
393 /* (as of T1040, implementation limit is 7: 0..6) */
394 #define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
395 /* (as of T1040, implementation limit is 3: 0..2) */
397 /* Interrupt types: */
398 #define XTHAL_INTTYPE_UNCONFIGURED 0
399 #define XTHAL_INTTYPE_SOFTWARE 1
400 #define XTHAL_INTTYPE_EXTERN_EDGE 2
401 #define XTHAL_INTTYPE_EXTERN_LEVEL 3
402 #define XTHAL_INTTYPE_TIMER 4
403 #define XTHAL_INTTYPE_NMI 5
404 #define XTHAL_INTTYPE_WRITE_ERROR 6
405 #define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */
408 #define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
409 #define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
411 /* Local Memory ECC/Parity: */
412 #define XTHAL_MEMEP_PARITY 1
413 #define XTHAL_MEMEP_ECC 2
414 /* Flags parameter to xthal_memep_inject_error(): */
415 #define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */
416 #define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */
417 #define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */
418 #define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */
419 #define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */
420 #define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error
421 (default is non-corr.) */
424 /* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
425 #define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none
426 exception on any access (aka "illegal") */
427 #define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI)
428 [or H HC] way from tag match;
429 [or U UC] (ISA: same except Isolate case) */
430 #define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none
431 [or F FI fill] refill cache on miss, way from LRU
432 (ISA: Read/Write Miss Refill) */
433 #define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT
434 store immediately to memory (ISA: same) */
435 #define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none
436 use cache regardless of hit-vs-miss,
437 way from vaddr (ISA: use-cache-on-miss+hit) */
438 #define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G *
439 non-speculative; spec/replay refs not permitted */
441 #define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M
442 on read, other CPU/bus-master may need to supply data;
443 on write, maybe redirect to or flush other CPU dirty line; etc */
444 #define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G *
445 mem accesses cannot be out of order */
446 #define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none
447 allow combining/merging multiple writes
448 (to same datapath data unit) into one
449 (implied by writeback) */
450 #define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none
451 memory will not bus error (if it does,
452 handle as fatal imprecise interrupt) */
453 #define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none
454 on refill, read line+1 into prefetch buffers */
455 #define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none
456 access one of N stream buffers */
459 #define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
460 #define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
461 #define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
462 #define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
463 #define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
464 #define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
466 #define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
467 #define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
468 #define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
469 #define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
470 #define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
471 #define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
475 * Allowed Access Modes (bit combinations).
479 * Access mode bits (see XTHAL_AMB_xxx above).
480 * <letter> = bit is set
482 * '.' = bit is irrelevant / don't care, as follows:
483 * E=1 makes all others irrelevant
484 * W,F relevant only for stores
486 * Indicates which Xtensa releases support the corresponding
487 * access mode. Releases for each character column are:
488 * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
489 * 3 = T1020.2 and later: T1020.2+, T1030
491 * 5 = T1050 (maybe), LX1, LX2, LX2.1
493 * And the character column contents are:
494 * <number> = support by release(s)
495 * "." = unsupported by release(s)
496 * "?" = support unknown
498 /* FOMGIWACE 23457 */
499 /* For instruction fetch: */
500 #define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */
501 #define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */
502 #define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */
503 #define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */
504 #define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */
506 #define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */
507 #define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */
508 #define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */
509 #define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */
510 #define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */
511 #define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */
512 #define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */
513 #define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */
514 #define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */
515 /* For data store: */
516 #define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */
517 #define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */
518 #define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */
519 /*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */
520 #define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */
521 /*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */
522 #define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */
523 /*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */
524 #define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */
528 Cache attribute encoding for CACHEATTR (per ISA):
529 (Note: if this differs from ISA Ref Manual, ISA has precedence)
531 Inst-fetches Loads Stores
532 ------------- ------------ -------------
533 0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate)
534 0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
535 0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass
536 0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
537 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
538 0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back
539 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
540 0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
541 0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
542 0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
543 * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
548 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
554 /*----------------------------------------------------------------------
556 ----------------------------------------------------------------------*/
558 /* This spill any live register windows (other than the caller's):
559 * (NOTE: current implementation require privileged code, but
560 * a user-callable implementation is possible.) */
561 extern void xthal_window_spill( void );
564 /*----------------------------------------------------------------------
565 Optional/Custom Processor State
566 ----------------------------------------------------------------------*/
568 /* validate & invalidate the TIE register file */
569 extern void xthal_validate_cp(int);
570 extern void xthal_invalidate_cp(int);
572 /* read and write cpenable register */
573 extern void xthal_set_cpenable(unsigned);
574 extern unsigned xthal_get_cpenable(void);
577 /*----------------------------------------------------------------------
579 ----------------------------------------------------------------------*/
581 /* the number of interrupt levels */
582 extern const unsigned char Xthal_num_intlevels;
583 /* the number of interrupts */
584 extern const unsigned char Xthal_num_interrupts;
586 /* mask for level of interrupts */
587 extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
588 /* mask for level 0 to N interrupts */
589 extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
591 /* level of each interrupt */
592 extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
594 /* type per interrupt */
595 extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
597 /* masks of each type of interrupt */
598 extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
600 /* interrupt numbers assigned to each timer interrupt */
601 extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
603 /* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */
604 extern unsigned xthal_get_intenable( void );
605 extern void xthal_set_intenable( unsigned );
606 extern unsigned xthal_get_interrupt( void );
607 #define xthal_get_intread xthal_get_interrupt /* backward compatibility */
608 extern void xthal_set_intset( unsigned );
609 extern void xthal_set_intclear( unsigned );
612 /*----------------------------------------------------------------------
614 ----------------------------------------------------------------------*/
616 /* Number of instruction and data break registers: */
617 extern const int Xthal_num_ibreak;
618 extern const int Xthal_num_dbreak;
621 /*----------------------------------------------------------------------
623 ----------------------------------------------------------------------*/
626 extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
627 extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
629 /* get CCOUNT register (if not present return 0) */
630 extern unsigned xthal_get_ccount(void);
632 /* set and get CCOMPAREn registers (if not present, get returns 0) */
633 extern void xthal_set_ccompare(int, unsigned);
634 extern unsigned xthal_get_ccompare(int);
637 /*----------------------------------------------------------------------
639 ----------------------------------------------------------------------*/
641 extern const unsigned char Xthal_have_prid;
642 extern const unsigned char Xthal_have_exceptions;
643 extern const unsigned char Xthal_xea_version;
644 extern const unsigned char Xthal_have_interrupts;
645 extern const unsigned char Xthal_have_highlevel_interrupts;
646 extern const unsigned char Xthal_have_nmi;
648 extern unsigned xthal_get_prid( void );
651 /*----------------------------------------------------------------------
652 Virtual interrupt prioritization (DEPRECATED)
653 ----------------------------------------------------------------------*/
655 /* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
656 extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
657 extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
659 /* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
660 extern unsigned xthal_int_enable(unsigned);
661 extern unsigned xthal_int_disable(unsigned);
663 /* Set/get virtual priority of an interrupt: */
664 extern int xthal_set_int_vpri(int intnum, int vpri);
665 extern int xthal_get_int_vpri(int intnum);
667 /* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
668 extern void xthal_set_vpri_locklevel(unsigned intlevel);
669 extern unsigned xthal_get_vpri_locklevel(void);
671 /* Set/get current virtual interrupt priority: */
672 extern unsigned xthal_set_vpri(unsigned vpri);
673 extern unsigned xthal_get_vpri(void);
674 extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
675 extern unsigned xthal_set_vpri_lock(void);
678 /*----------------------------------------------------------------------
679 Generic Interrupt Trampolining Support (DEPRECATED)
680 ----------------------------------------------------------------------*/
682 typedef void (XtHalVoidFunc)(void);
684 /* Bitmask of interrupts currently trampolining down: */
685 extern unsigned Xthal_tram_pending;
688 * Bitmask of which interrupts currently trampolining down synchronously are
689 * actually enabled; this bitmask is necessary because INTENABLE cannot hold
690 * that state (sync-trampolining interrupts must be kept disabled while
691 * trampolining); in the current implementation, any bit set here is not set
692 * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
693 * one), its enable bit must be moved from here to INTENABLE:
695 extern unsigned Xthal_tram_enabled;
697 /* Bitmask of interrupts configured for sync trampolining: */
698 extern unsigned Xthal_tram_sync;
700 /* Trampoline support functions: */
701 extern unsigned xthal_tram_pending_to_service( void );
702 extern void xthal_tram_done( unsigned serviced_mask );
703 extern int xthal_tram_set_sync( int intnum, int sync );
704 extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
707 /*----------------------------------------------------------------------
709 ----------------------------------------------------------------------*/
711 extern const unsigned char Xthal_num_instrom;
712 extern const unsigned char Xthal_num_instram;
713 extern const unsigned char Xthal_num_datarom;
714 extern const unsigned char Xthal_num_dataram;
715 extern const unsigned char Xthal_num_xlmi;
717 /* Each of the following arrays contains at least one entry,
718 * or as many entries as needed if more than one: */
719 extern const unsigned int Xthal_instrom_vaddr[];
720 extern const unsigned int Xthal_instrom_paddr[];
721 extern const unsigned int Xthal_instrom_size [];
722 extern const unsigned int Xthal_instram_vaddr[];
723 extern const unsigned int Xthal_instram_paddr[];
724 extern const unsigned int Xthal_instram_size [];
725 extern const unsigned int Xthal_datarom_vaddr[];
726 extern const unsigned int Xthal_datarom_paddr[];
727 extern const unsigned int Xthal_datarom_size [];
728 extern const unsigned int Xthal_dataram_vaddr[];
729 extern const unsigned int Xthal_dataram_paddr[];
730 extern const unsigned int Xthal_dataram_size [];
731 extern const unsigned int Xthal_xlmi_vaddr[];
732 extern const unsigned int Xthal_xlmi_paddr[];
733 extern const unsigned int Xthal_xlmi_size [];
736 /*----------------------------------------------------------------------
738 ----------------------------------------------------------------------*/
740 /* number of cache sets in log2(lines per way) */
741 extern const unsigned char Xthal_icache_setwidth;
742 extern const unsigned char Xthal_dcache_setwidth;
743 /* cache set associativity (number of ways) */
744 extern const unsigned int Xthal_icache_ways;
745 extern const unsigned int Xthal_dcache_ways;
747 extern const unsigned char Xthal_icache_line_lockable;
748 extern const unsigned char Xthal_dcache_line_lockable;
750 /* cache attribute register control (used by other HAL routines) */
751 extern unsigned xthal_get_cacheattr( void );
752 extern unsigned xthal_get_icacheattr( void );
753 extern unsigned xthal_get_dcacheattr( void );
754 extern void xthal_set_cacheattr( unsigned );
755 extern void xthal_set_icacheattr( unsigned );
756 extern void xthal_set_dcacheattr( unsigned );
757 /* set cache attribute (access modes) for a range of memory */
758 extern int xthal_set_region_attribute( void *addr, unsigned size,
759 unsigned cattr, unsigned flags );
760 /* Bits of flags parameter to xthal_set_region_attribute(): */
761 #define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */
762 #define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */
763 #define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */
764 #define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */
765 #define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */
768 extern void xthal_icache_enable( void ); /* DEPRECATED */
769 extern void xthal_dcache_enable( void ); /* DEPRECATED */
771 extern void xthal_icache_disable( void ); /* DEPRECATED */
772 extern void xthal_dcache_disable( void ); /* DEPRECATED */
774 /* invalidate the caches */
775 extern void xthal_icache_all_invalidate( void );
776 extern void xthal_dcache_all_invalidate( void );
777 /* write dirty data back */
778 extern void xthal_dcache_all_writeback( void );
779 /* write dirty data back and invalidate */
780 extern void xthal_dcache_all_writeback_inv( void );
781 /* prefetch and lock specified memory range into cache */
782 extern void xthal_icache_region_lock( void *addr, unsigned size );
783 extern void xthal_dcache_region_lock( void *addr, unsigned size );
784 extern void xthal_icache_line_lock(void *addr);
785 extern void xthal_dcache_line_lock(void *addr);
786 /* unlock from cache */
787 extern void xthal_icache_all_unlock( void );
788 extern void xthal_dcache_all_unlock( void );
789 extern void xthal_icache_region_unlock( void *addr, unsigned size );
790 extern void xthal_dcache_region_unlock( void *addr, unsigned size );
791 extern void xthal_icache_line_unlock(void *addr);
792 extern void xthal_dcache_line_unlock(void *addr);
796 /*----------------------------------------------------------------------
797 Local Memory ECC/Parity
798 ----------------------------------------------------------------------*/
800 /* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */
801 extern void xthal_memep_inject_error(void *addr, int size, int flags);
805 /*----------------------------------------------------------------------
806 Memory Management Unit
807 ----------------------------------------------------------------------*/
809 extern const unsigned char Xthal_have_spanning_way;
810 extern const unsigned char Xthal_have_identity_map;
811 extern const unsigned char Xthal_have_mimic_cacheattr;
812 extern const unsigned char Xthal_have_xlt_cacheattr;
813 extern const unsigned char Xthal_have_cacheattr;
814 extern const unsigned char Xthal_have_tlbs;
816 extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
817 extern const unsigned char Xthal_mmu_asid_kernel;
818 extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
819 extern const unsigned char Xthal_mmu_ring_bits;
820 extern const unsigned char Xthal_mmu_sr_bits;
821 extern const unsigned char Xthal_mmu_ca_bits;
822 extern const unsigned int Xthal_mmu_max_pte_page_size;
823 extern const unsigned int Xthal_mmu_min_pte_page_size;
825 extern const unsigned char Xthal_itlb_way_bits;
826 extern const unsigned char Xthal_itlb_ways;
827 extern const unsigned char Xthal_itlb_arf_ways;
828 extern const unsigned char Xthal_dtlb_way_bits;
829 extern const unsigned char Xthal_dtlb_ways;
830 extern const unsigned char Xthal_dtlb_arf_ways;
832 /* Convert between virtual and physical addresses (through static maps only): */
833 /*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
834 extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
835 extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
841 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
843 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
848 /****************************************************************************
849 EXPERIMENTAL and DEPRECATED Definitions
850 ****************************************************************************/
853 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
858 #ifdef INCLUDE_DEPRECATED_HAL_CODE
859 extern const unsigned char Xthal_have_old_exc_arch;
860 extern const unsigned char Xthal_have_mmu;
861 extern const unsigned int Xthal_num_regs;
862 extern const unsigned char Xthal_num_iroms;
863 extern const unsigned char Xthal_num_irams;
864 extern const unsigned char Xthal_num_droms;
865 extern const unsigned char Xthal_num_drams;
866 extern const unsigned int Xthal_configid0;
867 extern const unsigned int Xthal_configid1;
870 #ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
871 #define XTHAL_24_BIT_BREAK 0x80000000
872 #define XTHAL_16_BIT_BREAK 0x40000000
873 extern const unsigned short Xthal_ill_inst_16[16];
874 #define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
875 #define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
876 #define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
877 #define XTHAL_RFW_INST 0x00000800
878 #define XTHAL_RFUE_INST 0x00000400
879 #define XTHAL_RFI_INST 0x00000200
880 #define XTHAL_RFE_INST 0x00000100
881 #define XTHAL_RET_INST 0x00000080
882 #define XTHAL_BREAK_INST 0x00000040
883 #define XTHAL_SYSCALL_INST 0x00000020
884 #define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
885 #define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
886 #define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
887 #define XTHAL_24_BIT_INST 0x00000002
888 #define XTHAL_16_BIT_INST 0x00000001
889 typedef struct xthal_state {
896 unsigned cpregs_ptr[XTHAL_MAX_CPS];
898 extern unsigned int xthal_inst_type(void *addr);
899 extern unsigned int xthal_branch_addr(void *addr);
900 extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
901 #endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
906 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
908 #endif /*XTENSA_HAL_H*/