2 * Copyright (c) 2013 Tensilica Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
27 #ifndef XTENSA_COREBITS_H
28 #define XTENSA_COREBITS_H
30 /* EXCCAUSE register fields: */
31 #define EXCCAUSE_EXCCAUSE_SHIFT 0
32 #define EXCCAUSE_EXCCAUSE_MASK 0x3F
33 /* EXCCAUSE register values: */
35 * General Exception Causes
36 * (values of EXCCAUSE special register set by general exceptions,
37 * which vector to the user, kernel, or double-exception vectors).
39 #define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
40 #define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
41 #define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
42 # define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
43 #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
44 # define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
45 #define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
46 # define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
47 #define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
48 #define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
49 #define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
50 #define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
51 #define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
53 #define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
54 #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
55 #define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
56 #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
57 #define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
58 #define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
59 #define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
60 /* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
61 #define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
63 #define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
64 #define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
65 #define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
66 /* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
67 #define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
68 #define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
70 #define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
71 #define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
72 #define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
73 #define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
74 #define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
75 #define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
76 #define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
77 #define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
78 #define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
79 /*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */
82 /* PS register fields: */
83 #define PS_WOE_SHIFT 18
84 #define PS_WOE_MASK 0x00040000
85 #define PS_WOE PS_WOE_MASK
86 #define PS_CALLINC_SHIFT 16
87 #define PS_CALLINC_MASK 0x00030000
88 #define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
89 #define PS_OWB_SHIFT 8
90 #define PS_OWB_MASK 0x00000F00
91 #define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
92 #define PS_RING_SHIFT 6
93 #define PS_RING_MASK 0x000000C0
94 #define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
96 #define PS_UM_MASK 0x00000020
97 #define PS_UM PS_UM_MASK
98 #define PS_EXCM_SHIFT 4
99 #define PS_EXCM_MASK 0x00000010
100 #define PS_EXCM PS_EXCM_MASK
101 #define PS_INTLEVEL_SHIFT 0
102 #define PS_INTLEVEL_MASK 0x0000000F
103 #define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
104 /* Backward compatibility (deprecated): */
105 #define PS_PROGSTACK_SHIFT PS_UM_SHIFT
106 #define PS_PROGSTACK_MASK PS_UM_MASK
107 #define PS_PROG_SHIFT PS_UM_SHIFT
108 #define PS_PROG_MASK PS_UM_MASK
109 #define PS_PROG PS_UM
111 /* DBREAKCn register fields: */
112 #define DBREAKC_MASK_SHIFT 0
113 #define DBREAKC_MASK_MASK 0x0000003F
114 #define DBREAKC_LOADBREAK_SHIFT 30
115 #define DBREAKC_LOADBREAK_MASK 0x40000000
116 #define DBREAKC_STOREBREAK_SHIFT 31
117 #define DBREAKC_STOREBREAK_MASK 0x80000000
119 /* DEBUGCAUSE register fields: */
120 #define DEBUGCAUSE_DEBUGINT_SHIFT 5
121 #define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
122 #define DEBUGCAUSE_BREAKN_SHIFT 4
123 #define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
124 #define DEBUGCAUSE_BREAK_SHIFT 3
125 #define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
126 #define DEBUGCAUSE_DBREAK_SHIFT 2
127 #define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
128 #define DEBUGCAUSE_IBREAK_SHIFT 1
129 #define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
130 #define DEBUGCAUSE_ICOUNT_SHIFT 0
131 #define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
133 /* MESR register fields: */
134 #define MESR_MEME 0x00000001 /* memory error */
135 #define MESR_MEME_SHIFT 0
136 #define MESR_DME 0x00000002 /* double memory error */
137 #define MESR_DME_SHIFT 1
138 #define MESR_RCE 0x00000010 /* recorded memory error */
139 #define MESR_RCE_SHIFT 4
141 #define MESR_LCE_SHIFT ?
143 #define MESR_ERRENAB 0x00000100
144 #define MESR_ERRENAB_SHIFT 8
145 #define MESR_ERRTEST 0x00000200
146 #define MESR_ERRTEST_SHIFT 9
147 #define MESR_DATEXC 0x00000400
148 #define MESR_DATEXC_SHIFT 10
149 #define MESR_INSEXC 0x00000800
150 #define MESR_INSEXC_SHIFT 11
151 #define MESR_WAYNUM_SHIFT 16
152 #define MESR_ACCTYPE_SHIFT 20
153 #define MESR_MEMTYPE_SHIFT 24
154 #define MESR_ERRTYPE_SHIFT 30
157 #endif /*XTENSA_COREBITS_H*/