2 * Copyright (c) 2013 Tensilica Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
26 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
27 * It pulls definitions tailored for a specific Xtensa processor configuration.
29 * Sources for binaries meant to be configuration-independent generally avoid
30 * including this file (they may use the configuration-specific HAL library).
31 * It is normal for the HAL library source itself to include this file.
34 #ifndef XTENSA_CONFIG_CORE_H
35 #define XTENSA_CONFIG_CORE_H
37 /* CONFIGURATION INDEPENDENT DEFINITIONS: */
39 #include <xtensa/hal.h>
44 /* CONFIGURATION SPECIFIC DEFINITIONS: */
46 #include <xtensa/config/core-isa.h>
47 #include <xtensa/config/core-matmap.h>
48 #include <xtensa/config/tie.h>
51 #include "core-matmap.h"
55 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
57 #include <xtensa/config/tie-asm.h>
61 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/
64 /*----------------------------------------------------------------------
66 ----------------------------------------------------------------------*/
69 * Separators for macros that expand into arrays.
70 * These can be predefined by files that #include this one,
71 * when different separators are required.
73 /* Element separator for macros that expand into 1-dimensional arrays: */
77 /* Array separator for macros that expand into 2-dimensional arrays: */
79 #define XCHAL_SEP2 },{
84 /*----------------------------------------------------------------------
86 ----------------------------------------------------------------------*/
89 # define XCHAL_HAVE_LE 0
90 # define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
92 # define XCHAL_HAVE_LE 1
93 # define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN
98 /*----------------------------------------------------------------------
100 ----------------------------------------------------------------------*/
102 /* Indexing macros: */
103 #define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
104 #define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
105 #define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
106 #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
107 #define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM
108 #define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */
109 #define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
110 #define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
111 #define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
112 #define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
113 #define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
114 #define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
117 #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
118 #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
119 #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
120 /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
122 /* These values are constant for existing Xtensa processor implementations: */
123 #define XCHAL_INTLEVEL0_MASK 0x00000000
124 #define XCHAL_INTLEVEL8_MASK 0x00000000
125 #define XCHAL_INTLEVEL9_MASK 0x00000000
126 #define XCHAL_INTLEVEL10_MASK 0x00000000
127 #define XCHAL_INTLEVEL11_MASK 0x00000000
128 #define XCHAL_INTLEVEL12_MASK 0x00000000
129 #define XCHAL_INTLEVEL13_MASK 0x00000000
130 #define XCHAL_INTLEVEL14_MASK 0x00000000
131 #define XCHAL_INTLEVEL15_MASK 0x00000000
133 /* Array of masks of interrupts at each interrupt level: */
134 #define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \
135 XCHAL_SEP XCHAL_INTLEVEL1_MASK \
136 XCHAL_SEP XCHAL_INTLEVEL2_MASK \
137 XCHAL_SEP XCHAL_INTLEVEL3_MASK \
138 XCHAL_SEP XCHAL_INTLEVEL4_MASK \
139 XCHAL_SEP XCHAL_INTLEVEL5_MASK \
140 XCHAL_SEP XCHAL_INTLEVEL6_MASK \
141 XCHAL_SEP XCHAL_INTLEVEL7_MASK \
142 XCHAL_SEP XCHAL_INTLEVEL8_MASK \
143 XCHAL_SEP XCHAL_INTLEVEL9_MASK \
144 XCHAL_SEP XCHAL_INTLEVEL10_MASK \
145 XCHAL_SEP XCHAL_INTLEVEL11_MASK \
146 XCHAL_SEP XCHAL_INTLEVEL12_MASK \
147 XCHAL_SEP XCHAL_INTLEVEL13_MASK \
148 XCHAL_SEP XCHAL_INTLEVEL14_MASK \
149 XCHAL_SEP XCHAL_INTLEVEL15_MASK
151 /* These values are constant for existing Xtensa processor implementations: */
152 #define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
153 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
154 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
155 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
156 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
157 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
158 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
159 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
160 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
162 /* Mask of all low-priority interrupts: */
163 #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK
165 /* Mask of all interrupts masked by PS.EXCM (or CEXCM): */
166 #define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
168 /* Array of masks of interrupts at each range 1..n of interrupt levels: */
169 #define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \
170 XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \
171 XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \
172 XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \
173 XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \
174 XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \
175 XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \
176 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
177 XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \
178 XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \
179 XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \
180 XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \
181 XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \
182 XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \
183 XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \
184 XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK
186 #if 0 /*XCHAL_HAVE_NMI*/
187 /* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */
188 # define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1)
191 /* Array of levels of each possible interrupt: */
192 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
193 XCHAL_SEP XCHAL_INT1_LEVEL \
194 XCHAL_SEP XCHAL_INT2_LEVEL \
195 XCHAL_SEP XCHAL_INT3_LEVEL \
196 XCHAL_SEP XCHAL_INT4_LEVEL \
197 XCHAL_SEP XCHAL_INT5_LEVEL \
198 XCHAL_SEP XCHAL_INT6_LEVEL \
199 XCHAL_SEP XCHAL_INT7_LEVEL \
200 XCHAL_SEP XCHAL_INT8_LEVEL \
201 XCHAL_SEP XCHAL_INT9_LEVEL \
202 XCHAL_SEP XCHAL_INT10_LEVEL \
203 XCHAL_SEP XCHAL_INT11_LEVEL \
204 XCHAL_SEP XCHAL_INT12_LEVEL \
205 XCHAL_SEP XCHAL_INT13_LEVEL \
206 XCHAL_SEP XCHAL_INT14_LEVEL \
207 XCHAL_SEP XCHAL_INT15_LEVEL \
208 XCHAL_SEP XCHAL_INT16_LEVEL \
209 XCHAL_SEP XCHAL_INT17_LEVEL \
210 XCHAL_SEP XCHAL_INT18_LEVEL \
211 XCHAL_SEP XCHAL_INT19_LEVEL \
212 XCHAL_SEP XCHAL_INT20_LEVEL \
213 XCHAL_SEP XCHAL_INT21_LEVEL \
214 XCHAL_SEP XCHAL_INT22_LEVEL \
215 XCHAL_SEP XCHAL_INT23_LEVEL \
216 XCHAL_SEP XCHAL_INT24_LEVEL \
217 XCHAL_SEP XCHAL_INT25_LEVEL \
218 XCHAL_SEP XCHAL_INT26_LEVEL \
219 XCHAL_SEP XCHAL_INT27_LEVEL \
220 XCHAL_SEP XCHAL_INT28_LEVEL \
221 XCHAL_SEP XCHAL_INT29_LEVEL \
222 XCHAL_SEP XCHAL_INT30_LEVEL \
223 XCHAL_SEP XCHAL_INT31_LEVEL
225 /* Array of types of each possible interrupt: */
226 #define XCHAL_INT_TYPES XCHAL_INT0_TYPE \
227 XCHAL_SEP XCHAL_INT1_TYPE \
228 XCHAL_SEP XCHAL_INT2_TYPE \
229 XCHAL_SEP XCHAL_INT3_TYPE \
230 XCHAL_SEP XCHAL_INT4_TYPE \
231 XCHAL_SEP XCHAL_INT5_TYPE \
232 XCHAL_SEP XCHAL_INT6_TYPE \
233 XCHAL_SEP XCHAL_INT7_TYPE \
234 XCHAL_SEP XCHAL_INT8_TYPE \
235 XCHAL_SEP XCHAL_INT9_TYPE \
236 XCHAL_SEP XCHAL_INT10_TYPE \
237 XCHAL_SEP XCHAL_INT11_TYPE \
238 XCHAL_SEP XCHAL_INT12_TYPE \
239 XCHAL_SEP XCHAL_INT13_TYPE \
240 XCHAL_SEP XCHAL_INT14_TYPE \
241 XCHAL_SEP XCHAL_INT15_TYPE \
242 XCHAL_SEP XCHAL_INT16_TYPE \
243 XCHAL_SEP XCHAL_INT17_TYPE \
244 XCHAL_SEP XCHAL_INT18_TYPE \
245 XCHAL_SEP XCHAL_INT19_TYPE \
246 XCHAL_SEP XCHAL_INT20_TYPE \
247 XCHAL_SEP XCHAL_INT21_TYPE \
248 XCHAL_SEP XCHAL_INT22_TYPE \
249 XCHAL_SEP XCHAL_INT23_TYPE \
250 XCHAL_SEP XCHAL_INT24_TYPE \
251 XCHAL_SEP XCHAL_INT25_TYPE \
252 XCHAL_SEP XCHAL_INT26_TYPE \
253 XCHAL_SEP XCHAL_INT27_TYPE \
254 XCHAL_SEP XCHAL_INT28_TYPE \
255 XCHAL_SEP XCHAL_INT29_TYPE \
256 XCHAL_SEP XCHAL_INT30_TYPE \
257 XCHAL_SEP XCHAL_INT31_TYPE
259 /* Array of masks of interrupts for each type of interrupt: */
260 #define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \
261 XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \
262 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \
263 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \
264 XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \
265 XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \
266 XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR
268 /* Interrupts that can be cleared using the INTCLEAR special register: */
269 #define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
270 /* Interrupts that can be triggered using the INTSET special register: */
271 #define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE
273 /* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */
274 #define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \
275 XCHAL_SEP XCHAL_TIMER1_INTERRUPT \
276 XCHAL_SEP XCHAL_TIMER2_INTERRUPT \
277 XCHAL_SEP XCHAL_TIMER3_INTERRUPT
281 /* For backward compatibility and for the array macros, define macros for
282 * each unconfigured interrupt number (unfortunately, the value of
283 * XTHAL_INTTYPE_UNCONFIGURED is not zero): */
284 #if XCHAL_NUM_INTERRUPTS == 0
285 # define XCHAL_INT0_LEVEL 0
286 # define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED
288 #if XCHAL_NUM_INTERRUPTS <= 1
289 # define XCHAL_INT1_LEVEL 0
290 # define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED
292 #if XCHAL_NUM_INTERRUPTS <= 2
293 # define XCHAL_INT2_LEVEL 0
294 # define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED
296 #if XCHAL_NUM_INTERRUPTS <= 3
297 # define XCHAL_INT3_LEVEL 0
298 # define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED
300 #if XCHAL_NUM_INTERRUPTS <= 4
301 # define XCHAL_INT4_LEVEL 0
302 # define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED
304 #if XCHAL_NUM_INTERRUPTS <= 5
305 # define XCHAL_INT5_LEVEL 0
306 # define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED
308 #if XCHAL_NUM_INTERRUPTS <= 6
309 # define XCHAL_INT6_LEVEL 0
310 # define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED
312 #if XCHAL_NUM_INTERRUPTS <= 7
313 # define XCHAL_INT7_LEVEL 0
314 # define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED
316 #if XCHAL_NUM_INTERRUPTS <= 8
317 # define XCHAL_INT8_LEVEL 0
318 # define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED
320 #if XCHAL_NUM_INTERRUPTS <= 9
321 # define XCHAL_INT9_LEVEL 0
322 # define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED
324 #if XCHAL_NUM_INTERRUPTS <= 10
325 # define XCHAL_INT10_LEVEL 0
326 # define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED
328 #if XCHAL_NUM_INTERRUPTS <= 11
329 # define XCHAL_INT11_LEVEL 0
330 # define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED
332 #if XCHAL_NUM_INTERRUPTS <= 12
333 # define XCHAL_INT12_LEVEL 0
334 # define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED
336 #if XCHAL_NUM_INTERRUPTS <= 13
337 # define XCHAL_INT13_LEVEL 0
338 # define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED
340 #if XCHAL_NUM_INTERRUPTS <= 14
341 # define XCHAL_INT14_LEVEL 0
342 # define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED
344 #if XCHAL_NUM_INTERRUPTS <= 15
345 # define XCHAL_INT15_LEVEL 0
346 # define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED
348 #if XCHAL_NUM_INTERRUPTS <= 16
349 # define XCHAL_INT16_LEVEL 0
350 # define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED
352 #if XCHAL_NUM_INTERRUPTS <= 17
353 # define XCHAL_INT17_LEVEL 0
354 # define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
356 #if XCHAL_NUM_INTERRUPTS <= 18
357 # define XCHAL_INT18_LEVEL 0
358 # define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
360 #if XCHAL_NUM_INTERRUPTS <= 19
361 # define XCHAL_INT19_LEVEL 0
362 # define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
364 #if XCHAL_NUM_INTERRUPTS <= 20
365 # define XCHAL_INT20_LEVEL 0
366 # define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
368 #if XCHAL_NUM_INTERRUPTS <= 21
369 # define XCHAL_INT21_LEVEL 0
370 # define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
372 #if XCHAL_NUM_INTERRUPTS <= 22
373 # define XCHAL_INT22_LEVEL 0
374 # define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
376 #if XCHAL_NUM_INTERRUPTS <= 23
377 # define XCHAL_INT23_LEVEL 0
378 # define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
380 #if XCHAL_NUM_INTERRUPTS <= 24
381 # define XCHAL_INT24_LEVEL 0
382 # define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
384 #if XCHAL_NUM_INTERRUPTS <= 25
385 # define XCHAL_INT25_LEVEL 0
386 # define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
388 #if XCHAL_NUM_INTERRUPTS <= 26
389 # define XCHAL_INT26_LEVEL 0
390 # define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
392 #if XCHAL_NUM_INTERRUPTS <= 27
393 # define XCHAL_INT27_LEVEL 0
394 # define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
396 #if XCHAL_NUM_INTERRUPTS <= 28
397 # define XCHAL_INT28_LEVEL 0
398 # define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
400 #if XCHAL_NUM_INTERRUPTS <= 29
401 # define XCHAL_INT29_LEVEL 0
402 # define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
404 #if XCHAL_NUM_INTERRUPTS <= 30
405 # define XCHAL_INT30_LEVEL 0
406 # define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
408 #if XCHAL_NUM_INTERRUPTS <= 31
409 # define XCHAL_INT31_LEVEL 0
410 # define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
415 * Masks and levels corresponding to each *external* interrupt.
418 #define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM)
419 #define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
420 #define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM)
421 #define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
422 #define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM)
423 #define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
424 #define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM)
425 #define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
426 #define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM)
427 #define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
428 #define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM)
429 #define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
430 #define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM)
431 #define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
432 #define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM)
433 #define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
434 #define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM)
435 #define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
436 #define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM)
437 #define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
438 #define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM)
439 #define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
440 #define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM)
441 #define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
442 #define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM)
443 #define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
444 #define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM)
445 #define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
446 #define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM)
447 #define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
448 #define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM)
449 #define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
450 #define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM)
451 #define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
452 #define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM)
453 #define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
454 #define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM)
455 #define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
456 #define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM)
457 #define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
458 #define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM)
459 #define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
460 #define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM)
461 #define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
462 #define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM)
463 #define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
464 #define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM)
465 #define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
466 #define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM)
467 #define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
468 #define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM)
469 #define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
470 #define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM)
471 #define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
472 #define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM)
473 #define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
474 #define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM)
475 #define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
476 #define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM)
477 #define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
478 #define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM)
479 #define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
480 #define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM)
481 #define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
484 /*----------------------------------------------------------------------
485 EXCEPTIONS and VECTORS
486 ----------------------------------------------------------------------*/
488 /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
489 #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
490 #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
491 #ifdef XCHAL_USER_VECTOR_VADDR
492 #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
493 #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
495 #ifdef XCHAL_USER_VECTOR_PADDR
496 # define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
497 # define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
499 #ifdef XCHAL_KERNEL_VECTOR_VADDR
500 # define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
501 # define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
503 #ifdef XCHAL_KERNEL_VECTOR_PADDR
504 # define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
505 # define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
510 # define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
511 /* This one should only get defined if the corresponding intlevel paddr macro exists: */
512 # define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
516 /* Indexing macros: */
517 #define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
518 #define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
521 * General Exception Causes
522 * (values of EXCCAUSE special register set by general exceptions,
523 * which vector to the user, kernel, or double-exception vectors).
525 * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros
526 * defined in <xtensa/corebits.h>. (Note that these have slightly
527 * different names, they don't just have the XCHAL_ prefix removed.)
529 #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */
530 #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */
531 #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */
532 #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
533 #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
534 #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */
535 #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
536 #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */
537 #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
538 #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */
540 #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
541 #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
542 #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
543 #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */
544 #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */
546 #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */
547 #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */
548 #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */
549 #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */
550 #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */
551 #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */
553 #define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */
554 #define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */
555 #define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */
556 #define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */
557 #define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */
558 #define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */
559 #define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */
560 #define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */
561 #define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */
566 * Miscellaneous special register fields.
568 * For each special register, and each field within each register:
569 * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
570 * XCHAL_<regname>_<field>_BITS is the number of bits in the field.
571 * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
573 * XCHAL_<regname>_<field>_SHIFT is the position of the field within
574 * the register, starting from the least significant bit.
576 * DEPRECATED. Please use the equivalent macros defined in
577 * <xtensa/corebits.h>. (Note that these have different names.)
580 /* DBREAKC (special register number 160): */
581 #define XCHAL_DBREAKC_VALIDMASK 0xC000003F
582 #define XCHAL_DBREAKC_MASK_BITS 6
583 #define XCHAL_DBREAKC_MASK_NUM 64
584 #define XCHAL_DBREAKC_MASK_SHIFT 0
585 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F
586 #define XCHAL_DBREAKC_LOADBREAK_BITS 1
587 #define XCHAL_DBREAKC_LOADBREAK_NUM 2
588 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30
589 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000
590 #define XCHAL_DBREAKC_STOREBREAK_BITS 1
591 #define XCHAL_DBREAKC_STOREBREAK_NUM 2
592 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31
593 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000
594 /* PS (special register number 230): */
595 #define XCHAL_PS_VALIDMASK 0x00070F3F
596 #define XCHAL_PS_INTLEVEL_BITS 4
597 #define XCHAL_PS_INTLEVEL_NUM 16
598 #define XCHAL_PS_INTLEVEL_SHIFT 0
599 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F
600 #define XCHAL_PS_EXCM_BITS 1
601 #define XCHAL_PS_EXCM_NUM 2
602 #define XCHAL_PS_EXCM_SHIFT 4
603 #define XCHAL_PS_EXCM_MASK 0x00000010
604 #define XCHAL_PS_UM_BITS 1
605 #define XCHAL_PS_UM_NUM 2
606 #define XCHAL_PS_UM_SHIFT 5
607 #define XCHAL_PS_UM_MASK 0x00000020
608 #define XCHAL_PS_RING_BITS 2
609 #define XCHAL_PS_RING_NUM 4
610 #define XCHAL_PS_RING_SHIFT 6
611 #define XCHAL_PS_RING_MASK 0x000000C0
612 #define XCHAL_PS_OWB_BITS 4
613 #define XCHAL_PS_OWB_NUM 16
614 #define XCHAL_PS_OWB_SHIFT 8
615 #define XCHAL_PS_OWB_MASK 0x00000F00
616 #define XCHAL_PS_CALLINC_BITS 2
617 #define XCHAL_PS_CALLINC_NUM 4
618 #define XCHAL_PS_CALLINC_SHIFT 16
619 #define XCHAL_PS_CALLINC_MASK 0x00030000
620 #define XCHAL_PS_WOE_BITS 1
621 #define XCHAL_PS_WOE_NUM 2
622 #define XCHAL_PS_WOE_SHIFT 18
623 #define XCHAL_PS_WOE_MASK 0x00040000
624 /* EXCCAUSE (special register number 232): */
625 #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F
626 #define XCHAL_EXCCAUSE_BITS 6
627 #define XCHAL_EXCCAUSE_NUM 64
628 #define XCHAL_EXCCAUSE_SHIFT 0
629 #define XCHAL_EXCCAUSE_MASK 0x0000003F
630 /* DEBUGCAUSE (special register number 233): */
631 #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F
632 #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1
633 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2
634 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0
635 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001
636 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1
637 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2
638 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1
639 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002
640 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1
641 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2
642 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2
643 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004
644 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1
645 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2
646 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3
647 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008
648 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1
649 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2
650 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4
651 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010
652 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1
653 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2
654 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5
655 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020
660 /*----------------------------------------------------------------------
662 ----------------------------------------------------------------------*/
664 /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
668 /*----------------------------------------------------------------------
669 INTERNAL I/D RAM/ROMs and XLMI
670 ----------------------------------------------------------------------*/
672 #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
673 #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
674 #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
675 #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
677 #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */
678 #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */
679 #define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */
680 #define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */
681 #define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */
682 #define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */
683 #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
684 #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
685 #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
686 #define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */
687 #define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */
688 #define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */
689 #define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */
690 #define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */
691 #define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */
692 #define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */
693 #define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */
694 #define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */
695 #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
696 #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
697 #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
698 #define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */
699 #define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */
700 #define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */
704 /*----------------------------------------------------------------------
706 ----------------------------------------------------------------------*/
709 /* Max for both I-cache and D-cache (used for general alignment): */
710 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
711 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH
712 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE
714 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH
715 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
718 #define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH)
719 #define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH)
720 /* Max for both I and D caches (used for cache-coherency page alignment): */
721 #if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
722 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH
723 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE
725 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH
726 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE
729 /* Instruction cache tag bits: */
730 #define XCHAL_ICACHE_TAG_V_SHIFT 0
731 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */
732 #if XCHAL_ICACHE_WAYS > 1
733 # define XCHAL_ICACHE_TAG_F_SHIFT 1
734 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */
736 # define XCHAL_ICACHE_TAG_F_SHIFT 0
737 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */
739 #if XCHAL_ICACHE_LINE_LOCKABLE
740 # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1)
741 # define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */
743 # define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT
744 # define XCHAL_ICACHE_TAG_L 0 /* no lock bit */
746 /* Data cache tag bits: */
747 #define XCHAL_DCACHE_TAG_V_SHIFT 0
748 #define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */
749 #if XCHAL_DCACHE_WAYS > 1
750 # define XCHAL_DCACHE_TAG_F_SHIFT 1
751 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */
753 # define XCHAL_DCACHE_TAG_F_SHIFT 0
754 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */
756 #if XCHAL_DCACHE_IS_WRITEBACK
757 # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1)
758 # define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */
760 # define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT
761 # define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */
763 #if XCHAL_DCACHE_LINE_LOCKABLE
764 # define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1)
765 # define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */
767 # define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT
768 # define XCHAL_DCACHE_TAG_L 0 /* no lock bit */
772 /*----------------------------------------------------------------------
774 ----------------------------------------------------------------------*/
776 /* See <xtensa/config/core-matmap.h> for more details. */
778 #define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
780 /* Indexing macros: */
781 #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
782 #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
783 #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
784 #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
785 #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
786 #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
787 #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
788 #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
790 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
791 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
794 /* Number of entries per autorefill way: */
795 #define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
796 #define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
799 * Determine whether we have a full MMU (with Page Table and Protection)
800 * usable for an MMU-based OS:
803 #if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
804 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
806 # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
811 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
813 #if XCHAL_HAVE_PTP_MMU
814 #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
815 #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
816 #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
817 #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
818 #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
819 #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
821 #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
822 #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
823 #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
824 #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
825 #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
826 #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
828 #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
829 #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
830 /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
834 /*----------------------------------------------------------------------
836 ----------------------------------------------------------------------*/
838 /* Data alignment required if used for instructions: */
839 #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
840 # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH
842 # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH
846 * Names kept for backward compatibility.
847 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
848 * under which they are released. In the T10##.# era there was no distinction.)
850 #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR
851 #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR
852 #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME
857 /*----------------------------------------------------------------------
858 COPROCESSORS and EXTRA STATE
859 ----------------------------------------------------------------------*/
861 #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE
862 #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN
863 #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE
864 #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN
866 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
868 #define xchal_extratie_load xchal_ncptie_load
869 #define xchal_extratie_store xchal_ncptie_store
870 #define xchal_extratie_load_a2 xchal_ncptie_load_a2
871 #define xchal_extratie_store_a2 xchal_ncptie_store_a2
872 #define xchal_extra_load xchal_ncp_load
873 #define xchal_extra_store xchal_ncp_store
874 #define xchal_extra_load_a2 xchal_ncp_load_a2
875 #define xchal_extra_store_a2 xchal_ncp_store_a2
876 #define xchal_extra_load_funcbody xchal_ncp_load_a2
877 #define xchal_extra_store_funcbody xchal_ncp_store_a2
879 /* Empty placeholder macros for undefined coprocessors: */
880 # ifndef XCHAL_CP0_NAME
881 # define xchal_cp0_store_a2 xchal_cp0_store a2, a3
882 # define xchal_cp0_load_a2 xchal_cp0_load a2, a3
883 .macro xchal_cp0_store ptr tmp
885 .macro xchal_cp0_load ptr tmp
888 # ifndef XCHAL_CP1_NAME
889 # define xchal_cp1_store_a2 xchal_cp1_store a2, a3
890 # define xchal_cp1_load_a2 xchal_cp1_load a2, a3
891 .macro xchal_cp1_store ptr tmp
893 .macro xchal_cp1_load ptr tmp
896 # ifndef XCHAL_CP2_NAME
897 # define xchal_cp2_store_a2 xchal_cp2_store a2, a3
898 # define xchal_cp2_load_a2 xchal_cp2_load a2, a3
899 .macro xchal_cp2_store ptr tmp
901 .macro xchal_cp2_load ptr tmp
904 # ifndef XCHAL_CP3_NAME
905 # define xchal_cp3_store_a2 xchal_cp3_store a2, a3
906 # define xchal_cp3_load_a2 xchal_cp3_load a2, a3
907 .macro xchal_cp3_store ptr tmp
909 .macro xchal_cp3_load ptr tmp
912 # ifndef XCHAL_CP4_NAME
913 # define xchal_cp4_store_a2 xchal_cp4_store a2, a3
914 # define xchal_cp4_load_a2 xchal_cp4_load a2, a3
915 .macro xchal_cp4_store ptr tmp
917 .macro xchal_cp4_load ptr tmp
920 # ifndef XCHAL_CP5_NAME
921 # define xchal_cp5_store_a2 xchal_cp5_store a2, a3
922 # define xchal_cp5_load_a2 xchal_cp5_load a2, a3
923 .macro xchal_cp5_store ptr tmp
925 .macro xchal_cp5_load ptr tmp
928 # ifndef XCHAL_CP6_NAME
929 # define xchal_cp6_store_a2 xchal_cp6_store a2, a3
930 # define xchal_cp6_load_a2 xchal_cp6_load a2, a3
931 .macro xchal_cp6_store ptr tmp
933 .macro xchal_cp6_load ptr tmp
936 # ifndef XCHAL_CP7_NAME
937 # define xchal_cp7_store_a2 xchal_cp7_store a2, a3
938 # define xchal_cp7_load_a2 xchal_cp7_load a2, a3
939 .macro xchal_cp7_store ptr tmp
941 .macro xchal_cp7_load ptr tmp
945 /********************
946 * Macros to create functions that save and restore the state of *any* TIE
947 * coprocessor (by dynamic index).
951 * Macro that expands to the body of a function
952 * that stores the selected coprocessor's state (registers etc).
953 * Entry: a2 = ptr to save area in which to save cp state
954 * a3 = coprocessor number
955 * Exit: any register a2-a15 (?) may have been clobbered.
957 .macro xchal_cpi_store_funcbody
958 # ifdef XCHAL_CP0_NAME
964 # ifdef XCHAL_CP1_NAME
970 # ifdef XCHAL_CP2_NAME
976 # ifdef XCHAL_CP3_NAME
982 # ifdef XCHAL_CP4_NAME
988 # ifdef XCHAL_CP5_NAME
994 # ifdef XCHAL_CP6_NAME
1000 # ifdef XCHAL_CP7_NAME
1010 * Macro that expands to the body of a function
1011 * that loads the selected coprocessor's state (registers etc).
1012 * Entry: a2 = ptr to save area from which to restore cp state
1013 * a3 = coprocessor number
1014 * Exit: any register a2-a15 (?) may have been clobbered.
1016 .macro xchal_cpi_load_funcbody
1017 # ifdef XCHAL_CP0_NAME
1023 # ifdef XCHAL_CP1_NAME
1029 # ifdef XCHAL_CP2_NAME
1035 # ifdef XCHAL_CP3_NAME
1041 # ifdef XCHAL_CP4_NAME
1047 # ifdef XCHAL_CP5_NAME
1053 # ifdef XCHAL_CP6_NAME
1059 # ifdef XCHAL_CP7_NAME
1068 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/
1071 /* Other default macros for undefined coprocessors: */
1072 #ifndef XCHAL_CP0_NAME
1073 # define XCHAL_CP0_SA_SIZE 0
1074 # define XCHAL_CP0_SA_ALIGN 1
1075 # define XCHAL_CP0_NAME 0
1076 # define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
1077 # define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
1079 #ifndef XCHAL_CP1_NAME
1080 # define XCHAL_CP1_SA_SIZE 0
1081 # define XCHAL_CP1_SA_ALIGN 1
1082 # define XCHAL_CP1_NAME 0
1083 # define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
1084 # define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
1086 #ifndef XCHAL_CP2_NAME
1087 # define XCHAL_CP2_SA_SIZE 0
1088 # define XCHAL_CP2_SA_ALIGN 1
1089 # define XCHAL_CP2_NAME 0
1090 # define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
1091 # define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
1093 #ifndef XCHAL_CP3_NAME
1094 # define XCHAL_CP3_SA_SIZE 0
1095 # define XCHAL_CP3_SA_ALIGN 1
1096 # define XCHAL_CP3_NAME 0
1097 # define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
1098 # define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
1100 #ifndef XCHAL_CP4_NAME
1101 # define XCHAL_CP4_SA_SIZE 0
1102 # define XCHAL_CP4_SA_ALIGN 1
1103 # define XCHAL_CP4_NAME 0
1104 # define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
1105 # define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
1107 #ifndef XCHAL_CP5_NAME
1108 # define XCHAL_CP5_SA_SIZE 0
1109 # define XCHAL_CP5_SA_ALIGN 1
1110 # define XCHAL_CP5_NAME 0
1111 # define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
1112 # define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
1114 #ifndef XCHAL_CP6_NAME
1115 # define XCHAL_CP6_SA_SIZE 0
1116 # define XCHAL_CP6_SA_ALIGN 1
1117 # define XCHAL_CP6_NAME 0
1118 # define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
1119 # define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
1121 #ifndef XCHAL_CP7_NAME
1122 # define XCHAL_CP7_SA_SIZE 0
1123 # define XCHAL_CP7_SA_ALIGN 1
1124 # define XCHAL_CP7_NAME 0
1125 # define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
1126 # define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
1129 /* Indexing macros: */
1130 #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
1131 #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
1132 #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
1133 #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
1135 #define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */
1137 /* Link-time HAL global variables that report coprocessor numbers by name
1138 (names are case-preserved from the original TIE): */
1139 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
1140 # define _XCJOIN(a,b) a ## b
1141 # define XCJOIN(a,b) _XCJOIN(a,b)
1142 # ifdef XCHAL_CP0_NAME
1143 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
1144 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
1146 # ifdef XCHAL_CP1_NAME
1147 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
1148 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
1150 # ifdef XCHAL_CP2_NAME
1151 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
1152 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
1154 # ifdef XCHAL_CP3_NAME
1155 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
1156 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
1158 # ifdef XCHAL_CP4_NAME
1159 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
1160 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
1162 # ifdef XCHAL_CP5_NAME
1163 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
1164 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
1166 # ifdef XCHAL_CP6_NAME
1167 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
1168 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
1170 # ifdef XCHAL_CP7_NAME
1171 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
1172 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
1179 /*----------------------------------------------------------------------
1181 ----------------------------------------------------------------------*/
1184 #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
1185 #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
1186 #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
1188 #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
1189 #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
1190 #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
1192 /* Belongs in xtensa/hal.h: */
1193 #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
1197 * Because information as to exactly which hardware version is targeted
1198 * by a given software build is not always available, compile-time HAL
1199 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
1200 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
1201 * under which they are released. In the T10##.# era there was no distinction.)
1203 #if XCHAL_HW_CONFIGID_RELIABLE
1204 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
1205 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
1206 # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
1207 # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
1209 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
1210 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
1212 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
1213 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
1215 # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
1216 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
1217 # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
1225 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
1226 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
1228 #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
1229 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
1230 || XCHAL_HW_RELEASE_AT(1050,0)))
1234 #endif /*XTENSA_CONFIG_CORE_H*/