2 * Copyright (c) 2013 Tensilica Inc.
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12 * The above copyright notice and this permission notice shall be included
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24 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
26 * NOTE: This header file is not meant to be included directly.
30 * This header file describes this specific Xtensa processor's TIE extensions
31 * that extend basic Xtensa core functionality. It is customized to this
32 * Xtensa processor configuration.
35 #ifndef _XTENSA_CORE_TIE_H
36 #define _XTENSA_CORE_TIE_H
38 #define XCHAL_CP_NUM 0 /* number of coprocessors */
39 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
40 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
41 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
43 /* Save area for non-coprocessor optional and custom (TIE) state: */
44 #define XCHAL_NCP_SA_SIZE 4
45 #define XCHAL_NCP_SA_ALIGN 4
47 /* Total save area for optional and custom state (NCP + CPn): */
48 #define XCHAL_TOTAL_SA_SIZE 16 /* with 16-byte align padding */
49 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
52 * Detailed contents of save areas.
53 * NOTE: caller must define the XCHAL_SA_{UREG,SREG,REGF} macros (they
54 * are not defined here) before expanding the XCHAL_SA_xxx_LIST macros.
56 * XCHAL_SA_SREG(dbnum,offset,size,contentsz,align,name,sregnum,bitmask,x,x)
57 * XCHAL_SA_UREG(dbnum,offset,size,contentsz,align,name,uregnum,bitmask,x,x)
58 * XCHAL_SA_REGF(dbnum,offset,size,contentsz,align,name,index,span,x,x,
59 * basename,regf_name,regf_numentries)
62 #define XCHAL_SA_NCP_NUM 1
63 #define XCHAL_SA_NCP_LIST \
64 XCHAL_SA_SREG(0x020C, 0, 4, 4, 4, scompare1, 12,0xFFFFFFFF,0,0)
66 /* Byte length of instruction from its first nibble (op0 field), per FLIX. */
67 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
69 #endif /*_XTENSA_CORE_TIE_H*/