2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
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13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "usb_table.h"
42 #define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211
43 #define VERIFY_CHECKSUM_BY_BOOTCODE 1
45 /***********************************************************************/
46 /* for SEEPROM Boot */
47 /***********************************************************************/
48 #define WLAN_BOOT_SIGNATURE (0x19710303)
50 #define WLAN_SIGNATURE_ADDR (0x102000)
52 #define cMAX_ADDR 0x10000
54 #define cEEPROM_SIZE 0x800 // 2k word (4k byte)
56 #define cRESERVE_LOAD_SPACE 0
58 // start addr. of boot code
59 #define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800
61 /************************** Register Addr Process *********************/
62 #define mpADDR(addr) ((volatile uint16_t*) (addr))
63 #define mADDR(addr) (*mpADDR(addr))
64 #define muADDR(addr) ((uint16_t) (&(addr)))
66 #define USB_BYTE_REG_WRITE(addr, val) iowrite8_usb(addr, val)
67 #define USB_BYTE_REG_READ(addr) ioread8_usb(addr)
69 #define USB_HALF_WORD_REG_WRITE(addr, val) iowrite16_usb(addr, val)
70 #define USB_HALF_WORD_REG_READ(addr) ioread16_usb(addr)
72 #define USB_WORD_REG_WRITE(addr, val) iowrite32_usb(addr, val)
73 #define USB_WORD_REG_READ(addr) ioread32_usb(addr)
76 /************************** Register Deinition ***************************/
77 //#define USB_BASE_ADDR_SOC 0x8000
79 //#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC)
81 #define cSOC_USB_OFST (0x100)
83 #define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0
85 #define cSOC_CBUS_CTL_OFFSET 0xF0
87 #define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS
89 #define ZM_MAIN_CTRL_OFFSET 0x00
90 #define ZM_DEVICE_ADDRESS_OFFSET 0x01
91 #define ZM_TEST_OFFSET 0x02
92 #define ZM_PHY_TEST_SELECT_OFFSET 0x08
93 #define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A
94 #define ZM_CX_CONFIG_STATUS_OFFSET 0x0B
95 #define ZM_EP0_DATA1_OFFSET 0x0C
96 #define ZM_EP0_DATA2_OFFSET 0x0D
97 #define ZM_EP0_DATA_OFFSET 0x0C
99 #define ZM_INTR_MASK_BYTE_0_OFFSET 0x11
100 #define ZM_INTR_MASK_BYTE_1_OFFSET 0x12
101 #define ZM_INTR_MASK_BYTE_2_OFFSET 0x13
102 #define ZM_INTR_MASK_BYTE_3_OFFSET 0x14
103 #define ZM_INTR_MASK_BYTE_4_OFFSET 0x15
104 #define ZM_INTR_MASK_BYTE_5_OFFSET 0x16
105 #define ZM_INTR_MASK_BYTE_6_OFFSET 0x17
106 #define ZM_INTR_MASK_BYTE_7_OFFSET 0x18
108 #define ZM_INTR_GROUP_OFFSET 0x20
109 #define ZM_INTR_SOURCE_0_OFFSET 0x21
110 #define ZM_INTR_SOURCE_1_OFFSET 0x22
111 #define ZM_INTR_SOURCE_2_OFFSET 0x23
112 #define ZM_INTR_SOURCE_3_OFFSET 0x24
113 #define ZM_INTR_SOURCE_4_OFFSET 0x25
114 #define ZM_INTR_SOURCE_5_OFFSET 0x26
115 #define ZM_INTR_SOURCE_6_OFFSET 0x27
116 #define ZM_INTR_SOURCE_7_OFFSET 0x28
118 #define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F
119 #define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E
121 #define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F
122 #define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E
124 #define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE
125 #define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE
126 #define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF
127 #define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF
129 #define ZM_EP3_DATA_OFFSET 0xF8
130 #define ZM_EP4_DATA_OFFSET 0xFC
132 #define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108
133 #define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110
134 #define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114
135 #define ZM_SOC_USB_DMA_RESET_OFFSET 0x118
137 #define ZM_ADDR_CONV 0x0
139 #define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
141 #define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
143 #define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
145 #define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
147 #define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV)
149 #define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
151 #define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
153 #define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
155 #define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
157 #define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
159 #define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
161 #define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
163 #define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
165 #define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
167 #define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
169 #define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
171 #define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
173 #define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
175 #define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
177 #define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
179 #define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
181 #define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
183 #define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
185 #define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
187 #define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
189 #define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
191 #define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
193 #define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
195 #define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
197 #define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
199 #define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
201 #define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET)
203 #define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET)
205 #define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET)
207 #define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
209 #define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET)
211 #define bmHIGH_SPEED BIT6
212 #define bmCWR_BUF_END BIT1
214 #define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
215 //#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG
216 //#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG
217 //#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG
218 #define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
219 #define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
221 #define mGetByte0(data) ( data & 0xff )
222 #define mGetByte1(data) ( (data >> 8) & 0xff )
223 #define mGetByte2(data) ( (data >> 16) & 0xff )
224 #define mGetByte3(data) ( (data >> 24) & 0xff )
226 //#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6)
227 //#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7)
228 //#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
229 //#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
231 #define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
232 #define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
233 #define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
234 #define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
236 #define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
237 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
238 #define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
239 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
240 #define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
241 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
243 #define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
244 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
246 #define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
247 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
248 #define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
249 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
250 #define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
251 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
252 #define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
253 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
254 // USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
256 #define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
257 USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
261 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
262 #define HS_C1_I0_A0_EP1_bInterval 00
264 #define HS_C1_I0_A0_EP_NUMBER 0x06
265 #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
266 #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
267 #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
269 #define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH)
270 #define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH)
272 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
273 //#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval
275 #define HS_CONFIGURATION_NUMBER 1
276 #define FS_CONFIGURATION_NUMBER 1
278 #define fDOUBLE_BUF 1
279 #define fDOUBLE_BUF_IN 1
281 #define fFLASH_DISK 0
282 #define fENABLE_ISO 0
284 #if (HS_CONFIGURATION_NUMBER >= 1)
285 // Configuration 0X01
286 #define HS_C1_INTERFACE_NUMBER 0x01
288 #define HS_C1_iConfiguration 0x00
289 #define HS_C1_bmAttribute 0x80
290 #if !(fFLASH_DISK && !fFLASH_BOOT)
291 #define HS_C1_iMaxPower 0xFA
293 #define HS_C1_iMaxPower 0x32
296 #if (HS_C1_INTERFACE_NUMBER >= 1)
298 #define HS_C1_I0_ALT_NUMBER 0X01
299 #if (HS_C1_I0_ALT_NUMBER >= 1)
300 // AlternateSetting 0X00
301 #define HS_C1_I0_A0_bInterfaceNumber 0X00
302 #define HS_C1_I0_A0_bAlternateSetting 0X00
304 //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
305 #define HS_C1_I0_A0_EP_NUMBER 0x06
307 //#define HS_C1_I0_A0_EP_NUMBER 0X03
309 #if !(fFLASH_DISK && !fFLASH_BOOT)
310 #define HS_C1_I0_A0_bInterfaceClass 0XFF
311 #define HS_C1_I0_A0_bInterfaceSubClass 0X00
312 #define HS_C1_I0_A0_bInterfaceProtocol 0X00
314 #define HS_C1_I0_A0_bInterfaceClass 0X08
315 #define HS_C1_I0_A0_bInterfaceSubClass 0X06
316 #define HS_C1_I0_A0_bInterfaceProtocol 0X50
318 #define HS_C1_I0_A0_iInterface 0X00
320 #if (HS_C1_I0_A0_EP_NUMBER >= 1)
322 #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
325 #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
327 #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
329 #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
330 #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
332 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
333 #define HS_C1_I0_A0_EP1_bInterval 00
335 #if (HS_C1_I0_A0_EP_NUMBER >= 2)
337 #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
340 #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
342 #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
344 #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
345 #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
346 #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
347 #define HS_C1_I0_A0_EP2_bInterval 00
349 #if (HS_C1_I0_A0_EP_NUMBER >= 3)
351 #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
352 #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
353 #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
354 #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
355 #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
356 #define HS_C1_I0_A0_EP3_bInterval 01
358 // Note: HS Bulk type require max pkt size = 512
359 // ==> must use Interrupt type for max pkt size = 64
360 #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
362 #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
363 #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
364 #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
365 #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT
366 #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
367 #define HS_C1_I0_A0_EP4_bInterval 01
369 #if (HS_C1_I0_A0_EP_NUMBER >= 5)
371 #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
373 #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
375 #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
377 #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
378 #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
379 #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
380 #define HS_C1_I0_A0_EP5_bInterval 00
382 #if (HS_C1_I0_A0_EP_NUMBER >= 6)
384 #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
386 #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
388 #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
390 #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
391 #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
392 #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
393 #define HS_C1_I0_A0_EP6_bInterval 00
399 #if (HS_CONFIGURATION_NUMBER >= 1)
401 #if (HS_C1_INTERFACE_NUMBER >= 1)
403 #if (HS_C1_I0_ALT_NUMBER >= 1)
404 // AlternateSetting 0
405 #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
406 #if (HS_C1_I0_A0_EP_NUMBER >= 1)
408 #define HS_C1_I0_A0_EP1_FIFO_START FIFO0
409 #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
410 #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
411 #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
412 #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
414 #if (HS_C1_I0_A0_EP_NUMBER >= 2)
417 #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
419 #define HS_C1_I0_A0_EP2_FIFO_START FIFO2
421 #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
422 #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
423 #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
424 #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
426 #if (HS_C1_I0_A0_EP_NUMBER >= 3)
429 // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
430 #define HS_C1_I0_A0_EP3_FIFO_START FIFO14
431 #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
432 #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
433 #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
434 #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
436 #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
438 #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
439 #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
440 #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
441 #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
442 #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
444 #if (HS_C1_I0_A0_EP_NUMBER >= 5)
446 #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
447 #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
448 #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
449 #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
450 #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
452 #if (HS_C1_I0_A0_EP_NUMBER >= 6)
454 #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
455 #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
456 #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
457 #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
458 #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
462 #if (HS_C1_I0_ALT_NUMBER >= 2)
463 // AlternateSetting 1
464 #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
465 #if (HS_C1_I0_A1_EP_NUMBER >= 1)
467 #define HS_C1_I0_A1_EP1_FIFO_START FIFO0
468 #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
469 #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
470 #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
471 #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
473 #if (HS_C1_I0_A1_EP_NUMBER >= 2)
475 #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
476 #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
477 #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
478 #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
479 #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
481 #if (HS_C1_I0_A1_EP_NUMBER >= 3)
483 #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
484 #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
485 #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
486 #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
487 #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
491 #if (HS_C1_I0_ALT_NUMBER == 1)
492 #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
493 #elif (HS_C1_I0_ALT_NUMBER == 2)
494 #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
498 #if (HS_C1_INTERFACE_NUMBER >= 2)
500 #if (HS_C1_I1_ALT_NUMBER >= 1)
501 // AlternateSetting 0
502 #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
503 #if (HS_C1_I1_A0_EP_NUMBER >= 1)
505 #define HS_C1_I1_A0_EP1_FIFO_START FIFO0
506 #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
507 #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
508 #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
509 #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
511 #if (HS_C1_I1_A0_EP_NUMBER >= 2)
513 #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
514 #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
515 #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
516 #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
517 #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
519 #if (HS_C1_I1_A0_EP_NUMBER >= 3)
521 #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
522 #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
523 #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
524 #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
525 #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
529 #if (HS_C1_I1_ALT_NUMBER >= 2)
530 // AlternateSetting 1
531 #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
532 #if (HS_C1_I1_A1_EP_NUMBER >= 1)
534 #define HS_C1_I1_A1_EP1_FIFO_START FIFO0
535 #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
536 #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
537 #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
538 #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
540 #if (HS_C1_I1_A1_EP_NUMBER >= 2)
542 #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
543 #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
544 #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
545 #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
546 #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
548 #if (HS_C1_I1_A1_EP_NUMBER >= 3)
550 #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
551 #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
552 #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
553 #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
554 #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
558 #if (HS_C1_I1_ALT_NUMBER == 1)
559 #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH)
560 #elif (HS_C1_I1_ALT_NUMBER == 2)
561 #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
565 #if (HS_C1_INTERFACE_NUMBER == 1)
566 #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
567 #elif (HS_C1_INTERFACE_NUMBER == 2)
568 #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
572 #if (FS_CONFIGURATION_NUMBER >= 1)
573 // Configuration 0X01
574 #define FS_C1_INTERFACE_NUMBER 0X01
576 #define FS_C1_iConfiguration 0X00
577 #define FS_C1_bmAttribute 0X80
578 #define FS_C1_iMaxPower 0XFA
580 #if (FS_C1_INTERFACE_NUMBER >= 1)
582 #define FS_C1_I0_ALT_NUMBER 0X01
583 #if (FS_C1_I0_ALT_NUMBER >= 1)
584 // AlternateSetting 0X00
585 #define FS_C1_I0_A0_bInterfaceNumber 0X00
586 #define FS_C1_I0_A0_bAlternateSetting 0X00
588 //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
589 #define FS_C1_I0_A0_EP_NUMBER 0x05
591 //#define FS_C1_I0_A0_EP_NUMBER 0X03
593 #if !(fFLASH_DISK && !fFLASH_BOOT)
594 #define FS_C1_I0_A0_bInterfaceClass 0XFF
595 #define FS_C1_I0_A0_bInterfaceSubClass 0X00
596 #define FS_C1_I0_A0_bInterfaceProtocol 0X00
598 #define FS_C1_I0_A0_bInterfaceClass 0X08
599 #define FS_C1_I0_A0_bInterfaceSubClass 0X06
600 #define FS_C1_I0_A0_bInterfaceProtocol 0X50
602 #define FS_C1_I0_A0_iInterface 0X00
604 #if (FS_C1_I0_A0_EP_NUMBER >= 1)
606 #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
609 #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
611 #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
613 #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
614 #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
616 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
617 #define FS_C1_I0_A0_EP1_bInterval 00
619 #if (FS_C1_I0_A0_EP_NUMBER >= 2)
621 #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
624 #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
626 #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
628 #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
629 #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
630 #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
631 #define FS_C1_I0_A0_EP2_bInterval 00
633 #if (FS_C1_I0_A0_EP_NUMBER >= 3)
635 #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
636 #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
637 #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
638 #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
639 #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
640 #define FS_C1_I0_A0_EP3_bInterval 01
642 #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
644 #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
645 #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
646 #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
647 #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK
648 #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
649 #define FS_C1_I0_A0_EP4_bInterval 00
651 #if (FS_C1_I0_A0_EP_NUMBER >= 5)
653 #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
655 #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
657 #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
659 #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
660 #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
661 #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
662 #define FS_C1_I0_A0_EP5_bInterval 00
664 #if (FS_C1_I0_A0_EP_NUMBER >= 6)
666 #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
668 #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
670 #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
672 #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
673 #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
674 #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
675 #define FS_C1_I0_A0_EP6_bInterval 00
681 #if (FS_CONFIGURATION_NUMBER >= 1)
683 #if (FS_C1_INTERFACE_NUMBER >= 1)
685 #if (FS_C1_I0_ALT_NUMBER >= 1)
686 // AlternateSetting 0
687 #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
688 #if (FS_C1_I0_A0_EP_NUMBER >= 1)
690 #define FS_C1_I0_A0_EP1_FIFO_START FIFO0
691 #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
692 #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
693 #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
694 #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
696 #if (FS_C1_I0_A0_EP_NUMBER >= 2)
698 #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
699 #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
700 #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
701 #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
702 #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
704 #if (FS_C1_I0_A0_EP_NUMBER >= 3)
707 // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
708 #define FS_C1_I0_A0_EP3_FIFO_START FIFO14
709 #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
710 #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
711 #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
712 #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
714 #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
716 #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
717 #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
718 #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
719 #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
720 #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
722 #if (FS_C1_I0_A0_EP_NUMBER >= 5)
724 #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
725 #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
726 #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
727 #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
728 #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
730 #if (FS_C1_I0_A0_EP_NUMBER >= 6)
732 #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
733 #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
734 #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
735 #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
736 #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
740 #if (FS_C1_I0_ALT_NUMBER >= 2)
741 // AlternateSetting 1
742 #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
743 #if (FS_C1_I0_A1_EP_NUMBER >= 1)
745 #define FS_C1_I0_A1_EP1_FIFO_START FIFO0
746 #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
747 #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
748 #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
749 #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
751 #if (FS_C1_I0_A1_EP_NUMBER >= 2)
753 #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
754 #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
755 #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
756 #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
757 #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
759 #if (FS_C1_I0_A1_EP_NUMBER >= 3)
761 #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
762 #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
763 #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
764 #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
765 #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
769 #if (FS_C1_I0_ALT_NUMBER == 1)
770 #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH)
771 #elif (FS_C1_I0_ALT_NUMBER == 2)
772 #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
776 #if (FS_C1_INTERFACE_NUMBER >= 2)
778 #if (FS_C1_I1_ALT_NUMBER >= 1)
779 // AlternateSetting 0
780 #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
781 #if (FS_C1_I1_A0_EP_NUMBER >= 1)
783 #define FS_C1_I1_A0_EP1_FIFO_START FIFO0
784 #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
785 #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
786 #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
787 #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
789 #if (FS_C1_I1_A0_EP_NUMBER >= 2)
791 #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
792 #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
793 #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
794 #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
795 #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
797 #if (FS_C1_I1_A0_EP_NUMBER >= 3)
799 #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
800 #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
801 #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
802 #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
803 #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
807 #if (FS_C1_I1_ALT_NUMBER >= 2)
808 // AlternateSetting 1
809 #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
810 #if (FS_C1_I1_A1_EP_NUMBER >= 1)
812 #define FS_C1_I1_A1_EP1_FIFO_START FIFO0
813 #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
814 #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
815 #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
816 #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
818 #if (FS_C1_I1_A1_EP_NUMBER >= 2)
820 #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
821 #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
822 #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
823 #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
824 #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
826 #if (FS_C1_I1_A1_EP_NUMBER >= 3)
828 #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
829 #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
830 #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
831 #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
832 #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
836 #if (FS_C1_I1_ALT_NUMBER == 1)
837 #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH)
838 #elif (FS_C1_I1_ALT_NUMBER == 2)
839 #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
843 #if (FS_C1_INTERFACE_NUMBER == 1)
844 #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH)
845 #elif (FS_C1_INTERFACE_NUMBER == 2)
846 #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
850 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
851 #define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
852 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
854 #define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
855 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
857 #define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
858 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode
860 #define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
861 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode
863 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
864 #define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
865 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable
867 #define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
868 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable
870 #define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
871 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode
873 #define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
874 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode
876 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
877 #define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
878 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
880 #define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
881 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
883 #define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
884 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode
886 #define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
887 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode
889 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
890 #define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
892 #define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
894 #define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode
896 #define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode
898 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
900 #define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \
901 USB_UP_PACKET_MODE(); \
904 #define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \
905 USB_LP_DN_PACKET_MODE(); \
906 USB_ENABLE_LP_DN_DMA()
908 #define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \
909 USB_MP_DN_PACKET_MODE(); \
910 USB_ENABLE_MP_DN_DMA();
912 #define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \
913 USB_HP_DN_PACKET_MODE(); \
914 USB_ENABLE_HP_DN_DMA();
916 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
917 #define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \
918 USB_UP_STREAM_MODE(); \
921 #define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \
922 USB_LP_DN_STREAM_MODE(); \
923 USB_ENABLE_LP_DN_DMA()
925 #define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \
926 USB_MP_DN_STREAM_MODE(); \
927 USB_ENABLE_MP_DN_DMA();
929 #define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \
930 USB_HP_DN_STREAM_MODE(); \
931 USB_ENABLE_HP_DN_DMA();
933 #define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
934 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
935 #define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea
936 #define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea