4 #define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \
5 typedef char assertion_name[(predicate) ? 1 : -1];
8 #if 0 /* At least for now, simplify debugging. */
16 #define NULL (void *)0
28 #define __ATTRIB_PACK __attribute__ ((packed))
29 #define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
30 #define __ATTRIB_NORETURN __attribute__ ((noreturn))
31 #define __ATTRIB_ALIGN(x) __attribute__ ((aligned((x))))
32 #define INLINE __inline__
35 #define __ATTRIB_PRINTF
36 #define __ATTRIB_NORETURN
37 #define __ATTRIB_ALIGN(x)
38 #define INLINE __inline
39 #endif /* End __GNUC__ */
42 #define POSTPACK __ATTRIB_PACK
45 #define A_SWAB32(_x) ( \
47 (((A_UINT32)(_x) & (A_UINT32)0x000000ffUL) << 24) | \
48 (((A_UINT32)(_x) & (A_UINT32)0x0000ff00UL) << 8) | \
49 (((A_UINT32)(_x) & (A_UINT32)0x00ff0000UL) >> 8) | \
50 (((A_UINT32)(_x) & (A_UINT32)0xff000000UL) >> 24) )) \
53 #define A_SWAB16(_x) \
55 (((A_UINT16)(_x) & (A_UINT16)0x00ffU) << 8) | \
56 (((A_UINT16)(_x) & (A_UINT16)0xff00U) >> 8) ))
58 /* unaligned little endian access */
59 #define A_LE_READ_2(p) \
61 (((A_UINT8 *)(p))[0]) | (((A_UINT8 *)(p))[1] << 8)))
63 #define A_LE_READ_4(p) \
65 (((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \
66 (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
68 #define A_LE64_TO_CPU(_x) ((A_UINT64)(_x))
69 #define A_LE32_TO_CPU(_x) ((A_UINT32)(_x))
70 #define A_CPU_TO_LE32(_x) ((A_UINT32)(_x))
71 #define A_BE32_TO_CPU(_x) A_SWAB32(_x)
72 #define A_CPU_TO_BE32(_x) A_SWAB32(_x)
73 #define A_LE16_TO_CPU(_x) ((A_UINT16)(_x))
74 #define A_CPU_TO_LE16(_x) ((A_UINT16)(_x))
75 #define A_BE16_TO_CPU(_x) A_SWAB16(_x)
76 #define A_CPU_TO_BE16(_x) A_SWAB16(_x)
79 #define A_LE32TOH(_x) A_LE32_TO_CPU(_x)
80 #define A_HTOLE32(_x) A_CPU_TO_LE32(_x)
81 #define A_BE32TOH(_x) A_BE32_TO_CPU(_x)
82 #define A_HTOBE32(_x) A_CPU_TO_BE32(_x)
83 #define A_LE16TOH(_x) A_LE16_TO_CPU(_x)
84 #define A_HTOLE16(_x) A_CPU_TO_LE16(_x)
85 #define A_BE16TOH(_x) A_BE16_TO_CPU(_x)
86 #define A_HTOBE16(_x) A_CPU_TO_BE16(_x)
88 #define A_MAX(x, y) (((x) > (y)) ? (x) : (y))
89 #define A_MIN(x, y) (((x) < (y)) ? (x) : (y))
90 #define A_ABS(x) (((x) >= 0) ? (x) : (-(x)))
91 #define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
92 #define A_ROUND_UP_PAD(x, y) (A_ROUND_UP(x, y) - (x))
93 #define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1))
94 #define A_ROUND_DOWN_PWR2(x, align) ((int)(x) & ~((align)-1))
96 #define A_TOLOWER(c) (((c) >= 'A' && (c) <= 'Z') ? ((c)-'A'+'a') : (c))
97 #define A_TOUPPER(c) (((c) >= 'a' && (c) <= 'z') ? ((c)-'a'+'A') : (c))
99 #define A_ARRAY_NUM_ENTRIES(a) (sizeof(a)/sizeof(*(a)))
100 #define A_FIELD_OFFSET(type, field) ((int)(&((type *)0)->field))
102 #define A_MSECS_PER_SECOND 1000 /* Milliseconds */
103 #define A_USECS_PER_SECOND 1000000 /* Microseconds */
104 #define A_NSECS_PER_SECOND 1000000000 /* Nanoseconds */
107 * Intentional Misaligned Load special "addresses".
108 * Loads from misaligned addresses have special semantics,
109 * handled by the OS, depending on the lower nibble.
111 * NOTE1: word-aligned nibbles will not cause any exception,
112 * so they must not be used.
114 * NOTE2: On AR6002, the Xtensa CPU may issue a load speculatively.
115 * If this load accesses an unmapped region of SOC (such as the
116 * lower 4KB), AR6002 hardware generates an Address Error interrupt
117 * even before the instruction has actually executed and therefore
118 * before it has a chance to generate the expected Misaligned Load
119 * error. To avoid this, we make these IML accesses be to an address
120 * range that is valid....ROM.
123 #define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */
124 #define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */
125 #define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */
126 #define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */
127 #define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */
128 #define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */
129 #define IML_SIGNAL_MASK 0xfffe000f
130 #define IML_LINENUM_SHIFT 4
133 #ifdef HTC_TRACE_MBOX_PAUSE
134 #define A_ASSERT( __bool )
137 * Code space dedicated to asserts is minimal. We use an Intentional
138 * Misaligned Load to signal an assert failure. We embed the line
139 * number in the misaligned address as a debugging aid. This may
140 * make it a bit more difficult to recognize a bona fide misaligned
141 * load, but that's an acceptable tradeoff.
143 * Bits 3..0 encodes the IML_SIGNAL_* number.
144 * Bits 16..4 encode the LINE number of the ASSERTion.
145 * Upper nibbles are the start of ROM.
147 #if defined(__XTENSA__)
148 #define _A_BARRIER asm volatile("memw")
152 #define A_ASSERT( __bool ) \
154 if (0 == (__bool)) { \
155 (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\
161 #define A_IML_IS_ASSERT(vaddr) \
162 (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK))
165 * The A_ASSERT macro encodes line number in the Intentionally Misaligned
166 * Address that it uses to signal a failure. This macro extracts that
167 * line number information.
169 * Note: ASSERTs up to line 8191 (13 bits) of a file are supported.
170 * Beyond that an assertion failure appears as a misaligned load.
172 #define A_IML_ASSLINE(vaddr) (((vaddr) & ~IML_SIGNAL_MASK) >> IML_LINENUM_SHIFT)
174 /* Prevent compiler code movement */
175 #define A_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
178 * Some general system settings may depend on which wireless band is
179 * to be used. For example, on AR6K the system PLL setting is
182 * These constants are used with A_WLAN_BAND_SET.
184 #define A_BAND_24GHZ 0
185 #define A_BAND_5GHZ 1
186 #define A_NUM_BANDS 2
191 //#include <AR6K/AR6K_soc.h>
193 #include <OTUS/OTUS_soc.h>
195 #error "Unsupported platform"
199 //#include "os/athos_api.h"
201 #endif /* __OSAPI_H__ */