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35 #ifndef __INTR_API_H__
36 #define __INTR_API_H__
39 * Interrupt handler, for application-managed interrupts.
40 * When an interrupt occurs, it is automatically disabled.
41 * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH().
43 * If a handler returns A_HANDLER_DONE, the interrupt is
44 * re-enabled. The OS calls the handler next time service
45 * is required. This is the normal case for a handler.
47 * If a handler returns A_HANDLER_YIELD, the interrupt
48 * remains masked. The handler is called again when
49 * it is "convenient". This gives the OS an opportunity
50 * to run other code/handlers. A handler should return
51 * A_HANDLER_YIELD if it might dominate the CPU for too
54 * If a handler returns A_HANDLER_NOENABLE, the interrupt
55 * remains disabled. It is up to the application to re-enable
56 * the interrupt (via A_*_INTR_UNMASK) when it's appropriate.
58 * Note that many combinations of interrupt functions and
59 * interrupt vectors are NOT supported: Callers should use
60 * only the macros defined in cmnos_api.h to access the
63 #include "cmnos_api.h"
65 typedef uint32_t A_old_intr_t;
67 //////////////////////////////////////////////////////////////////
68 // this is copied from mercury/cmnos_xtensa.h
70 * These are CMNOS interrupt manifest constants.
71 * They have specially-chosen values that align with hardware and or
72 * operating system values (see cmnos_interrupt_info).
74 #if defined(__XTENSA__)
76 * Enumeration of low and medium priority interrupt numbers
77 * which match the CPU hardware configuration:
80 /* XTensa Level 1 interrupt */
81 #define A_INUM_SOFTWARE 0 /* currently unused */
83 /* XTensa Level2 interrupts */
84 #define A_INUM_XTTIMER 1 /* Tensilica timer */
85 #define A_INUM_TBD_2 2 /* TBD */
86 #define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */
87 #define A_INUM_TBD_4 4 /* TBD */
88 #define A_INUM_TBD_5 5 /* TBD */
89 #define A_INUM_TBD_6 6 /* TBD */
90 #define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */
91 #define A_INUM_TBD_8 8 /* TBD */
92 #define A_INUM_TBD_9 9 /* TBD */
93 #define A_INUM_USB_CTRL 10 /* USB core control */
94 #define A_INUM_USB_DMA 11 /* USB DMA */
95 #define A_INUM_TBD_12 12 /* TBD */
96 #define A_INUM_TBD_13 13 /* TBD */
97 #define A_INUM_TBD_14 14 /* TBD */
99 /* Level 3 interrupts */
100 #define A_INUM_ERROR 15 /* Errors (e.g. access illegal address) */
101 #define A_INUM_TBD_16 16 /* TBD */
102 #define A_INUM_MAC 17 /* MAC */
104 /* Level 5 interrupts */
105 #define A_INUM_CPU_NMI 18 /* CPU NMI */
107 /* Number of interrupts that map directly into CPU/hal interrupt bits. */
108 #define NUM_DIRECT_INTR 19
111 //////////////////////////////////////////////////////////////////
113 #define CMNOS_IMASK_XTTIMER (1<<A_INUM_XTTIMER)
114 #define CMNOS_IMASK_CPU_WDT (1<<A_INUM_CPU_WDT)
115 #define CMNOS_IMASK_CPU_GEN_TIMER (1<<A_INUM_CPU_GEN_TIMER)
116 #define CMNOS_IMASK_USB_CTRL (1<<A_INUM_USB_CTRL)
117 #define CMNOS_IMASK_USB_DMA (1<<A_INUM_USB_DMA)
118 #define CMNOS_IMASK_ERROR (1<<A_INUM_ERROR)
119 #define CMNOS_IMASK_MAC (1<<A_INUM_MAC)
120 #define CMNOS_IMASK_CPU_NMI (1<<A_INUM_CPU_NMI)
122 typedef enum inum_intr {
127 /* add intr above here */
131 //////////////////////////////////////////////////////////////////
134 * An interrupt handler, which is a function called in response
135 * to a hardware interrupt, possibly as a Delayed Service Routine.
137 typedef int (* A_handler_t)(void *);
138 /* Return values from a handler/DSR, A_handler_t */
139 #define A_HANDLER_NOENABLE 0 /* do not re-enable interrupts */
140 #define A_HANDLER_DONE 1 /* all intrs handled, call on next intr */
141 #define A_HANDLER_YIELD 2 /* leave intrs disabled and
142 call back later regardless of intr state */
145 * An Interrupt Service Routine, which must be called
146 * directly in interrupt context (not delayed), and which
147 * must be very small and may not have access to all OS
148 * functions. These are for use only when interrupt
149 * latency is critical; otherwise, an A_handler_t ("dsr")
152 typedef uint32_t (* A_isr_t)(void *);
153 /* Return values from an ISR */
154 #if defined(CYG_ISR_HANDLED)
155 #define A_ISR_HANDLED CYG_ISR_HANDLED
156 #define A_ISR_CALL_DSR CYG_ISR_CALL_DSR
158 #define A_ISR_HANDLED 1
159 #define A_ISR_CALL_DSR 2
163 void (*_intr_init)(void);
164 uint32_t (* _intr_invoke_isr)(uint32_t inum);
165 A_old_intr_t(* _intr_disable)(void);
166 void (* _intr_restore)(A_old_intr_t);
168 void (* _intr_mask_inum)(uint32_t inum);
169 void (* _intr_unmask_inum)(uint32_t inum);
170 void (* _intr_attach_isr)(uint32_t inum, A_isr_t isr, void *arg);
171 /* Low-level interrupt access, intended for use by OS modules */
172 unsigned int (* _get_intrenable)(void);
173 void (* _set_intrenable)(unsigned int);
174 unsigned int (* _get_intrpending)(void);
175 void (* _unblock_all_intrlvl)(void);
178 #endif /* __INTR_API_H__ */