2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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17 * * Neither the name of Qualcomm Atheros nor the names of its
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "athos_api.h"
42 #include "usbfifo_api.h"
47 typedef void (* USBFIFO_recv_command)(VBUF *cmd);
48 void _fw_usb_suspend_reboot();
50 extern Action eUsbCxFinishAction;
51 extern CommandType eUsbCxCommand;
52 extern BOOLEAN UsbChirpFinish;
53 extern USB_FIFO_CONFIG usbFifoConf;
55 USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL;
58 #define vUsb_ep0end(void) \
60 eUsbCxCommand = CMD_VOID; \
61 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \
64 #define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
68 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
69 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \
70 UsbChirpFinish = FALSE; \
73 #define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
74 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
76 #define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
77 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
79 void _fw_usbfifo_recv_command(VBUF *buf)
84 cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset);
85 tmp = *((A_UINT32 *)cmd_data);
86 if ( tmp == 0xFFFFFFFF ) {
87 _fw_usb_suspend_reboot();
89 m_origUsbfifoRecvCmd(buf);
93 void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig)
95 m_origUsbfifoRecvCmd = pConfig->recv_command;
97 usbFifoConf.get_command_buf = pConfig->get_command_buf;
98 usbFifoConf.recv_command = _fw_usbfifo_recv_command;
99 usbFifoConf.get_event_buf = pConfig->get_event_buf;
100 usbFifoConf.send_event_done = pConfig->send_event_done;
103 #define CHECK_SOF_LOOP_CNT 50
105 void _fw_usb_suspend_reboot()
107 volatile uint32_t gpio_in = 0;
108 volatile uint32_t pupd = 0;
109 volatile uint32_t t = 0;
110 volatile uint32_t sof_no=0,sof_no_new=0;
111 /* Set GO_TO_SUSPEND bit to USB main control register */
113 A_PRINTF("!USB suspend\n\r");
115 // keep the record of suspend
116 #if defined(PROJECT_MAGPIE)
117 *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
118 #elif defined(PROJECT_K2)
119 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
120 #endif /* #if defined(PROJECT_MAGPIE) */
128 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000;
130 // reset ep3/ep4 fifo in case there is data which might affect resuming
131 // HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
132 // HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
135 // config gpio to input before goto suspend
138 //jtag = HAL_WORD_REG_READ(0x10004054);
139 //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17));
142 //spi = HAL_WORD_REG_READ(0x50040);
143 //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8)));
145 //set all GPIO to input
146 gpio_in = HAL_WORD_REG_READ(0x1000404c);
147 HAL_WORD_REG_WRITE(0x100404c, 0x0);
149 //set PU/PD for all GPIO except two UART pins
150 pupd = HAL_WORD_REG_READ(0x10004088);
151 HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A);
154 sof_no= HAL_WORD_REG_READ(0x10004);
155 for (t = 0; t < CHECK_SOF_LOOP_CNT; t++)
157 A_DELAY_USECS(1000); //delay 1ms
158 sof_no_new = HAL_WORD_REG_READ(0x10004);
160 if(sof_no_new == sof_no)
167 * Reset "printf" module patch point(RAM to ROM) when K2 warm start or suspend,
168 * which fixed the error issue cause by redownload another different firmware.
170 _indir_tbl.cmnos.printf._printf = save_cmnos_printf;
172 ///////////////////////////////////////////////////////////////
173 // setting the go suspend here, power down right away...
174 if (t != CHECK_SOF_LOOP_CNT) // not time out
175 HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
176 ///////////////////////////////////////////////////////////////
178 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100;
180 #if 0 // pll unstable, h/w bug?
181 HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12));
182 A_UART_HWINIT((40*1000*1000)/1, 19200);
185 // restore gpio setting
186 //HAL_WORD_REG_WRITE(0x10004054, jtag);
187 //HAL_WORD_REG_WRITE(0x50040, spi);
188 HAL_WORD_REG_WRITE(0x1000404c, gpio_in);
189 HAL_WORD_REG_WRITE(0x10004088, pupd);
191 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200;
194 // since we still need to touch mac_base address after resuming back, so that
195 // reset mac can't be done in ResetFifo function, move to here...
196 // whole mac control reset.... (bit1)
197 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1) );
198 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
199 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
202 //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020));
203 // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
204 mUSB_STATUS_IN_INT_DISABLE();
206 MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
207 MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
208 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
209 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
211 if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) {
212 /* UART_SEL and SPI_SEL */
213 HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12));
216 /* Jump to boot code */
222 * -- patch usb_fw_task --
223 * . usb zero length interrupt should not clear by s/w, h/w will handle that
224 * . complete suspend handle, configure gpio, turn off related function,
225 * slow down the pll for stable issue
227 void _fw_usb_fw_task(void)
229 register uint8_t usb_interrupt_level1;
230 register uint8_t usb_interrupt_level2;
232 usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
233 #if 0 // these endpoints are handled by DMA
234 if (usb_interrupt_level1 & BIT5) //Group Byte 5
239 if (usb_interrupt_level1 & BIT4)
241 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
242 if( usb_interrupt_level2 & BIT6)
243 A_USB_REG_OUT();//vUsb_Reg_Out();
246 if (usb_interrupt_level1 & BIT6)
248 //zfGenWatchDogEvent();
249 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
250 if( usb_interrupt_level2 & BIT6)
251 A_USB_STATUS_IN();//vUsb_Status_In();
254 if (usb_interrupt_level1 & BIT0) //Group Byte 0
256 //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG;
257 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
259 // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
260 if (usb_interrupt_level2 & BIT7)
262 //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort
263 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
264 A_PRINTF("![SOURCE_0] bit7 on\n\r");
267 if (usb_interrupt_level2 & BIT1)
269 //A_PRINTF("![USB] ep0 IN in \n\r");
270 A_USB_EP0_TX(); // USB EP0 tx interrupt
272 if (usb_interrupt_level2 & BIT2)
274 //A_PRINTF("![USB] ep0 OUT in\n\r");
275 A_USB_EP0_RX(); // USB EP0 rx interrupt
277 if (usb_interrupt_level2 & BIT0)
279 //A_PRINTF("![USB] ep0 SETUP in\n\r");
281 //vWriteUSBFakeData();
283 // else if (usb_interrupt_level2 & BIT3)
284 if (usb_interrupt_level2 & BIT3)
287 // A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r");
289 if (usb_interrupt_level2 & BIT4)
292 // A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r");
294 if (eUsbCxFinishAction == ACT_STALL)
296 // set CX_STL to stall Endpoint0 & will also clear FIFO0
297 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
298 // A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
300 else if (eUsbCxFinishAction == ACT_DONE)
302 // set CX_DONE to indicate the transmistion of control frame
303 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
305 eUsbCxFinishAction = ACT_IDLE;
308 if (usb_interrupt_level1 & BIT7) //Group Byte 7
310 //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
311 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
314 if (usb_interrupt_level2 & BIT7)
316 vUsb_Data_Out0Byte();
317 // A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r");
319 if (usb_interrupt_level2 & BIT6)
322 // A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r");
326 if (usb_interrupt_level2 & BIT1)
329 //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2));
330 A_PRINTF("!USB reset\n\r");
331 // A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
333 if (usb_interrupt_level2 & BIT2)
335 // TBD: the suspend resume code should put here, Ryan, 07/18
337 // issue, jump back to rom code and what peripherals should we reset here?
339 _fw_usb_suspend_reboot();
341 if (usb_interrupt_level2 & BIT3)
344 A_PRINTF("!USB resume\n\r");
351 void _fw_usb_reset_fifo(void)
353 volatile uint32_t *reg_data;
355 HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
356 HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
358 // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
359 mUSB_STATUS_IN_INT_DISABLE();
361 // update magic pattern to indicate this is a suspend
362 // k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR
363 // magpie: MAGPIE_REG_RST_STATUS_ADDR
364 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
367 * Before USB suspend, USB DMA must be reset(refer to Otus)
368 * Otus runs the following statements only
369 * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 );
370 * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
371 * K2 must run the following statements additionally
372 * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118);
373 * *reg_data = 0x00000000;
374 * *reg_data = 0x00000001;
375 * because of Hardware bug in K2
377 reg_data = (uint32_t *)(USB_CTRL_BASE_ADDRESS + 0x118);
378 *reg_data = 0x00000000;
380 // reset both usb(bit2)/wlan(bit1) dma
381 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2) );
382 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
383 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
385 *reg_data = 0x00000001;
387 /* MAC warem reset */
388 //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000);
389 //*reg_data = 0x00000001;
393 //*reg_data = 0x00000000;
395 //while (*reg_data) ;
397 A_PRINTF("\n change clock to 22 and go to suspend now!");
400 HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12));
401 A_UART_HWINIT((22*1000*1000), 19200);
405 * -- support more than 64 bytes command on ep4 --
407 void vUsb_Reg_Out_patch(void)
412 static volatile uint32_t *regaddr; // = (volatile uint32_t *) ZM_CMD_BUFFER;
413 static uint16_t cmdLen;
415 BOOLEAN cmd_is_last = FALSE;
416 static BOOLEAN cmd_is_new = TRUE;
418 // get the size of this transcation
419 usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
421 // check is command is new
424 buf = usbFifoConf.get_command_buf();
430 // copy free, assignment buffer of the address
431 regaddr = (uint32_t *)buf->desc_list->buf_addr;
436 // just in case, suppose should not happen
440 // if size is smaller, this is the last command!
442 // zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here
444 if( usbfifolen<bUSB_EP_MAX_PKT_SIZE_64 ) {
448 // accumulate the size
449 cmdLen += usbfifolen;
451 // round it to alignment
453 usbfifolen = (usbfifolen >> 2) + 1;
455 usbfifolen = usbfifolen >> 2;
457 // A_PRINTF("copy data out from fifo to - %p\n\r", regaddr);
458 // retrieve the data from fifo
459 for(ii = 0; ii < usbfifolen; ii++)
461 ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
466 // if this is the last command, callback to HTC
469 buf->desc_list->next_desc = NULL;
470 buf->desc_list->data_offset = 0;
471 buf->desc_list->data_size = cmdLen;
472 buf->desc_list->control = 0;
473 buf->next_buf = NULL;
474 buf->buf_length = cmdLen;
476 usbFifoConf.recv_command(buf);
483 // we might get no command buffer here?
484 // but if we return here, the ep4 fifo will be lock out,
485 // so that we still read them out but just drop it ?
486 for(ii = 0; ii < usbfifolen; ii++)
488 ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
492 //mUSB_STATUS_IN_INT_ENABLE();
499 * -- usb1.1 ep6 fix --
501 extern uint16_t u8UsbConfigValue;
502 extern uint16_t u8UsbInterfaceValue;
503 extern uint16_t u8UsbInterfaceAlternateSetting;
504 extern SetupPacket ControlCmd;
505 extern void vUsbClrEPx(void);
507 void vUSBFIFO_EP6Cfg_FS_patch(void)
509 #if (FS_C1_I0_A0_EP_NUMBER >= 6)
513 mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP);
514 mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP);
515 mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG);
517 for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ;
518 i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++)
520 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
523 mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
524 mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
525 mUsbEPinHighBandSet(EP6 , FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET);
529 void vUsbFIFO_EPxCfg_FS_patch(void)
531 switch (u8UsbConfigValue)
533 #if (FS_CONFIGURATION_NUMBER >= 1)
534 // Configuration 0X01
536 switch (u8UsbInterfaceValue)
538 #if (FS_C1_INTERFACE_NUMBER >= 1)
541 switch (u8UsbInterfaceAlternateSetting)
544 #if (FS_C1_I0_ALT_NUMBER >= 1)
545 // AlternateSetting 0
550 // patch up this ep6_fs config
551 vUSBFIFO_EP6Cfg_FS_patch();
573 BOOLEAN bSet_configuration_patch(void)
575 //A_PRINTF("bSet_configuration...\n\r");
577 bSet_configuration();
579 if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0)
586 if (mUsbHighSpeedST()) // First judge HS or FS??
594 vUsbFIFO_EPxCfg_FS_patch();
600 eUsbCxFinishAction = ACT_DONE;
606 * -- support more than 64 bytes command on ep3 --
608 void vUsb_Status_In_patch(void)
613 BOOLEAN cmdEnd = FALSE;
615 static u16_t mBufLen;
616 static VBUF *evntbuf = NULL;
617 static volatile u32_t *regaddr;
618 static BOOLEAN cmd_is_new = TRUE;
622 evntbuf = usbFifoConf.get_event_buf();
623 if ( evntbuf != NULL )
625 regaddr = (u32_t *)VBUF_GET_DATA_ADDR(evntbuf);
626 mBufLen = evntbuf->buf_length;
630 mUSB_STATUS_IN_INT_DISABLE();
636 // if( mBufLen>bUSB_EP_MAX_PKT_SIZE_64 )
637 // A_PRINTF("EP3 send %d bytes to host \n", mBufLen);
641 if( mBufLen > bUSB_EP_MAX_PKT_SIZE_64 ) {
642 RegBufLen = bUSB_EP_MAX_PKT_SIZE_64;
643 mBufLen -= bUSB_EP_MAX_PKT_SIZE_64;
645 // TODO: 64 byes... controller supposed will take care of zero-length?
652 for(count = 0; count < (RegBufLen / 4); count++)
654 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
658 remainder = RegBufLen % 4;
665 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
668 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
671 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
675 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
677 // Restore CBus FIFO size to word size
678 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
681 mUSB_EP3_XFER_DONE();
683 // if( mBufLen<=bUSB_EP_MAX_PKT_SIZE_64 )
687 if ( evntbuf != NULL && cmdEnd )
689 usbFifoConf.send_event_done(evntbuf);
697 extern uint16_t *u8ConfigDescriptorEX;
698 extern uint16_t *pu8DescriptorEX;
699 extern uint16_t u16TxRxCounter;
700 extern BOOLEAN bGet_descriptor(void);
702 uint16_t ConfigDescriptorPatch[30];
704 #define EP3_TRANSFER_TYPE_OFFSET 17
705 #define EP3_INT_INTERVAL 19
706 #define EP4_TRANSFER_TYPE_OFFSET 21
707 #define EP4_INT_INTERVAL 22
709 BOOLEAN bGet_descriptor_patch(void)
711 if (mDEV_REQ_VALUE_HIGH() == 2) {
712 uint8_t *p = (uint8_t *)u8ConfigDescriptorEX;
714 /* Copy ConfigDescriptor */
715 memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch));
717 p = (uint8_t *)ConfigDescriptorPatch;
719 /* Patch the transfer type of EP3 and EP4 */
720 ConfigDescriptorPatch[EP3_TRANSFER_TYPE_OFFSET] = 0x0283;
721 ConfigDescriptorPatch[EP3_INT_INTERVAL] = 0x0700;
722 ConfigDescriptorPatch[EP4_TRANSFER_TYPE_OFFSET] = 0x4002;
723 ConfigDescriptorPatch[EP4_INT_INTERVAL] = 0x00;
725 switch (mDEV_REQ_VALUE_LOW())
727 case 0x00: // configuration no: 0
728 pu8DescriptorEX = ConfigDescriptorPatch;
729 u16TxRxCounter = ConfigDescriptorPatch[1];
730 //u16TxRxCounter = 46;
736 if (u16TxRxCounter > mDEV_REQ_LENGTH())
737 u16TxRxCounter = mDEV_REQ_LENGTH();
743 return bGet_descriptor();
747 extern BOOLEAN bStandardCommand(void);
749 BOOLEAN bStandardCommand_patch(void)
751 if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) {
754 #if ENABLE_SWAP_DATA_MODE
755 // SWAP FUNCTION should be enabled while DMA engine is not working,
756 // the best place to enable it is before we trigger the DMA
757 MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
758 MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
760 #if SYSTEM_MODULE_HP_EP5
761 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
764 #if SYSTEM_MODULE_HP_EP6
765 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
768 #endif //ENABLE_SWAP_DATA_MODE
772 return bStandardCommand();