2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include "athos_api.h"
38 #if SYSTEM_MODULE_SFLASH
40 #include "adf_os_io.h"
43 #include "sflash_api.h"
45 /*******************************************
46 * Definitions of module internal constant *
47 *******************************************/
49 /* Definitions of base address and Flash sise -> Project dependent */
50 #define ZM_SPI_REGISTER_BASE SPI_REG_BASE_ADDRESS /* 0x0005B000 */
51 #define ZM_SPI_FLASH_BASE SPI_FLASH_BASE /* 0x0F000000 */
52 #define ZM_SPI_FLASH_MAX_ADDR SPI_FLASH_MAX_ADDR /* 0x0FFFFFFF */
53 #define ZM_SPI_FLASH_MAX_SIZE SPI_FLASH_MAX_SIZE /* 0x01000000 */
56 * Base address of Clock and Reset Control Registers is 0x00050000
57 * Offset of Clock Control Register is 0x40
58 * SPI_SEL (bit 8) : Switch the function of I/O pin 19~22 between GPIO and SPI.
59 * 0 -> act as GPIO5~8;
60 * 1 -> act as SPI pins.
62 #define ZM_SPI_CLK_CTRL_ADDR 0x00050040
63 #define ZM_SPI_SPI_SEL_BIT 0x100
65 /* Definitions of Serial Flash constants -> According to standard or vendor dependent */
66 #define ZM_SFLASH_PAGE_SIZE 256
68 /* Definitions of OP Code -> According to standard or vendor dependent */
69 #define ZM_SFLASH_OP_READ 0x03 /* Read Data Bytes */
70 #define ZM_SFLASH_OP_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */
72 * For MXIC, sector erase : Command 0x20, size 4K bytes
73 * block erase : Command 0xD8, size 64K bytes
74 * chip earse : command 0x60 or 0xC7
75 * For Spansion, sector erase : Command 0x20 or 0xD8, size 64K bytes (For 64 KB sector devices, either command is valid and performs the same function.)
76 * block erase : Command 0xD8, size 256K bytes
77 * chip earse : command 0x60 or 0xC7, Uniform 64 KB Sector Product (For 64 KB sector devices, either command is valid and performs the same function.)
78 * 0xC7, Uniform 256 KB Sector Product
80 #define ZM_SFLASH_OP_SE 0x20 /* Sector Erase */
81 #define ZM_SFLASH_OP_BE 0xD8 /* Block Erase */
82 #define ZM_SFLASH_OP_CE 0xC7 /* Chip Erase */
83 #define ZM_SFLASH_OP_PP 0x02 /* Page Program */
84 #define ZM_SFLASH_OP_RDSR 0x05 /* Read from Status Register */
85 #define ZM_SFLASH_OP_WRSR 0x01 /* Write to Status Register */
86 #define ZM_SFLASH_OP_WREN 0x06 /* Write Enable */
87 #define ZM_SFLASH_OP_WRDI 0x04 /* Write Disable */
88 #define ZM_SFLASH_OP_RDID 0x9F /* Read Identification */
89 #define ZM_SFLASH_OP_DP 0xB9 /* Deep Power Down */
90 #define ZM_SFLASH_OP_RES 0xAB /* Release from Deep Power Down, Release from Deep Power Down and Read Electronic Signature */
92 /* Definitions of Status Register -> According to standard or vendor dependent */
93 /* Write in progress bit
94 * 1 = Device Busy. A Write Status Register, program, or erase operation is in progress
95 * 0 = Ready. Device is in standby mode and can accept commands.
97 #define ZM_SFLASH_STATUS_REG_WIP (1<<0)
98 /* Write enable latch bit
99 * 1 = Device accepts Write Status Register, program, or erase commands
100 * 0 = Ignores Write Status Register, program, or erase commands
102 #define ZM_SFLASH_STATUS_REG_WEL (1<<1)
103 /* Status register write disable bit
104 * 1 = Protects when WP#/ACC is low
105 * 0 = No protection, even when WP#/ACC is low
107 #define ZM_SFLASH_STATUS_REG_SRWD (1<<7)
109 /* Definitions of SPI Flash Controller -> SPI Flash Controller dependent */
110 /* SPI Flash Controller used in K2 project is part of Falcon's "Driver Support Logic" (DSL) block */
113 * ====== ==========================================================
114 * 0x0000 SPI control/status register (SPI_CS)
115 * 0x0004 SPI address/opcode register (SPI_AO)
116 * 0x0008 SPI data register (SPI_D)
120 * SPI control/status register (SPI_CS)
122 * Cold reset: (See field descriptions)
123 * Warm reset: (Same as cold reset)
126 * 3:0 - Transmit byte count. Determines the number of bytes
127 * transmitted from Falcon to the SPI device. Values of 1-8 are
128 * valid; other values are illegal. See the 'Notes' section below
129 * for details on how to use this field. Resets to an undefined
131 * 7:4 - Receive byte count. Determines the number of bytes received
132 * from the SPI device into Falcon. Values of 0-8 are valid;
133 * other values are illegal. See the 'Notes' section below for
134 * details on how to use this field. Resets to an undefined
136 * 8 - SPI transaction start. Only writes to this field are
137 * meaningful; reads always return 0. Resets to 0x0. For writes:
138 * * A write of '1' starts the SPI transaction defined by the
139 * transmit byte count, receive byte count, SPI_AO, and SPI_D
141 * * A write of '0' has no effect
142 * 9 - SPI chip select 1 enable. Resets to 0x0. See bug 12540.
143 * 0 - SP0 is enabled and SP1 is forced inactive.
144 * 1 - SP1 is enabled and SP0 is forced inactive.
146 * 16 - Transaction busy indication. Read-only; writes to this bit are
147 * ignored. Resets to 0x0.
148 * 0 - No SPI transaction is ongoing. Software may start a new
149 * SPI transaction by writing to the 'SPI transaction start'
150 * bit within this register.
151 * 1 - An SPI transaction presently is underway. Software must
152 * not try to start a new SPI transaction, nor may software
153 * alter the value of any field of the SPI_CS, SPI_AO, or
155 * 18:17 - Automatically-determined SPI address size. Read-only; writes
156 * to this bit are ignored. Resets to an undefined value, but
157 * then is updated after the autosizing process completes.
158 * 0 - SPI address size was determined to be 16 bits
159 * 1 - SPI address size was determined to be 24 bits
161 * 3 - Automatic SPI address size determination failed. Typical
162 * causes of this result:
163 * * The SPI device is missing
164 * * The SPI device is unprogrammed
165 * * The SPI device is programmed with an incorrect
167 * 20:19 - SPI autosize override. Resets to 0x0.
168 * 0 - Use automatically-determined SPI address size (see bits
169 * [18:17] of this register)
170 * 1 - Force SPI address size to 16 bits
171 * 2 - Force SPI address size to 24 bits
176 #define SPI_CS_ADDRESS MAGPIE_REG_SPI_CS_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000000)
177 /* 3:0 - Transmit byte count, values of 1-8 are valid */
178 #define SPI_CS_TXBCNT_MSB 3
179 #define SPI_CS_TXBCNT_LSB 0
180 #define SPI_CS_TXBCNT_MASK 0x0000000f
181 #define SPI_CS_TXBCNT_GET(x) (((x) & SPI_CS_TXBCNT_MASK) >> SPI_CS_TXBCNT_LSB)
182 #define SPI_CS_TXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_TXBCNT_LSB) & SPI_CS_TXBCNT_MASK)
184 /* 7:4 - Receive byte count, values of 1-8 are valid */
185 #define SPI_CS_RXBCNT_MSB 7
186 #define SPI_CS_RXBCNT_LSB 4
187 #define SPI_CS_RXBCNT_MASK 0x000000f0
188 #define SPI_CS_RXBCNT_GET(x) (((x) & SPI_CS_RXBCNT_MASK) >> SPI_CS_RXBCNT_LSB)
189 #define SPI_CS_RXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_RXBCNT_LSB) & SPI_CS_RXBCNT_MASK)
191 /* 8 - SPI transaction start */
192 #define SPI_CS_XCNSTART_MSB 8
193 #define SPI_CS_XCNSTART_LSB 8
194 #define SPI_CS_XCNSTART_MASK 0x00000100
195 #define SPI_CS_XCNSTART_GET(x) 0x0
196 #define SPI_CS_XCNSTART_SET(x) (((0x0 | (x)) << SPI_CS_XCNSTART_LSB) & SPI_CS_XCNSTART_MASK)
197 #define SPI_CS_XCNSTART_RESET 0x0
199 /* 9 - SPI chip select */
200 #define SPI_CS_CS_MSB 9
201 #define SPI_CS_CS_LSB 9
202 #define SPI_CS_CS_MASK 0x00000200
203 #define SPI_CS_CS_GET(x) (((x) & SPI_CS_CS_MASK) >> SPI_CS_CS_LSB)
204 #define SPI_CS_CS_SET(x) (((0x0 | (x)) << SPI_CS_CS_LSB) & SPI_CS_CS_MASK)
205 #define SPI_CS_CS_RESET 0x0
207 /* 16 - Transaction busy indication */
208 #define SPI_CS_BUSY_MSB 16
209 #define SPI_CS_BUSY_LSB 16
210 #define SPI_CS_BUSY_MASK 0x00010000
211 #define SPI_CS_BUSY_GET(x) (((x) & SPI_CS_BUSY_MASK) >> SPI_CS_BUSY_LSB)
212 #define SPI_CS_BUSY_SET(x) (((0x0 | (x)) << SPI_CS_BUSY_LSB) & SPI_CS_BUSY_MASK)
213 #define SPI_CS_BUSY_RESET 0x0
215 /* 18:17 - Automatically-determined SPI address size */
216 #define SPI_CS_AUTOSIZ_MSB 18
217 #define SPI_CS_AUTOSIZ_LSB 17
218 #define SPI_CS_AUTOSIZ_MASK 0x00060000
219 #define SPI_CS_AUTOSIZ_GET(x) (((x) & SPI_CS_AUTOSIZ_MASK) >> SPI_CS_AUTOSIZ_LSB)
220 #define SPI_CS_AUTOSIZ_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_LSB) & SPI_CS_AUTOSIZ_MASK)
222 /* 20:19 - SPI autosize override */
223 #define SPI_CS_AUTOSIZ_OVR_MSB 20
224 #define SPI_CS_AUTOSIZ_OVR_LSB 19
225 #define SPI_CS_AUTOSIZ_OVR_MASK 0x00180000
226 #define SPI_CS_AUTOSIZ_OVR_GET(x) (((x) & SPI_CS_AUTOSIZ_OVR_MASK) >> SPI_CS_AUTOSIZ_OVR_LSB)
227 #define SPI_CS_AUTOSIZ_OVR_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_OVR_LSB) & SPI_CS_AUTOSIZ_OVR_MASK)
228 #define SPI_CS_AUTOSIZ_OVR_RESET 0x0
230 #define SPI_CS_RESET (0x0 | \
231 SPI_CS_AUTOSIZ_OVR_SET(SPI_CS_AUTOSIZ_OVR_RESET) | \
232 SPI_CS_BUSY_SET(SPI_CS_BUSY_RESET) | \
233 SPI_CS_CS_SET(SPI_CS_CS_RESET) | \
234 SPI_CS_XCNSTART_SET(SPI_CS_XCNSTART_RESET))
237 * SPI address/opcode register (SPI_AO)
239 * Cold reset: (See field descriptions)
240 * Warm reset: (Same as cold reset)
243 * 7:0 - SPI opcode. Usually this field specifies the 8-bit opcode
244 * (aka "instruction") to transmit to the SPI device as the first
245 * part of an SPI transaction. See the 'Notes' section below for
246 * more details. Resets to an undefined value.
247 * 31:8 - Address. Usually this field specifies the 24-bit address to
248 * transmit to the SPI device. See the 'Notes' section below for
249 * more details. Resets to an undefined value.
252 #define SPI_AO_ADDRESS MAGPIE_REG_SPI_AO_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000004)
253 /* 7:0 - SPI opcode */
254 #define SPI_AO_OPC_MSB 7
255 #define SPI_AO_OPC_LSB 0
256 #define SPI_AO_OPC_MASK 0x000000ff
257 #define SPI_AO_OPC_GET(x) (((x) & SPI_AO_OPC_MASK) >> SPI_AO_OPC_LSB)
258 #define SPI_AO_OPC_SET(x) (((0x0 | (x)) << SPI_AO_OPC_LSB) & SPI_AO_OPC_MASK)
260 #define SPI_AO_ADDR_MSB 31
261 #define SPI_AO_ADDR_LSB 8
262 #define SPI_AO_ADDR_MASK 0xffffff00
263 #define SPI_AO_ADDR_GET(x) (((x) & SPI_AO_ADDR_MASK) >> SPI_AO_ADDR_LSB)
264 #define SPI_AO_ADDR_SET(x) (((0x0 | (x)) << SPI_AO_ADDR_LSB)& SPI_AO_ADDR_MASK)
267 * SPI data register (SPI_D)
269 * Cold reset: (See field descriptions)
270 * Warm reset: (Same as cold reset)
273 * 31:0 - SPI data. Usually this register specifies a series of up to
274 * four data bytes to transmit to or receive from the SPI device.
275 * See the 'Notes' section below for more details. Resets to an
279 #define SPI_D_ADDRESS MAGPIE_REG_SPI_D_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000008)
280 /* 31:0 - SPI data */
281 #define SPI_D_DATA_MSB 31
282 #define SPI_D_DATA_LSB 0
283 #define SPI_D_DATA_MASK 0xffffffff
284 #define SPI_D_DATA_GET(x) (((x) & SPI_D_DATA_MASK) >> SPI_D_DATA_LSB)
285 #define SPI_D_DATA_SET(x) (((0x0 | (x)) << SPI_D_DATA_LSB) & SPI_D_DATA_MASK)
288 * SPI clock division register (SPI_CLKDIV)
290 * Cold reset: (See field descriptions)
291 * Warm reset: (Same as cold reset)
294 * 17:16 - 0b00(fastest), 0b01, 0b10, 0b11(slowest)
296 #define SPI_CLKDIV_ADDRESS MAGPIE_REG_SPI_CLKDIV_ADDR //SPI_BASE_ADDRESS + 0x0000001c
297 #define SPI_CLKDIV_MSB 17
298 #define SPI_CLKDIV_LSB 16
299 #define SPI_CLKDIV_MASK 0x00030000
300 #define SPI_CLKDIV_GET(x) (((x) & SPI_CLKDIV_MASK) >> SPI_CLKDIV_LSB)
301 #define SPI_CLKDIV_SET(x) (((0x0 | (x)) << SPI_CLKDIV_LSB) & SPI_CLKDIV_MASK) // read-then-write
302 #define SPI_CLKDIV_RESET 0x3
308 * An SPI transaction consists of three phases: an opcode transmit
309 * phase (always a single byte), followed by an optional address
310 * transmit phase of 0-3 bytes, followed by an optional data transmit
311 * or receive phase of 0-4 bytes.
313 * Combined, then, an SPI transaction consists of a 1- to 8-byte
314 * transmit phase from Falcon to the SPI device, followed by a 0- to
315 * 8-byte receive phase from the SPI device into Falcon.
317 * The 'transmit byte count' field in the SPI_CS register controls the
318 * size (number of bytes) of the transmit phase. The source of each
319 * of the bytes transmitted is fixed:
322 * ---- -----------------------------------------------------------
323 * 0 SPI_AO[7:0] (the 'SPI opcode' field)
324 * 1 SPI_AO[31:24] (the high byte of the 'SPI address' field)
325 * 2 SPI_AO[23:16] (the middle byte of the 'SPI address' field)
326 * 3 SPI_AO[15:8] (the low byte of the 'SPI address' field)
327 * 4 SPI_D[7:0] (the low byte of the 'SPI data' register)
328 * 5 SPI_D[15:8] (the next byte of the 'SPI data' register)
329 * 6 SPI_D[23:16] (the next byte of the 'SPI data' register)
330 * 7 SPI_D[31:24] (the high byte of the 'SPI data' register)
333 * The 'receive byte count' field in the SPI_CS register controls the
334 * size (number of bytes) of the receive phase. The destination of
335 * each of the bytes received is fixed:
338 * ---- -----------------------------------------------------------
339 * 0 SPI_D[7:0] (the low byte of the 'SPI data' register)
340 * 1 SPI_D[15:8] (the next byte of the 'SPI data' register)
341 * 2 SPI_D[23:16] (the next byte of the 'SPI data' register)
342 * 3 SPI_D[31:24] (the high byte of the 'SPI data' register)
343 * 4 SPI_AO[7:0] (the 'SPI opcode' field)
344 * 5 SPI_AO[15:8] (the low byte of the 'SPI address' field)
345 * 6 SPI_AO[23:16] (the middle byte of the 'SPI address' field)
346 * 7 SPI_AO[31:24] (the high byte of the 'SPI address' field)
349 * * To perform an SPI transaction:
350 * Write the appropriate values into the SPI_AO and SPI_D registers
351 * * Write the appropriate values into the 'transmit byte count' and
352 * 'received byte count' fields of the SPI_CS register.
353 * * Write a '1' to the 'SPI transaction start' bit of the SPI_CS
354 * register (this step can be combined with the one above if desired
355 * so that only a single SPI_CS write is needed).
356 * * Poll the 'transaction busy indication' bit in the SPI_CS register
357 * until it is clear, indicating that the SPI transaction has
359 * * If the transaction included a receive phase, then retrieve the
360 * received data by reading the appropriate bytes from the SPI_D and
365 * * A "write disable" (WRDI) transaction:
366 * * Opcode (SPI_AO[7:0]): 0x04 (for STMicro; varies by
367 * manufacturer and device type)
368 * * Address (SPI_AO[31:8]): don't care (not used)
369 * * Data (SPI_D[31:0]): don't care (not used)
370 * * Transmission byte count: 1
371 * * Receive byte count: 0
373 * * A "read status register" (RDSR) transaction:
374 * * Opcode (SPI_AO[7:0]): 0x05 (for STMicro; varies by
375 * manufacturer and device type)
376 * * Address (SPI_AO[31:8]): don't care (not used)
377 * * Data (SPI_D[31:0]): don't care (not used)
378 * * Transmission byte count: 1
379 * * Receive byte count: 1
380 * * Read SPI_D[7:0] to retrieve status register value
382 * * A "page program" (PP) transaction to write a value of 0xdeadbeef
383 * to address 0x123456:
384 * * Opcode (SPI_AO[7:0]): 0x02 (for STMicro; varies by
385 * manufacturer and device type)
386 * * Address (SPI_AO[31:8]): 0x123456
387 * * Data (SPI_D[31:0]): 0xdeadbeef
388 * * Transmission byte count: 8
389 * * Receive byte count: 0
392 /* Wait till Transaction busy indication bit in SPI control/status register of Falcon's SPI Flash Controller is clear */
394 _cmnos_sflash_WaitTillTransactionOver(void)
401 poldata = ioread32(SPI_CS_ADDRESS);
403 flg = SPI_CS_BUSY_GET(poldata);
404 } while (flg != 0x0);
407 /* Wait till Write In Progress bit in Status Register of Serial Flash is clear */
409 _cmnos_sflash_WaitTillNotWriteInProcess(void)
415 _cmnos_sflash_WaitTillTransactionOver();
417 iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR));
418 iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1));
420 _cmnos_sflash_WaitTillTransactionOver();
422 flg = ioread32(SPI_D_ADDRESS) & ZM_SFLASH_STATUS_REG_WIP;
424 } while (flg != 0x0);
427 /************************************************************************/
428 /* Function to Send WREN(Write Enable) Operation */
429 /************************************************************************/
431 _cmnos_sflash_WriteEnable()
433 _cmnos_sflash_WaitTillNotWriteInProcess();
435 iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN));
436 iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
438 _cmnos_sflash_WaitTillTransactionOver();
441 /************************************************************************/
442 /* Function to Initialize SPI Flash Controller */
443 /************************************************************************/
445 cmnos_sflash_init(void)
447 /* Switch the function of I/O pin 19~22 to act as SPI pins */
448 io32_set(MAGPIE_REG_CLOCK_CTRL_ADDR, BIT8);
450 /* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail :
451 * The designers reached an conclusion that the spi master (the apb_spi interface control) will be
452 * modified as presuming the attached flash model to be 24-bit addressing, i.e., no more
453 * auto-size detection!
454 * Hence you are free to force the 24-bit addressing in the *.c test code.
457 /* Force SPI address size to 24 bits */
458 iowrite32(SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2));
461 /************************************************************************/
462 /* Function to Send Sector/Block/Chip Erase Operation */
463 /************************************************************************/
465 cmnos_sflash_erase(A_UINT32 erase_type, A_UINT32 addr)
467 A_UINT32 erase_opcode;
470 if (erase_type == ZM_SFLASH_SECTOR_ERASE)
472 erase_opcode = ZM_SFLASH_OP_SE;
475 else if (erase_type == ZM_SFLASH_BLOCK_ERASE)
477 erase_opcode = ZM_SFLASH_OP_BE;
482 erase_opcode = ZM_SFLASH_OP_CE;
486 _cmnos_sflash_WriteEnable();
487 _cmnos_sflash_WaitTillNotWriteInProcess();
489 iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr));
490 iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
493 /* Do not wait(let it be completed in background) */
494 _cmnos_sflash_WaitTillTransactionOver();
496 /* Wait till completion */
497 _cmnos_sflash_WaitTillNotWriteInProcess(); /* Chip Erase takes 80 - 200 seconds to complete */
501 /************************************************************************/
502 /* Function to Perform Page Program Operation */
504 /* Serial Flash has the following characteristics : */
505 /* 1) In datasheet, 1-256 data bytes can be sent at a time, but */
506 /* Falcon supports only 4 bytes at a time. */
507 /* 2) If the eight least significant address bits(A7-A0) are not */
508 /* all 0, all transmitted data which goes beyond the end of the */
509 /* current page are programmed from the start address in the */
511 /* This API hides the complexity of the above. */
512 /************************************************************************/
514 cmnos_sflash_program(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf)
516 A_UINT32 s_addr, e_addr;
517 A_UINT32 reminder, write_byte;
518 A_UINT32 data_offset;
519 A_UINT32 next_page_base;
520 A_UINT32 t_word_data;
523 for (s_addr = addr; s_addr < e_addr; )
525 next_page_base = (s_addr - s_addr%ZM_SFLASH_PAGE_SIZE) + ZM_SFLASH_PAGE_SIZE;
527 reminder = e_addr - s_addr;
529 write_byte = next_page_base - s_addr;
534 if (write_byte > reminder)
535 write_byte = reminder;
537 data_offset = s_addr - addr;
539 A_MEMCPY(&t_word_data, buf + data_offset, write_byte);
541 _cmnos_sflash_WriteEnable();
542 _cmnos_sflash_WaitTillNotWriteInProcess();
544 iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr));
545 iowrite32(SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data));
546 iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
548 _cmnos_sflash_WaitTillTransactionOver();
550 s_addr += write_byte;
554 /************************************************************************/
555 /* Function to Send Read/Fast Read Data Operation */
556 /************************************************************************/
558 cmnos_sflash_read(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf)
560 A_UINT32 read_opcode;
562 A_UINT32 read_cnt, remainder;
563 A_UINT32 write_byte, read_byte;
567 read_opcode = ZM_SFLASH_OP_FAST_READ;
572 read_opcode = ZM_SFLASH_OP_READ;
582 for (i = 0; i < read_cnt; i ++)
584 if (i == read_cnt-1 && remainder)
585 read_byte = remainder;
587 _cmnos_sflash_WaitTillNotWriteInProcess();
589 iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4));
590 iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1));
592 _cmnos_sflash_WaitTillTransactionOver();
594 A_MEMCPY(buf + i*4, (A_UINT8 *)(SPI_D_ADDRESS), read_byte);
598 /************************************************************************/
599 /* Function to Read Flash Status Register */
600 /************************************************************************/
602 cmnos_sflash_rdsr(void)
606 _cmnos_sflash_WaitTillTransactionOver();
608 iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR));
609 iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1));
611 _cmnos_sflash_WaitTillTransactionOver();
613 word_data = ioread32(SPI_D_ADDRESS) & 0x000000FF;
619 cmnos_sflash_module_install(struct sflash_api *tbl)
621 /* Indispensable functions */
622 tbl->_sflash_init = cmnos_sflash_init;
623 tbl->_sflash_erase = cmnos_sflash_erase;
624 tbl->_sflash_program = cmnos_sflash_program;
625 tbl->_sflash_read = cmnos_sflash_read;
627 /* Dispensable functions */
628 tbl->_sflash_rdsr = cmnos_sflash_rdsr;
631 #endif /* SYSTEM_MODULE_SFLASH */