1 /*************************************************************************/
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2 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
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4 /* Module Name : reg_defs.h */
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7 /* This file contains the register addr and marco definition. */
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12 /*************************************************************************/
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13 #ifndef _REG_DEFS_H_
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14 #define _REG_DEFS_H_
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16 #include "dt_defs.h"
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18 #define BIT_SET(bit) (1<<bit)
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19 #define BIT_CLR(bit) (0<<bit)
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21 #define HAL_WORD_REG_WRITE(addr, val) \
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23 (*((volatile uint32_t *)(addr&0xfffffffc))) = (uint32_t)(val); \
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26 #define HAL_WORD_REG_READ(addr) (*((volatile uint32_t *)(addr&0xfffffffc)))
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29 #define HAL_HALF_WORD_REG_WRITE(addr, val) \
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31 (*((volatile uint16_t *)(addr&0xfffffffe))) = (uint16_t)(val); \
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34 #define HAL_HALF_WORD_REG_READ(addr) (*((volatile uint16_t *)(addr&0xfffffffe)))
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37 #define HAL_BYTE_REG_WRITE(addr, val) \
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39 (*((volatile uint8_t *)(addr))) = (uint8_t)(val); \
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42 #define HAL_BYTE_REG_READ(addr) (*((volatile uint8_t *)(addr)))
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44 /***** REGISTER BASE ADDRESS DEFINITION *****/
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45 #define RESET_VECTOR_ADDRESS 0x8e0000
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46 /********************************************/
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48 /***** REGISTER BASE ADDRESS DEFINITION *****/
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49 #define USB_CTRL_BASE_ADDRESS 0x00010000
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50 //#define PCIE_BASE_ADDRESS 0x00020000
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51 #define RST_BASE_ADDRESS 0x00050000
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52 #define UART_BASE_ADDRESS 0x00051000
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53 #define GPIO_BASE_ADDRESS 0x00052000
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54 #define HOST_DMA_BASE_ADDRESS 0x00053000
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55 #define GMAC_BASE_ADDRESS 0x00054000
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56 #define USB_DMA_BASE_ADDRESS 0x00055000
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57 #define CPU_PLL_BASE_ADDRESS 0x00056000
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58 #define SPI_REG_BASE_ADDRESS 0x0005B000
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59 #define EEPROM_BASE_ADDRESS 0x1f000000
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60 #define WLAN_BASE_ADDRESS 0x10ff0000
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61 /*******************************************************************************/
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63 #define MAGPEI_REG_RST_BASE_ADDR RST_BASE_ADDRESS
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65 #define REG_GENERAL_TIMER_OFFSET 0x0
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66 #define REG_GENERAL_TIMER_RELOAD_OFFSET 0x4
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67 #define REG_WATCHDOG_TIMER_CONTROL_OFFSET 0x8
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68 #define REG_WATCHDOG_TIMER_OFFSET 0xC
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69 #define REG_RESET_OFFSET 0x10
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70 #define REG_BOOTSTRAP 0x14
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71 #define REG_AHB_ARB 0x18
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72 #define REG_REVISION_ID 0x90
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75 #define MAGPEI_REG_RST_GENERAL_TIMER_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_OFFSET)
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76 #define MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_RELOAD_OFFSET)
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77 #define MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_CONTROL_OFFSET)
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78 #define MAGPIE_REG_RST_WDT_TIMER_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_OFFSET)
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79 #define MAGPIE_REG_RST_RESET_ADDR (RST_BASE_ADDRESS+REG_RESET_OFFSET)
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80 #define MAGPIE_REG_RST_BOOTSTRAP_ADDR (RST_BASE_ADDRESS+REG_BOOTSTRAP)
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81 #define MAGPIE_REG_AHB_ARB_ADDR (RST_BASE_ADDRESS+REG_AHB_ARB)
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82 #define MAGPIE_REG_REVISION_ID_ADDR (RST_BASE_ADDRESS+REG_REVISION_ID)
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84 #define MAGPEI_REG_RST_GENERAL_TIMER (*((volatile u32_t*)(MAGPEI_REG_RST_GENERAL_TIMER_ADDR)))
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85 #define MAGPIE_REG_RST_GENERAL_TIMER_RLD (*((volatile u32_t*)(MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR)))
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86 #define MAGPIE_REG_RST_WDT_TIMER_CTRL (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)))
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87 #define MAGPIE_REG_RST_WDT_TIMER (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_ADDR)))
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88 #define MAGPIE_REG_RST_RESET (*((volatile u32_t*)(MAGPIE_REG_RST_RESET_ADDR)))
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89 #define MAGPIE_REG_RST_BOOTSTRAP (*((volatile u32_t*)(MAGPIE_REG_RST_BOOTSTRAP_ADDR)))
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90 #define MAGPIE_REG_AHB_ARB (*((volatile u32_t*)(MAGPIE_REG_AHB_ARB_ADDR)))
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91 #define MAGPIE_REG_REVISION_ID (*((volatile u32_t*)(MAGPIE_REG_REVISION_ID_ADDR)))
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94 /*******************************************************************************/
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95 /* USB DMA Register*/
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97 #define MAGPIE_REG_USB_INTERRUPT_ADDR USB_DMA_BASE_ADDRESS
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98 #define MAGPIE_REG_USB_INTERRUPT_MASK_ADDR (USB_DMA_BASE_ADDRESS + 0x4)
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100 #define MAGPIE_REG_USB_RX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x800)
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101 #define MAGPIE_REG_USB_RX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x804)
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102 #define MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x808)
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103 #define MAGPIE_REG_USB_RX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x814)
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104 #define MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x818)
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105 #define MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x81C)
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107 #define MAGPIE_REG_USB_RX1_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x900)
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108 #define MAGPIE_REG_USB_RX1_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x904)
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109 #define MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x908)
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110 #define MAGPIE_REG_USB_RX1_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x914)
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111 #define MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x918)
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112 #define MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x91C)
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114 #define MAGPIE_REG_USB_RX2_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa00)
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115 #define MAGPIE_REG_USB_RX2_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa04)
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116 #define MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xa08)
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117 #define MAGPIE_REG_USB_RX2_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xa14)
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118 #define MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xa18)
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119 #define MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xa1C)
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121 #define MAGPIE_REG_USB_TX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC00)
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122 #define MAGPIE_REG_USB_TX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC04)
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123 #define MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xC08)
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124 #define MAGPIE_REG_USB_TX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xC10)
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125 #define MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xC14)
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126 #define MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xC18)
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128 #define MAGPIE_REG_USB_INTERRUPT_TX0_END (1<<24) //0x1000000
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129 #define MAGPIE_REG_USB_INTERRUPT_TX0_COMPL (1<<16) //0x10000
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130 #define MAGPIE_REG_USB_INTERRUPT_RX2_END (1<<10) //0x00400
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131 #define MAGPIE_REG_USB_INTERRUPT_RX1_END (1<<9) //0x00200
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132 #define MAGPIE_REG_USB_INTERRUPT_RX0_END (1<<8) //0x0100
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133 #define MAGPIE_REG_USB_INTERRUPT_RX2_COMPL (1<<2) //0x00004
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135 #define MAGPIE_REG_USB_INTERRUPT_RX1_COMPL (1<<1) //0x00002
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136 #define MAGPIE_REG_USB_INTERRUPT_RX0_COMPL (1<<0) //0x00001
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139 #define MAGPIE_REG_USB_INTERRUPT (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_ADDR)))
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140 #define MAGPIE_REG_USB_INTERRUPT_MASK (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_MASK_ADDR)))
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142 #define MAGPIE_REG_USB_RX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DESC_START_ADDR)))
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143 #define MAGPIE_REG_USB_RX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DMA_START_ADDR)))
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144 #define MAGPIE_REG_USB_RX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR)))
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145 #define MAGPIE_REG_USB_RX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_STATE_ADDR)))
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146 #define MAGPIE_REG_USB_RX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR)))
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147 #define MAGPIE_REG_USB_RX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR)))
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150 #define MAGPIE_REG_USB_RX1_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DESC_START_ADDR)))
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151 #define MAGPIE_REG_USB_RX1_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DMA_START_ADDR)))
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152 #define MAGPIE_REG_USB_RX1_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR)))
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153 #define MAGPIE_REG_USB_RX1_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_STATE_ADDR)))
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154 #define MAGPIE_REG_USB_RX1_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR)))
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155 #define MAGPIE_REG_USB_RX1_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR)))
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157 #define MAGPIE_REG_USB_RX2_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DESC_START_ADDR)))
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158 #define MAGPIE_REG_USB_RX2_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DMA_START_ADDR)))
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159 #define MAGPIE_REG_USB_RX2_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR)))
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160 #define MAGPIE_REG_USB_RX2_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_STATE_ADDR)))
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161 #define MAGPIE_REG_USB_RX2_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR)))
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162 #define MAGPIE_REG_USB_RX2_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR)))
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165 #define MAGPIE_REG_USB_TX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DESC_START_ADDR)))
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166 #define MAGPIE_REG_USB_TX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DMA_START_ADDR)))
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167 #define MAGPIE_REG_USB_TX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR)))
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168 #define MAGPIE_REG_USB_TX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_STATE_ADDR)))
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169 #define MAGPIE_REG_USB_TX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR)))
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170 #define MAGPIE_REG_USB_TX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR)))
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174 /*******************************************************************************/
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175 /* CPU PLL Register*/
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177 #define REG_CPU_PLL_OFFSET 0x0
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178 #define REG_CPU_PLL_BYPASS_OFFSET 0x4
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179 #define REG_USB_DIVIDE_OFFSET 0x8
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180 #define REG_ETH_PLL_OFFSET 0xC
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181 #define REG_ETH_PLL_BYPASS_OFFSET 0x10
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182 #define REG_ETH_TXRX_DIVIDE_OFFSET 0x14
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183 #define REG_ETH_XTAL_DIVIDE_OFFSET 0x18
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184 #define REG_PCIE_PLL_CONFIG_OFFSET 0x1C
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185 #define REG_PCIE_DITHER_DIV_MAX_OFFSET 0x20
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186 #define REG_PCIE_PLL_DITHER_DIV_MIN_OFFSET 0x24
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187 #define REG_PCIE_PLL_DITHER_STEP_OFFSET 0x28
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188 #define REG_CURRENT_PCIE_PLL_DITHER_OFFSET 0x2c
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189 #define REG_USB_SUSPEND_ENABLE_OFFSET 0x30
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192 #define MAGPIE_REG_CPU_PLL_ADDR (CPU_PLL_BASE_ADDRESS + REG_CPU_PLL_OFFSET)
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193 #define MAGPIE_REG_CPU_PLL_BYPASS_ADDR (CPU_PLL_BASE_ADDRESS + REG_CPU_PLL_BYPASS_OFFSET)
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194 #define MAGPIE_REG_USB_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_USB_DIVIDE_OFFSET)
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195 #define MAGPIE_REG_ETH_PLL_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_PLL_OFFSET)
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196 #define MAGPIE_REG_ETH_PLL_BYPASS_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_PLL_BYPASS_OFFSET)
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197 #define MAGPIE_REG_ETH_TXRX_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_TXRX_DIVIDE_OFFSET)
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198 #define MAGPIE_REG_ETH_XTAL_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_XTAL_DIVIDE_OFFSET)
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199 #define MAGPIE_REG_PCIE_PLL_CONFIG_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_CONFIG_OFFSET)
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200 #define MAGPIE_REG_PCIE_DITHER_DIV_MAX_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_DITHER_DIV_MAX_OFFSET)
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201 #define MAGPIE_REG_PCIE_PLL_DITHER_DIV_MIN_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_DITHER_DIV_MIN_OFFSET)
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202 #define MAGPIE_REG_PCIE_PLL_DITHER_STEP_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_DITHER_STEP_OFFSET)
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203 #define MAGPIE_REG_CURRENT_PCIE_PLL_DITHER_ADDR (CPU_PLL_BASE_ADDRESS + REG_CURRENT_PCIE_PLL_DITHER_OFFSET)
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204 #define MAGPIE_REG_SUSPEND_ENABLE_ADDR (CPU_PLL_BASE_ADDRESS + REG_USB_SUSPEND_ENABLE_OFFSET)
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207 /*******************************************************************************/
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210 #define REG_GPIO_OE 0x0
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211 #define REG_GPIO_IN 0x4
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212 #define REG_GPIO_OUT 0x8
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213 #define REG_GPIO_SET 0xC
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214 #define REG_GPIO_CLEAR 0x10
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215 #define REG_GPIO_INT 0x14
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216 #define REG_GPIO_INT_TYPE 0x18
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217 #define REG_GPIO_INT_POLARITY 0x1C
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218 #define REG_GPIO_PENDING 0x20
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219 #define REG_GPIO_INT_MASK 0x24
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220 #define REG_GPIO_FUNCTION 0x28
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223 #define MAGPIE_REG_GPIO_OE (GPIO_BASE_ADDRESS + REG_GPIO_OE)
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224 #define MAGPIE_REG_GPIO_IN (GPIO_BASE_ADDRESS + REG_GPIO_IN)
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225 #define MAGPIE_REG_GPIO_OUT (GPIO_BASE_ADDRESS + REG_GPIO_OUT)
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226 #define MAGPIE_REG_GPIO_SET (GPIO_BASE_ADDRESS + REG_GPIO_SET)
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227 #define MAGPIE_REG_GPIO_CLEAR (GPIO_BASE_ADDRESS + REG_GPIO_CLEAR)
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228 #define MAGPIE_REG_GPIO_INT (GPIO_BASE_ADDRESS + REG_GPIO_INT)
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229 #define MAGPIE_REG_GPIO_INT_TYPE (GPIO_BASE_ADDRESS + REG_GPIO_INT_TYPE)
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230 #define MAGPIE_REG_GPIO_INT_POLARITY (GPIO_BASE_ADDRESS + REG_GPIO_INT_POLARITY)
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231 #define MAGPIE_REG_GPIO_PENDING (GPIO_BASE_ADDRESS + REG_GPIO_PENDING)
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232 #define MAGPIE_REG_GPIO_INT_MASK (GPIO_BASE_ADDRESS + REG_GPIO_INT_MASK)
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233 #define MAGPIE_REG_GPIO_FUNCTION (GPIO_BASE_ADDRESS + REG_GPIO_FUNCTION)
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236 /*******************************************************************************/
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237 /* SPI Flash Register*/
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238 #define MAGPEI_REG_SPI_BASE_ADDR SPI_REG_BASE_ADDRESS
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240 #define REG_SPI_CS_OFFSET 0x0
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241 #define REG_SPI_AO_OFFSET 0x4
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242 #define REG_SPI_D_OFFSET 0x8
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243 #define REG_SPI_CLKDIV_OFFSET 0x1C
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245 #define MAGPIE_REG_SPI_CS_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_CS_OFFSET)
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246 #define MAGPIE_REG_SPI_AO_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_AO_OFFSET)
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247 #define MAGPIE_REG_SPI_D_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_D_OFFSET)
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248 #define MAGPIE_REG_SPI_CLKDIV_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_CLKDIV_OFFSET)
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