2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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43 #include "athos_api.h"
47 extern uint16_t u8UsbConfigValue;
48 extern uint16_t u8UsbInterfaceValue;
49 extern uint16_t u8UsbInterfaceAlternateSetting;
53 void mUsbEPMap(uint8_t EPn, uint8_t MAP)
55 //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1));
57 uint8_t reg = (0x30+(EPn-1));
59 // A_PRINTF("=>mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
60 USB_BYTE_REG_WRITE(reg, MAP );
62 // A_PRINTF("<=mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
64 //zfUartSendStr("mUsbEPMap\r\n");
65 //zfUartSendStrAndHex("EPn=", EPn);
66 //zfUartSendStrAndHex("MAP=", MAP);
69 void mUsbFIFOMap(uint8_t FIFOn, uint8_t MAP)
71 //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x80+FIFOn);
74 uint8_t reg = (0x80+FIFOn);
78 // A_PRINTF("=>mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
79 USB_BYTE_REG_WRITE( reg, MAP );
81 // A_PRINTF("<=mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
82 //zfUartSendStr("mUsbFIFOMap\r\n");
83 //zfUartSendStrAndHex("FIFOn=", FIFOn);
84 //zfUartSendStrAndHex("MAP=", MAP);
87 void mUsbFIFOConfig(uint8_t FIFOn, uint8_t cfg)
89 //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn);
91 uint8_t reg = (0x90+FIFOn);
93 // A_PRINTF("=>mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg));
94 USB_BYTE_REG_WRITE( reg, cfg );
96 // A_PRINTF("<=mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg));
97 //zfUartSendStr((uint8_t *)"mUsbFIFOConfig\r\n");
98 //zfUartSendStrAndHex((uint8_t *)"FIFOn=", FIFOn);
99 //zfUartSendStrAndHex((uint8_t *)"cfg=", cfg);
102 void mUsbEPMxPtSzHigh(uint8_t EPn, uint8_t dir, uint16_t size)
104 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1));
105 //*reg = (size >> 8) & 0xf;
106 uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+(EPn << 1)));
108 // A_PRINTF("=>mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg));
109 USB_BYTE_REG_WRITE(reg, ((size >> 8) & 0xff));
111 // A_PRINTF("<=mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg));
112 //USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf));
115 void mUsbEPMxPtSzLow(uint8_t EPn, uint8_t dir, uint16_t size)
117 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1));
118 //*reg = (size & 0xff);
120 uint8_t reg = (ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+(EPn << 1)));
121 // A_PRINTF("=>mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg));
122 USB_BYTE_REG_WRITE(reg, (size & 0xff));
124 // A_PRINTF("<=mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg));
127 void mUsbEPinHighBandSet(uint8_t EPn, uint8_t dir, uint16_t size)
130 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1));
132 //*reg &= ~(BIT6 | BIT5);
133 //*reg |= (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
135 uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1));
136 // uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
137 uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
139 // A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg));
140 USB_BYTE_REG_WRITE(reg, (USB_BYTE_REG_READ(reg)&~(BIT6 | BIT5)));
141 USB_BYTE_REG_WRITE(reg, (USB_BYTE_REG_READ(reg)|reg2));
143 // A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg));
149 #define mUsbEPMap( EPn, MAP) USB_BYTE_REG_WRITE( (0x30+(EPn-1)), MAP )
151 #define mUsbFIFOMap( FIFOn, MAP) USB_BYTE_REG_WRITE( (0x80+FIFOn), MAP )
153 #define mUsbFIFOConfig(FIFOn, cfg) USB_BYTE_REG_WRITE( (0x90+FIFOn), cfg )
155 #define mUsbEPMxPtSzHigh(EPn, dir, size) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf))
157 #define mUsbEPMxPtSzLow(EPn, dir, size) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1)), (size & 0xff))
159 #define mUsbEPinHighBandSet( EPn, dir, size) \
161 USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)), \
162 (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1))&(~(BIT6 | BIT5))))); \
163 USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)), \
164 (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)|((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir))))); \
169 /////////////////////////////////////////////////////
170 // vUsbFIFO_EPxCfg_HS(void)
172 // 1. Configure the FIFO and EPx map
175 /////////////////////////////////////////////////////
176 void vUsbFIFO_EPxCfg_HS(void)
181 switch (u8UsbConfigValue)
183 #if (HS_CONFIGURATION_NUMBER >= 1)
184 // Configuration 0X01
186 switch (u8UsbInterfaceValue)
188 #if (HS_C1_INTERFACE_NUMBER >= 1)
191 switch (u8UsbInterfaceAlternateSetting)
193 #if (HS_C1_I0_ALT_NUMBER >= 1)
194 // AlternateSetting 0
196 #if (HS_C1_I0_A0_EP_NUMBER >= 1)
198 mUsbEPMap(EP1, HS_C1_I0_A0_EP1_MAP);
199 mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_MAP);
201 mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START+1, HS_C1_I0_A0_EP1_FIFO_MAP); //ryan
203 mUsbFIFOConfig(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_CONFIG);
205 for(i = HS_C1_I0_A0_EP1_FIFO_START + 1 ;
206 i < HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO ;
209 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
212 mUsbEPMxPtSzHigh(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
213 mUsbEPMxPtSzLow(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
214 mUsbEPinHighBandSet(EP1 , HS_C1_I0_A0_EP1_DIRECTION , HS_C1_I0_A0_EP1_MAX_PACKET);
217 #if (HS_C1_I0_A0_EP_NUMBER >= 2)
219 mUsbEPMap(EP2, HS_C1_I0_A0_EP2_MAP);
220 mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_MAP);
222 mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START+1, HS_C1_I0_A0_EP2_FIFO_MAP);//ryan
224 mUsbFIFOConfig(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_CONFIG);
226 for(i = HS_C1_I0_A0_EP2_FIFO_START + 1 ;
227 i < HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO ;
230 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
233 mUsbEPMxPtSzHigh(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
234 mUsbEPMxPtSzLow(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
235 mUsbEPinHighBandSet(EP2 , HS_C1_I0_A0_EP2_DIRECTION , HS_C1_I0_A0_EP2_MAX_PACKET);
238 #if (HS_C1_I0_A0_EP_NUMBER >= 3)
240 mUsbEPMap(EP3, HS_C1_I0_A0_EP3_MAP);
241 mUsbFIFOMap(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_MAP);
242 mUsbFIFOConfig(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_CONFIG);
244 for(i = HS_C1_I0_A0_EP3_FIFO_START + 1 ;
245 i < HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO ;
248 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
251 mUsbEPMxPtSzHigh(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
252 mUsbEPMxPtSzLow(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
253 mUsbEPinHighBandSet(EP3 , HS_C1_I0_A0_EP3_DIRECTION , HS_C1_I0_A0_EP3_MAX_PACKET);
256 #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
258 mUsbEPMap(EP4, HS_C1_I0_A0_EP4_MAP);
259 mUsbFIFOMap(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_MAP);
260 mUsbFIFOConfig(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_CONFIG);
262 for(i = HS_C1_I0_A0_EP4_FIFO_START + 1 ;
263 i < HS_C1_I0_A0_EP4_FIFO_START + HS_C1_I0_A0_EP4_FIFO_NO ;
266 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
269 mUsbEPMxPtSzHigh(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
270 mUsbEPMxPtSzLow(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
271 mUsbEPinHighBandSet(EP4 , HS_C1_I0_A0_EP4_DIRECTION , HS_C1_I0_A0_EP4_MAX_PACKET);
274 //////////////////////////////////////////////////////////////
275 #if SYSTEM_MODULE_HP_EP5
276 #if (HS_C1_I0_A0_EP_NUMBER >= 5)
278 mUsbEPMap(EP5, HS_C1_I0_A0_EP5_MAP);
279 mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_MAP);
281 mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START+1, HS_C1_I0_A0_EP5_FIFO_MAP); //ryan
283 mUsbFIFOConfig(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_CONFIG);
285 for(i = HS_C1_I0_A0_EP5_FIFO_START + 1 ;
286 i < HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO ;
289 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) );
292 mUsbEPMxPtSzHigh(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) );
293 mUsbEPMxPtSzLow(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) );
294 mUsbEPinHighBandSet(EP5 , HS_C1_I0_A0_EP5_DIRECTION , HS_C1_I0_A0_EP5_MAX_PACKET);
296 #endif //SYSTEM_MODULE_HP_EP5
298 //////////////////////////////////////////////////////////////
299 #if SYSTEM_MODULE_HP_EP6
300 #if (HS_C1_I0_A0_EP_NUMBER >= 6)
302 mUsbEPMap(EP6, HS_C1_I0_A0_EP6_MAP);
303 mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_MAP);
305 mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START+1, HS_C1_I0_A0_EP6_FIFO_MAP); //ryan
307 mUsbFIFOConfig(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_CONFIG);
309 for(i = HS_C1_I0_A0_EP6_FIFO_START + 1 ;
310 i < HS_C1_I0_A0_EP6_FIFO_START + HS_C1_I0_A0_EP6_FIFO_NO ;
313 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
316 mUsbEPMxPtSzHigh(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) );
317 mUsbEPMxPtSzLow(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) );
318 mUsbEPinHighBandSet(EP6 , HS_C1_I0_A0_EP6_DIRECTION , HS_C1_I0_A0_EP6_MAX_PACKET);
321 #endif //SYSTEM_MODULE_HP_EP6
341 void vUsbFIFO_EPxCfg_FS(void)
346 switch (u8UsbConfigValue)
348 #if (FS_CONFIGURATION_NUMBER >= 1)
349 // Configuration 0X01
351 switch (u8UsbInterfaceValue)
353 #if (FS_C1_INTERFACE_NUMBER >= 1)
356 switch (u8UsbInterfaceAlternateSetting)
358 #if (FS_C1_I0_ALT_NUMBER >= 1)
359 // AlternateSetting 0
361 #if (FS_C1_I0_A0_EP_NUMBER >= 1)
363 mUsbEPMap(EP1, FS_C1_I0_A0_EP1_MAP);
364 mUsbFIFOMap(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_MAP);
365 mUsbFIFOConfig(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_CONFIG);
367 for(i = FS_C1_I0_A0_EP1_FIFO_START + 1 ;
368 i < FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO ;
371 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
374 mUsbEPMxPtSzHigh(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
375 mUsbEPMxPtSzLow(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
377 mUsbEPinHighBandSet(EP1 , FS_C1_I0_A0_EP1_DIRECTION, FS_C1_I0_A0_EP1_MAX_PACKET);
380 #if (FS_C1_I0_A0_EP_NUMBER >= 2)
382 mUsbEPMap(EP2, FS_C1_I0_A0_EP2_MAP);
383 mUsbFIFOMap(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_MAP);
384 mUsbFIFOConfig(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_CONFIG);
386 for(i = FS_C1_I0_A0_EP2_FIFO_START + 1 ;
387 i < FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO ;
390 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
393 mUsbEPMxPtSzHigh(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
394 mUsbEPMxPtSzLow(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
395 mUsbEPinHighBandSet(EP2 , FS_C1_I0_A0_EP2_DIRECTION, FS_C1_I0_A0_EP2_MAX_PACKET);
398 #if (FS_C1_I0_A0_EP_NUMBER >= 3)
400 mUsbEPMap(EP3, FS_C1_I0_A0_EP3_MAP);
401 mUsbFIFOMap(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_MAP);
402 mUsbFIFOConfig(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_CONFIG);
404 for(i = FS_C1_I0_A0_EP3_FIFO_START + 1 ;
405 i < FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO ;
408 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
411 mUsbEPMxPtSzHigh(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
412 mUsbEPMxPtSzLow(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
413 mUsbEPinHighBandSet(EP3 , FS_C1_I0_A0_EP3_DIRECTION, FS_C1_I0_A0_EP3_MAX_PACKET);
416 #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
418 mUsbEPMap(EP4, FS_C1_I0_A0_EP4_MAP);
419 mUsbFIFOMap(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_MAP);
420 mUsbFIFOConfig(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_CONFIG);
422 for(i = FS_C1_I0_A0_EP4_FIFO_START + 1 ;
423 i < FS_C1_I0_A0_EP4_FIFO_START + FS_C1_I0_A0_EP4_FIFO_NO ;
426 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
429 mUsbEPMxPtSzHigh(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
430 mUsbEPMxPtSzLow(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
431 mUsbEPinHighBandSet(EP4 , FS_C1_I0_A0_EP4_DIRECTION, FS_C1_I0_A0_EP4_MAX_PACKET);
434 #if (FS_C1_I0_A0_EP_NUMBER >= 5)
436 mUsbEPMap(EP5, FS_C1_I0_A0_EP5_MAP);
437 mUsbFIFOMap(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_MAP);
438 mUsbFIFOConfig(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_CONFIG);
440 for(i = FS_C1_I0_A0_EP5_FIFO_START + 1 ;
441 i < FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO ;
444 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) );
447 mUsbEPMxPtSzHigh(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff));
448 mUsbEPMxPtSzLow(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff));
449 mUsbEPinHighBandSet(EP5 , FS_C1_I0_A0_EP5_DIRECTION, FS_C1_I0_A0_EP5_MAX_PACKET);