2 #include <Magpie_api.h>
9 /**************************Constants******************************/
11 /*************************Data types*******************************/
13 MAG_REG_AHB_RESET = 0x00050010,
14 MAG_REG_AHB_ARB = 0x00050018
17 #define PCI_AHB_ARB_ENB (1 << 3)
18 #define PCI_AHB_RESET_DMA (1 << 13)
19 #define PCI_AHB_RESET_DMA_HST_RAW (1 << 14)
20 #define PCI_AHB_RESET_DMA_HST (1 << 15)
22 /*********************************softC************************/
23 typedef struct __pci_softc{
28 #define ret_pkt sw.send_buf_done
29 #define indicate_pkt sw.recv_buf
30 #define htc_ctx sw.context
31 /*********************************DEFINES**********************************/
32 #define hdl_to_softc(_hdl) (__pci_softc_t *)(_hdl)
34 #define PCI_ENG_NUM(_eng) HIF_PCI_PIPE_##_eng
36 #define PCI_INIT_PIPE { \
45 #define rx_pipe0 DMA_ENGINE_RX0
46 #define rx_pipe1 DMA_ENGINE_RX1
47 #define tx_pipe0 DMA_ENGINE_TX0
48 #define tx_pipe1 DMA_ENGINE_TX1
50 #define dbg_pci_loopback 0
52 #define PCI_DBG_MODE 0
54 void __pci_cfg_pipe(hif_handle_t hdl, int pipe, int num_desc);
55 int __pci_get_max_msg_len(hif_handle_t hdl, int pipe);
56 void __pci_return_recv(hif_handle_t hdl, int pipe, VBUF *buf);
57 void __pci_reset(void);
58 void __pci_enable(void);
61 /***********************************Globals********************************/
63 * @brief Engines are fixed
65 __pci_softc_t pci_sc = {0};
68 /**************************************APIs********************************/
71 __pci_reg_read(A_UINT32 addr)
73 return *((volatile A_UINT32 *)addr);
77 __pci_reg_write(A_UINT32 addr, A_UINT32 val)
79 *((volatile A_UINT32 *)addr) = val;
83 __pci_get_pipe(dma_engine_t eng)
87 return HIF_PCI_PIPE_RX0;
89 return HIF_PCI_PIPE_RX1;
91 return HIF_PCI_PIPE_RX2;
93 return HIF_PCI_PIPE_RX3;
95 return HIF_PCI_PIPE_TX0;
97 return HIF_PCI_PIPE_TX1;
104 __pci_get_tx_eng(hif_pci_pipe_tx_t pipe)
107 case HIF_PCI_PIPE_TX0:
108 return DMA_ENGINE_TX0;
110 case HIF_PCI_PIPE_TX1:
111 return DMA_ENGINE_TX1;
114 return DMA_ENGINE_MAX;
118 __pci_get_rx_eng(hif_pci_pipe_rx_t pipe)
121 case HIF_PCI_PIPE_RX0:
122 return DMA_ENGINE_RX0;
124 case HIF_PCI_PIPE_RX1:
125 return DMA_ENGINE_RX1;
127 case HIF_PCI_PIPE_RX2:
128 return DMA_ENGINE_RX2;
130 case HIF_PCI_PIPE_RX3:
131 return DMA_ENGINE_RX3;
134 return DMA_ENGINE_MAX;
145 * Grant access to the internal memory for PCI DMA
148 r_data = __pci_reg_read(MAG_REG_AHB_ARB);
149 r_data |= PCI_AHB_ARB_ENB;
150 __pci_reg_write(MAG_REG_AHB_ARB, r_data);
155 * XXX: Move this to RAM
160 volatile A_UINT32 r_data;
163 * Poll until the Host has reset
165 A_PRINTF("Waiting for host reset..");
167 r_data = __pci_reg_read(MAG_REG_AHB_RESET);
169 if ( r_data & PCI_AHB_RESET_DMA_HST_RAW)
172 A_PRINTF("received.\n");
175 * Pull the AHB out of reset
178 r_data = __pci_reg_read(MAG_REG_AHB_RESET);
179 r_data &= ~PCI_AHB_RESET_DMA;
180 __pci_reg_write(MAG_REG_AHB_RESET, r_data);
185 * Put the AHB into reset
188 r_data = __pci_reg_read(MAG_REG_AHB_RESET);
189 r_data |= PCI_AHB_RESET_DMA;
190 __pci_reg_write(MAG_REG_AHB_RESET, r_data);
195 * Pull the AHB out of reset
198 r_data = __pci_reg_read(MAG_REG_AHB_RESET);
199 r_data &= ~PCI_AHB_RESET_DMA;
200 __pci_reg_write(MAG_REG_AHB_RESET, r_data);
208 __pci_boot_init(void)
213 dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_PCI);
214 dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_PCI);
216 dma_lib_rx_config(DMA_ENGINE_RX0, PCI_MAX_BOOT_DESC,
217 PCI_MAX_DATA_PKT_LEN);
225 * @return hif_handle_t
228 __pci_init(HIF_CONFIG *pConfig)
234 * Initializing the other TX engines
236 dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_PCI);
237 dma_lib_tx_init(DMA_ENGINE_TX1, DMA_IF_PCI);
240 * Initializing the other RX engines
242 dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_PCI);
243 dma_lib_rx_init(DMA_ENGINE_RX1, DMA_IF_PCI);
244 dma_lib_rx_init(DMA_ENGINE_RX2, DMA_IF_PCI);
245 dma_lib_rx_init(DMA_ENGINE_RX3, DMA_IF_PCI);
250 * @brief Configure the receive pipe
257 __pci_cfg_pipe(hif_handle_t hdl, int pipe, int num_desc)
262 eng = __pci_get_rx_eng(pipe);
264 if (eng == DMA_ENGINE_MAX) {
265 A_PRINTF("Bad Engine number\n");
269 desc_len = __pci_get_max_msg_len(hdl, pipe);
271 dma_lib_rx_config(eng, num_desc, desc_len);
274 * @brief Start the interface
279 __pci_start(hif_handle_t hdl)
284 * @brief Register callback of thre HTC
290 __pci_reg_callback(hif_handle_t hdl, HIF_CALLBACK *sw)
292 __pci_softc_t *sc = &pci_sc;
294 sc->htc_ctx = sw->context;
295 sc->indicate_pkt = sw->recv_buf;
296 sc->ret_pkt = sw->send_buf_done;
300 * @brief reap the transmit queue for trasnmitted packets
306 __pci_reap_xmitted(__pci_softc_t *sc, dma_engine_t eng_no)
311 pipe = __pci_get_pipe(eng_no);
313 vbuf = dma_lib_reap_xmitted(eng_no);
316 sc->ret_pkt(vbuf, sc->htc_ctx);
318 A_PRINTF("Empty RX Reap\n");
324 * @brief reap the receive queue for vbuf's on the specified
331 __pci_reap_recv(__pci_softc_t *sc, dma_engine_t eng_no)
335 vbuf = dma_lib_reap_recv(eng_no);
338 sc->indicate_pkt(NULL, vbuf, sc->htc_ctx);
340 A_PRINTF("Empty TX Reap \n");
343 * @brief The interrupt handler
348 __pci_isr_handler(hif_handle_t hdl)
350 __pci_softc_t *sc = &pci_sc;
357 if( dma_lib_xmit_done(DMA_ENGINE_TX1) ) {
358 __pci_reap_xmitted(sc,DMA_ENGINE_TX1);
361 if( dma_lib_recv_pkt(DMA_ENGINE_RX3) ) {
362 __pci_reap_recv(sc, DMA_ENGINE_RX3);
372 if( dma_lib_xmit_done(DMA_ENGINE_TX1) ) {
373 __pci_reap_xmitted(sc,DMA_ENGINE_TX1);
376 if( dma_lib_recv_pkt(DMA_ENGINE_RX2) ) {
377 __pci_reap_recv(sc, DMA_ENGINE_RX2);
387 if( dma_lib_xmit_done(DMA_ENGINE_TX1) ) {
388 __pci_reap_xmitted(sc,DMA_ENGINE_TX1);
391 if( dma_lib_recv_pkt(DMA_ENGINE_RX1) ) {
392 __pci_reap_recv(sc, DMA_ENGINE_RX1);
402 if( dma_lib_xmit_done(DMA_ENGINE_TX0) ) {
403 __pci_reap_xmitted(sc,DMA_ENGINE_TX0);
407 if( dma_lib_recv_pkt(DMA_ENGINE_RX0) ) {
408 __pci_reap_recv(sc, DMA_ENGINE_RX0);
416 * @brief transmit the vbuf from the specified pipe
425 __pci_xmit_buf(hif_handle_t hdl, int pipe, VBUF *vbuf)
429 eng = __pci_get_tx_eng(pipe);
431 if (eng == DMA_ENGINE_MAX) {
432 A_PRINTF("Invalid Pipe number\n");
436 return dma_lib_hard_xmit(eng, vbuf);
439 * @brief Submit the receive vbuf into the receive queue
446 __pci_return_recv(hif_handle_t hdl, int pipe, VBUF *buf)
450 eng = __pci_get_rx_eng(pipe);
452 if (eng == DMA_ENGINE_MAX)
455 dma_lib_return_recv(eng, buf);
458 * @brief Is this pipe number supported
466 __pci_is_pipe_supported(hif_handle_t hdl, int pipe)
468 if (pipe >= 0 && pipe <= 4)
474 * @brief maximum message length this pipe can support
482 __pci_get_max_msg_len(hif_handle_t hdl, int pipe)
484 if( pipe == HIF_PCI_PIPE_TX0 || pipe == HIF_PCI_PIPE_RX0)
485 return PCI_MAX_CMD_PKT_LEN;
487 return PCI_MAX_DATA_PKT_LEN;
490 * @brief return the header room required by this HIF
497 __pci_get_reserved_headroom(hif_handle_t hdl)
502 * @brief Device shutdown, HIF reset required
507 __pci_shutdown(hif_handle_t hdl)
513 __pci_get_def_pipe(hif_handle_t handle, A_UINT8 *pipe_rx, A_UINT8 *pipe_tx)
515 *pipe_rx = HIF_PCI_PIPE_RX0;
516 *pipe_tx = HIF_PCI_PIPE_TX0;
519 * @brief This install the API's of the HIF
524 hif_pci_module_install(struct hif_api *apis)
527 apis->_init = __pci_init;
528 apis->_start = __pci_start;
529 apis->_config_pipe = __pci_cfg_pipe;
530 apis->_isr_handler = __pci_isr_handler;
531 apis->_send_buffer = __pci_xmit_buf;
532 apis->_return_recv_buf = __pci_return_recv;
533 apis->_is_pipe_supported = __pci_is_pipe_supported;
534 apis->_get_max_msg_len = __pci_get_max_msg_len;
535 apis->_register_callback = __pci_reg_callback;
536 apis->_shutdown = __pci_shutdown;
537 apis->_get_reserved_headroom = __pci_get_reserved_headroom;
538 apis->_get_default_pipe = __pci_get_def_pipe;
542 cmnos_pci_module_install(struct pci_api *apis)
544 apis->pci_boot_init = __pci_boot_init;