1 /************************************************************************/
2 /* Copyright (c) 2013 Qualcomm Atheros, All Rights Reserved. */
4 /* Module Name : desc_def.h */
7 /* This module contains DMA descriptor related definitions. */
12 /************************************************************************/
24 volatile u16_t ctrl; // Descriptor control
25 volatile u16_t status; // Descriptor status
27 volatile u16_t totalLen; // Total length
28 volatile u16_t dataSize; // Data size
31 volatile u16_t status; // Descriptor status
32 volatile u16_t ctrl; // Descriptor control
33 volatile u16_t dataSize; // Data size
34 volatile u16_t totalLen; // Total length
36 struct zsDmaDesc* lastAddr; // Last address of this chain
37 volatile u32_t dataAddr; // Data buffer address
38 struct zsDmaDesc* nextAddr; // Next TD address
42 /* Tx5 Dn Rx Up Int */
44 #define ZM_TERMINATOR_NUMBER_B 8
46 #if ZM_BAR_AUTO_BA == 1
47 #define ZM_TERMINATOR_NUMBER_BAR 1
49 #define ZM_TERMINATOR_NUMBER_BAR 0
52 #if ZM_INT_USE_EP2 == 1
53 #define ZM_TERMINATOR_NUMBER_INT 1
55 #define ZM_TERMINATOR_NUMBER_INT 0
58 #define ZM_TX_DELAY_DESC_NUM 16
59 #define ZM_TERMINATOR_NUMBER (8 + ZM_TERMINATOR_NUMBER_BAR + \
60 ZM_TERMINATOR_NUMBER_INT + \
64 #define ZM_BLOCK_SIZE (256+64)
65 #define ZM_DESCRIPTOR_SIZE (sizeof(struct zsDmaDesc))
68 //#define ZM_FRAME_MEMORY_BASE 0x100000
72 //#define ZM_FRAME_MEMROY_SIZE 0xf000
74 //#define ZM_FRAME_MEMROY_SIZE 0x17000
79 #define ZM_FRAME_MEMROY_SIZE (ZM_BLOCK_SIZE+ZM_DESCRIPTOR_SIZE)*(160+60) + \
80 (ZM_DESCRIPTOR_SIZE*ZM_TERMINATOR_NUMBER)+64
83 #define ZM_BLOCK_NUMBER ((ZM_FRAME_MEMROY_SIZE-(ZM_DESCRIPTOR_SIZE* \
84 ZM_TERMINATOR_NUMBER)-64)/(ZM_BLOCK_SIZE \
86 #define ZM_DESC_NUMBER (ZM_BLOCK_NUMBER + ZM_TERMINATOR_NUMBER)
88 #define ZM_DESCRIPTOR_BASE ZM_FRAME_MEMORY_BASE
89 #define ZM_BLOCK_BUFFER_BASE (((((ZM_BLOCK_NUMBER+ZM_TERMINATOR_NUMBER) \
90 *ZM_DESCRIPTOR_SIZE) >> 6) << 6) + 0x40 \
91 + ZM_FRAME_MEMORY_BASE)
93 #define ZM_DOWN_BLOCK_RATIO 2
94 #define ZM_RX_BLOCK_RATIO 1
95 /* Tx 16*2 = 32 packets => 32*(5*320) */
96 #define ZM_TX_BLOCK_NUMBER ZM_BLOCK_NUMBER * ZM_DOWN_BLOCK_RATIO / \
97 (ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO)
98 #define ZM_RX_BLOCK_NUMBER ZM_BLOCK_NUMBER-ZM_TX_BLOCK_NUMBER
99 //ZM_BLOCK_NUMBER * ZM_RX_BLOCK_RATIO / \
100 //(ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO)
103 #define ZM_TX_DELAY_DESC_BASE ZM_FRAME_MEMORY_BASE + ZM_DESCRIPTOR_SIZE*(ZM_TERMINATOR_NUMBER-ZM_TX_DELAY_DESC_NUM)
107 #define ZM_ERR_FS_BIT 1
108 #define ZM_ERR_LS_BIT 2
109 #define ZM_ERR_OWN_BITS 3
110 #define ZM_ERR_DATA_SIZE 4
111 #define ZM_ERR_TOTAL_LEN 5
112 #define ZM_ERR_DATA 6
116 /* Status bits definitions */
117 /* Own bits definitions */
118 #define ZM_OWN_BITS_MASK 0x3
119 #define ZM_OWN_BITS_SW 0x0
120 #define ZM_OWN_BITS_HW 0x1
121 #define ZM_OWN_BITS_SE 0x2
123 /* Control bits definitions */
124 /* First segament bit */
125 #define ZM_LS_BIT 0x100
126 /* Last segament bit */
127 #define ZM_FS_BIT 0x200
132 struct zsDmaDesc* head;
133 struct zsDmaDesc* terminator;
140 extern struct zsDmaDesc* zfDmaGetPacket(struct zsDmaQueue* q);
141 extern void zfDmaReclaimPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc);
142 extern void zfDmaPutPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc);
144 #endif /* #ifndef _DESC_DEFS_H */