2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include "athos_api.h"
38 #if SYSTEM_MODULE_SFLASH
41 #include "sflash_api.h"
43 /*******************************************
44 * Definitions of module internal constant *
45 *******************************************/
47 /* Definitions of base address and Flash sise -> Project dependent */
48 #define ZM_SPI_REGISTER_BASE SPI_REG_BASE_ADDRESS /* 0x0005B000 */
49 #define ZM_SPI_FLASH_BASE SPI_FLASH_BASE /* 0x0F000000 */
50 #define ZM_SPI_FLASH_MAX_ADDR SPI_FLASH_MAX_ADDR /* 0x0FFFFFFF */
51 #define ZM_SPI_FLASH_MAX_SIZE SPI_FLASH_MAX_SIZE /* 0x01000000 */
54 * Base address of Clock and Reset Control Registers is 0x00050000
55 * Offset of Clock Control Register is 0x40
56 * SPI_SEL (bit 8) : Switch the function of I/O pin 19~22 between GPIO and SPI.
57 * 0 -> act as GPIO5~8;
58 * 1 -> act as SPI pins.
60 #define ZM_SPI_CLK_CTRL_ADDR 0x00050040
61 #define ZM_SPI_SPI_SEL_BIT 0x100
63 /* Definitions of Serial Flash constants -> According to standard or vendor dependent */
64 #define ZM_SFLASH_PAGE_SIZE 256
66 /* Definitions of OP Code -> According to standard or vendor dependent */
67 #define ZM_SFLASH_OP_READ 0x03 /* Read Data Bytes */
68 #define ZM_SFLASH_OP_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */
70 * For MXIC, sector erase : Command 0x20, size 4K bytes
71 * block erase : Command 0xD8, size 64K bytes
72 * chip earse : command 0x60 or 0xC7
73 * For Spansion, sector erase : Command 0x20 or 0xD8, size 64K bytes (For 64 KB sector devices, either command is valid and performs the same function.)
74 * block erase : Command 0xD8, size 256K bytes
75 * chip earse : command 0x60 or 0xC7, Uniform 64 KB Sector Product (For 64 KB sector devices, either command is valid and performs the same function.)
76 * 0xC7, Uniform 256 KB Sector Product
78 #define ZM_SFLASH_OP_SE 0x20 /* Sector Erase */
79 #define ZM_SFLASH_OP_BE 0xD8 /* Block Erase */
80 #define ZM_SFLASH_OP_CE 0xC7 /* Chip Erase */
81 #define ZM_SFLASH_OP_PP 0x02 /* Page Program */
82 #define ZM_SFLASH_OP_RDSR 0x05 /* Read from Status Register */
83 #define ZM_SFLASH_OP_WRSR 0x01 /* Write to Status Register */
84 #define ZM_SFLASH_OP_WREN 0x06 /* Write Enable */
85 #define ZM_SFLASH_OP_WRDI 0x04 /* Write Disable */
86 #define ZM_SFLASH_OP_RDID 0x9F /* Read Identification */
87 #define ZM_SFLASH_OP_DP 0xB9 /* Deep Power Down */
88 #define ZM_SFLASH_OP_RES 0xAB /* Release from Deep Power Down, Release from Deep Power Down and Read Electronic Signature */
90 /* Definitions of Status Register -> According to standard or vendor dependent */
91 /* Write in progress bit
92 * 1 = Device Busy. A Write Status Register, program, or erase operation is in progress
93 * 0 = Ready. Device is in standby mode and can accept commands.
95 #define ZM_SFLASH_STATUS_REG_WIP (1<<0)
96 /* Write enable latch bit
97 * 1 = Device accepts Write Status Register, program, or erase commands
98 * 0 = Ignores Write Status Register, program, or erase commands
100 #define ZM_SFLASH_STATUS_REG_WEL (1<<1)
101 /* Status register write disable bit
102 * 1 = Protects when WP#/ACC is low
103 * 0 = No protection, even when WP#/ACC is low
105 #define ZM_SFLASH_STATUS_REG_SRWD (1<<7)
107 /* Definitions of SPI Flash Controller -> SPI Flash Controller dependent */
108 /* SPI Flash Controller used in K2 project is part of Falcon's "Driver Support Logic" (DSL) block */
111 * ====== ==========================================================
112 * 0x0000 SPI control/status register (SPI_CS)
113 * 0x0004 SPI address/opcode register (SPI_AO)
114 * 0x0008 SPI data register (SPI_D)
118 * SPI control/status register (SPI_CS)
120 * Cold reset: (See field descriptions)
121 * Warm reset: (Same as cold reset)
124 * 3:0 - Transmit byte count. Determines the number of bytes
125 * transmitted from Falcon to the SPI device. Values of 1-8 are
126 * valid; other values are illegal. See the 'Notes' section below
127 * for details on how to use this field. Resets to an undefined
129 * 7:4 - Receive byte count. Determines the number of bytes received
130 * from the SPI device into Falcon. Values of 0-8 are valid;
131 * other values are illegal. See the 'Notes' section below for
132 * details on how to use this field. Resets to an undefined
134 * 8 - SPI transaction start. Only writes to this field are
135 * meaningful; reads always return 0. Resets to 0x0. For writes:
136 * * A write of '1' starts the SPI transaction defined by the
137 * transmit byte count, receive byte count, SPI_AO, and SPI_D
139 * * A write of '0' has no effect
140 * 9 - SPI chip select 1 enable. Resets to 0x0. See bug 12540.
141 * 0 - SP0 is enabled and SP1 is forced inactive.
142 * 1 - SP1 is enabled and SP0 is forced inactive.
144 * 16 - Transaction busy indication. Read-only; writes to this bit are
145 * ignored. Resets to 0x0.
146 * 0 - No SPI transaction is ongoing. Software may start a new
147 * SPI transaction by writing to the 'SPI transaction start'
148 * bit within this register.
149 * 1 - An SPI transaction presently is underway. Software must
150 * not try to start a new SPI transaction, nor may software
151 * alter the value of any field of the SPI_CS, SPI_AO, or
153 * 18:17 - Automatically-determined SPI address size. Read-only; writes
154 * to this bit are ignored. Resets to an undefined value, but
155 * then is updated after the autosizing process completes.
156 * 0 - SPI address size was determined to be 16 bits
157 * 1 - SPI address size was determined to be 24 bits
159 * 3 - Automatic SPI address size determination failed. Typical
160 * causes of this result:
161 * * The SPI device is missing
162 * * The SPI device is unprogrammed
163 * * The SPI device is programmed with an incorrect
165 * 20:19 - SPI autosize override. Resets to 0x0.
166 * 0 - Use automatically-determined SPI address size (see bits
167 * [18:17] of this register)
168 * 1 - Force SPI address size to 16 bits
169 * 2 - Force SPI address size to 24 bits
174 #define SPI_CS_ADDRESS MAGPIE_REG_SPI_CS_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000000)
175 /* 3:0 - Transmit byte count, values of 1-8 are valid */
176 #define SPI_CS_TXBCNT_MSB 3
177 #define SPI_CS_TXBCNT_LSB 0
178 #define SPI_CS_TXBCNT_MASK 0x0000000f
179 #define SPI_CS_TXBCNT_GET(x) (((x) & SPI_CS_TXBCNT_MASK) >> SPI_CS_TXBCNT_LSB)
180 #define SPI_CS_TXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_TXBCNT_LSB) & SPI_CS_TXBCNT_MASK)
182 /* 7:4 - Receive byte count, values of 1-8 are valid */
183 #define SPI_CS_RXBCNT_MSB 7
184 #define SPI_CS_RXBCNT_LSB 4
185 #define SPI_CS_RXBCNT_MASK 0x000000f0
186 #define SPI_CS_RXBCNT_GET(x) (((x) & SPI_CS_RXBCNT_MASK) >> SPI_CS_RXBCNT_LSB)
187 #define SPI_CS_RXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_RXBCNT_LSB) & SPI_CS_RXBCNT_MASK)
189 /* 8 - SPI transaction start */
190 #define SPI_CS_XCNSTART_MSB 8
191 #define SPI_CS_XCNSTART_LSB 8
192 #define SPI_CS_XCNSTART_MASK 0x00000100
193 #define SPI_CS_XCNSTART_GET(x) 0x0
194 #define SPI_CS_XCNSTART_SET(x) (((0x0 | (x)) << SPI_CS_XCNSTART_LSB) & SPI_CS_XCNSTART_MASK)
195 #define SPI_CS_XCNSTART_RESET 0x0
197 /* 9 - SPI chip select */
198 #define SPI_CS_CS_MSB 9
199 #define SPI_CS_CS_LSB 9
200 #define SPI_CS_CS_MASK 0x00000200
201 #define SPI_CS_CS_GET(x) (((x) & SPI_CS_CS_MASK) >> SPI_CS_CS_LSB)
202 #define SPI_CS_CS_SET(x) (((0x0 | (x)) << SPI_CS_CS_LSB) & SPI_CS_CS_MASK)
203 #define SPI_CS_CS_RESET 0x0
205 /* 16 - Transaction busy indication */
206 #define SPI_CS_BUSY_MSB 16
207 #define SPI_CS_BUSY_LSB 16
208 #define SPI_CS_BUSY_MASK 0x00010000
209 #define SPI_CS_BUSY_GET(x) (((x) & SPI_CS_BUSY_MASK) >> SPI_CS_BUSY_LSB)
210 #define SPI_CS_BUSY_SET(x) (((0x0 | (x)) << SPI_CS_BUSY_LSB) & SPI_CS_BUSY_MASK)
211 #define SPI_CS_BUSY_RESET 0x0
213 /* 18:17 - Automatically-determined SPI address size */
214 #define SPI_CS_AUTOSIZ_MSB 18
215 #define SPI_CS_AUTOSIZ_LSB 17
216 #define SPI_CS_AUTOSIZ_MASK 0x00060000
217 #define SPI_CS_AUTOSIZ_GET(x) (((x) & SPI_CS_AUTOSIZ_MASK) >> SPI_CS_AUTOSIZ_LSB)
218 #define SPI_CS_AUTOSIZ_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_LSB) & SPI_CS_AUTOSIZ_MASK)
220 /* 20:19 - SPI autosize override */
221 #define SPI_CS_AUTOSIZ_OVR_MSB 20
222 #define SPI_CS_AUTOSIZ_OVR_LSB 19
223 #define SPI_CS_AUTOSIZ_OVR_MASK 0x00180000
224 #define SPI_CS_AUTOSIZ_OVR_GET(x) (((x) & SPI_CS_AUTOSIZ_OVR_MASK) >> SPI_CS_AUTOSIZ_OVR_LSB)
225 #define SPI_CS_AUTOSIZ_OVR_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_OVR_LSB) & SPI_CS_AUTOSIZ_OVR_MASK)
226 #define SPI_CS_AUTOSIZ_OVR_RESET 0x0
228 #define SPI_CS_RESET (0x0 | \
229 SPI_CS_AUTOSIZ_OVR_SET(SPI_CS_AUTOSIZ_OVR_RESET) | \
230 SPI_CS_BUSY_SET(SPI_CS_BUSY_RESET) | \
231 SPI_CS_CS_SET(SPI_CS_CS_RESET) | \
232 SPI_CS_XCNSTART_SET(SPI_CS_XCNSTART_RESET))
235 * SPI address/opcode register (SPI_AO)
237 * Cold reset: (See field descriptions)
238 * Warm reset: (Same as cold reset)
241 * 7:0 - SPI opcode. Usually this field specifies the 8-bit opcode
242 * (aka "instruction") to transmit to the SPI device as the first
243 * part of an SPI transaction. See the 'Notes' section below for
244 * more details. Resets to an undefined value.
245 * 31:8 - Address. Usually this field specifies the 24-bit address to
246 * transmit to the SPI device. See the 'Notes' section below for
247 * more details. Resets to an undefined value.
250 #define SPI_AO_ADDRESS MAGPIE_REG_SPI_AO_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000004)
251 /* 7:0 - SPI opcode */
252 #define SPI_AO_OPC_MSB 7
253 #define SPI_AO_OPC_LSB 0
254 #define SPI_AO_OPC_MASK 0x000000ff
255 #define SPI_AO_OPC_GET(x) (((x) & SPI_AO_OPC_MASK) >> SPI_AO_OPC_LSB)
256 #define SPI_AO_OPC_SET(x) (((0x0 | (x)) << SPI_AO_OPC_LSB) & SPI_AO_OPC_MASK)
258 #define SPI_AO_ADDR_MSB 31
259 #define SPI_AO_ADDR_LSB 8
260 #define SPI_AO_ADDR_MASK 0xffffff00
261 #define SPI_AO_ADDR_GET(x) (((x) & SPI_AO_ADDR_MASK) >> SPI_AO_ADDR_LSB)
262 #define SPI_AO_ADDR_SET(x) (((0x0 | (x)) << SPI_AO_ADDR_LSB)& SPI_AO_ADDR_MASK)
265 * SPI data register (SPI_D)
267 * Cold reset: (See field descriptions)
268 * Warm reset: (Same as cold reset)
271 * 31:0 - SPI data. Usually this register specifies a series of up to
272 * four data bytes to transmit to or receive from the SPI device.
273 * See the 'Notes' section below for more details. Resets to an
277 #define SPI_D_ADDRESS MAGPIE_REG_SPI_D_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000008)
278 /* 31:0 - SPI data */
279 #define SPI_D_DATA_MSB 31
280 #define SPI_D_DATA_LSB 0
281 #define SPI_D_DATA_MASK 0xffffffff
282 #define SPI_D_DATA_GET(x) (((x) & SPI_D_DATA_MASK) >> SPI_D_DATA_LSB)
283 #define SPI_D_DATA_SET(x) (((0x0 | (x)) << SPI_D_DATA_LSB) & SPI_D_DATA_MASK)
286 * SPI clock division register (SPI_CLKDIV)
288 * Cold reset: (See field descriptions)
289 * Warm reset: (Same as cold reset)
292 * 17:16 - 0b00(fastest), 0b01, 0b10, 0b11(slowest)
294 #define SPI_CLKDIV_ADDRESS MAGPIE_REG_SPI_CLKDIV_ADDR //SPI_BASE_ADDRESS + 0x0000001c
295 #define SPI_CLKDIV_MSB 17
296 #define SPI_CLKDIV_LSB 16
297 #define SPI_CLKDIV_MASK 0x00030000
298 #define SPI_CLKDIV_GET(x) (((x) & SPI_CLKDIV_MASK) >> SPI_CLKDIV_LSB)
299 #define SPI_CLKDIV_SET(x) (((0x0 | (x)) << SPI_CLKDIV_LSB) & SPI_CLKDIV_MASK) // read-then-write
300 #define SPI_CLKDIV_RESET 0x3
306 * An SPI transaction consists of three phases: an opcode transmit
307 * phase (always a single byte), followed by an optional address
308 * transmit phase of 0-3 bytes, followed by an optional data transmit
309 * or receive phase of 0-4 bytes.
311 * Combined, then, an SPI transaction consists of a 1- to 8-byte
312 * transmit phase from Falcon to the SPI device, followed by a 0- to
313 * 8-byte receive phase from the SPI device into Falcon.
315 * The 'transmit byte count' field in the SPI_CS register controls the
316 * size (number of bytes) of the transmit phase. The source of each
317 * of the bytes transmitted is fixed:
320 * ---- -----------------------------------------------------------
321 * 0 SPI_AO[7:0] (the 'SPI opcode' field)
322 * 1 SPI_AO[31:24] (the high byte of the 'SPI address' field)
323 * 2 SPI_AO[23:16] (the middle byte of the 'SPI address' field)
324 * 3 SPI_AO[15:8] (the low byte of the 'SPI address' field)
325 * 4 SPI_D[7:0] (the low byte of the 'SPI data' register)
326 * 5 SPI_D[15:8] (the next byte of the 'SPI data' register)
327 * 6 SPI_D[23:16] (the next byte of the 'SPI data' register)
328 * 7 SPI_D[31:24] (the high byte of the 'SPI data' register)
331 * The 'receive byte count' field in the SPI_CS register controls the
332 * size (number of bytes) of the receive phase. The destination of
333 * each of the bytes received is fixed:
336 * ---- -----------------------------------------------------------
337 * 0 SPI_D[7:0] (the low byte of the 'SPI data' register)
338 * 1 SPI_D[15:8] (the next byte of the 'SPI data' register)
339 * 2 SPI_D[23:16] (the next byte of the 'SPI data' register)
340 * 3 SPI_D[31:24] (the high byte of the 'SPI data' register)
341 * 4 SPI_AO[7:0] (the 'SPI opcode' field)
342 * 5 SPI_AO[15:8] (the low byte of the 'SPI address' field)
343 * 6 SPI_AO[23:16] (the middle byte of the 'SPI address' field)
344 * 7 SPI_AO[31:24] (the high byte of the 'SPI address' field)
347 * * To perform an SPI transaction:
348 * Write the appropriate values into the SPI_AO and SPI_D registers
349 * * Write the appropriate values into the 'transmit byte count' and
350 * 'received byte count' fields of the SPI_CS register.
351 * * Write a '1' to the 'SPI transaction start' bit of the SPI_CS
352 * register (this step can be combined with the one above if desired
353 * so that only a single SPI_CS write is needed).
354 * * Poll the 'transaction busy indication' bit in the SPI_CS register
355 * until it is clear, indicating that the SPI transaction has
357 * * If the transaction included a receive phase, then retrieve the
358 * received data by reading the appropriate bytes from the SPI_D and
363 * * A "write disable" (WRDI) transaction:
364 * * Opcode (SPI_AO[7:0]): 0x04 (for STMicro; varies by
365 * manufacturer and device type)
366 * * Address (SPI_AO[31:8]): don't care (not used)
367 * * Data (SPI_D[31:0]): don't care (not used)
368 * * Transmission byte count: 1
369 * * Receive byte count: 0
371 * * A "read status register" (RDSR) transaction:
372 * * Opcode (SPI_AO[7:0]): 0x05 (for STMicro; varies by
373 * manufacturer and device type)
374 * * Address (SPI_AO[31:8]): don't care (not used)
375 * * Data (SPI_D[31:0]): don't care (not used)
376 * * Transmission byte count: 1
377 * * Receive byte count: 1
378 * * Read SPI_D[7:0] to retrieve status register value
380 * * A "page program" (PP) transaction to write a value of 0xdeadbeef
381 * to address 0x123456:
382 * * Opcode (SPI_AO[7:0]): 0x02 (for STMicro; varies by
383 * manufacturer and device type)
384 * * Address (SPI_AO[31:8]): 0x123456
385 * * Data (SPI_D[31:0]): 0xdeadbeef
386 * * Transmission byte count: 8
387 * * Receive byte count: 0
390 /* Wait till Transaction busy indication bit in SPI control/status register of Falcon's SPI Flash Controller is clear */
392 _cmnos_sflash_WaitTillTransactionOver(void)
399 poldata = HAL_WORD_REG_READ(SPI_CS_ADDRESS);
401 flg = SPI_CS_BUSY_GET(poldata);
402 } while (flg != 0x0);
405 /* Wait till Write In Progress bit in Status Register of Serial Flash is clear */
407 _cmnos_sflash_WaitTillNotWriteInProcess(void)
414 _cmnos_sflash_WaitTillTransactionOver();
416 HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) );
417 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) );
419 _cmnos_sflash_WaitTillTransactionOver();
421 poldata = HAL_WORD_REG_READ(SPI_D_ADDRESS);
422 flg = poldata & ZM_SFLASH_STATUS_REG_WIP;
424 } while (flg != 0x0);
427 /************************************************************************/
428 /* Function to Send WREN(Write Enable) Operation */
429 /************************************************************************/
431 _cmnos_sflash_WriteEnable()
433 _cmnos_sflash_WaitTillNotWriteInProcess();
435 HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN) );
436 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
438 _cmnos_sflash_WaitTillTransactionOver();
441 /************************************************************************/
442 /* Function to In itialize SPI Flash Controller */
443 /************************************************************************/
445 cmnos_sflash_init(void)
447 #if defined(PROJECT_K2)
448 /* Switch the function of I/O pin 19~22 to act as SPI pins */
449 HAL_WORD_REG_WRITE( MAGPIE_REG_CLOCK_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_CLOCK_CTRL_ADDR)|BIT8 );
452 /* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail :
453 * The designers reached an conclusion that the spi master (the apb_spi interface control) will be
454 * modified as ¡§presuming the attached flash model to be 24-bit addressing¡¨, i.e., no more
455 * auto-size detection!
456 * Hence you are free to force the 24-bit addressing in the *.c test code.
459 /* Force SPI address size to 24 bits */
460 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2) );
463 /************************************************************************/
464 /* Function to Send Sector/Block/Chip Erase Operation */
465 /************************************************************************/
467 cmnos_sflash_erase(A_UINT32 erase_type, A_UINT32 addr)
469 A_UINT32 erase_opcode;
472 if (erase_type == ZM_SFLASH_SECTOR_ERASE)
474 erase_opcode = ZM_SFLASH_OP_SE;
477 else if (erase_type == ZM_SFLASH_BLOCK_ERASE)
479 erase_opcode = ZM_SFLASH_OP_BE;
484 erase_opcode = ZM_SFLASH_OP_CE;
488 _cmnos_sflash_WriteEnable();
489 _cmnos_sflash_WaitTillNotWriteInProcess();
491 HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr) );
492 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
495 /* Do not wait(let it be completed in background) */
496 _cmnos_sflash_WaitTillTransactionOver();
498 /* Wait till completion */
499 _cmnos_sflash_WaitTillNotWriteInProcess(); /* Chip Erase takes 80 - 200 seconds to complete */
503 /************************************************************************/
504 /* Function to Perform Page Program Operation */
506 /* Serial Flash has the following characteristics : */
507 /* 1) In datasheet, 1-256 data bytes can be sent at a time, but */
508 /* Falcon supports only 4 bytes at a time. */
509 /* 2) If the eight least significant address bits(A7-A0) are not */
510 /* all 0, all transmitted data which goes beyond the end of the */
511 /* current page are programmed from the start address in the */
513 /* This API hides the complexity of the above. */
514 /************************************************************************/
516 cmnos_sflash_program(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf)
518 A_UINT32 s_addr, e_addr;
519 A_UINT32 reminder, write_byte;
520 A_UINT32 data_offset;
521 A_UINT32 next_page_base;
522 A_UINT32 t_word_data;
525 for (s_addr = addr; s_addr < e_addr; )
527 next_page_base = (s_addr - s_addr%ZM_SFLASH_PAGE_SIZE) + ZM_SFLASH_PAGE_SIZE;
529 reminder = e_addr - s_addr;
531 write_byte = next_page_base - s_addr;
536 if (write_byte > reminder)
537 write_byte = reminder;
539 data_offset = s_addr - addr;
541 A_MEMCPY(&t_word_data, buf + data_offset, write_byte);
543 _cmnos_sflash_WriteEnable();
544 _cmnos_sflash_WaitTillNotWriteInProcess();
546 HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr) );
547 HAL_WORD_REG_WRITE( SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data) );
548 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
550 _cmnos_sflash_WaitTillTransactionOver();
552 s_addr += write_byte;
556 /************************************************************************/
557 /* Function to Send Read/Fast Read Data Operation */
558 /************************************************************************/
560 cmnos_sflash_read(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf)
562 A_UINT32 read_opcode;
564 A_UINT32 read_cnt, remainder;
565 A_UINT32 write_byte, read_byte;
569 read_opcode = ZM_SFLASH_OP_FAST_READ;
574 read_opcode = ZM_SFLASH_OP_READ;
584 for (i = 0; i < read_cnt; i ++)
586 if (i == read_cnt-1 && remainder)
587 read_byte = remainder;
589 _cmnos_sflash_WaitTillNotWriteInProcess();
591 HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4) );
592 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1) );
594 _cmnos_sflash_WaitTillTransactionOver();
596 A_MEMCPY(buf + i*4, (A_UINT8 *)(SPI_D_ADDRESS), read_byte);
600 /************************************************************************/
601 /* Function to Read Flash Status Register */
602 /************************************************************************/
604 cmnos_sflash_rdsr(void)
608 _cmnos_sflash_WaitTillTransactionOver();
610 HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) );
611 HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) );
613 _cmnos_sflash_WaitTillTransactionOver();
615 word_data = HAL_WORD_REG_READ(SPI_D_ADDRESS) & 0x000000FF;
621 cmnos_sflash_module_install(struct sflash_api *tbl)
623 /* Indispensable functions */
624 tbl->_sflash_init = cmnos_sflash_init;
625 tbl->_sflash_erase = cmnos_sflash_erase;
626 tbl->_sflash_program = cmnos_sflash_program;
627 tbl->_sflash_read = cmnos_sflash_read;
629 /* Dispensable functions */
630 tbl->_sflash_rdsr = cmnos_sflash_rdsr;
633 #endif /* SYSTEM_MODULE_SFLASH */