5 * Interrupt handler, for application-managed interrupts.
6 * When an interrupt occurs, it is automatically disabled.
7 * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH().
9 * If a handler returns A_HANDLER_DONE, the interrupt is
10 * re-enabled. The OS calls the handler next time service
11 * is required. This is the normal case for a handler.
13 * If a handler returns A_HANDLER_YIELD, the interrupt
14 * remains masked. The handler is called again when
15 * it is "convenient". This gives the OS an opportunity
16 * to run other code/handlers. A handler should return
17 * A_HANDLER_YIELD if it might dominate the CPU for too
20 * If a handler returns A_HANDLER_NOENABLE, the interrupt
21 * remains disabled. It is up to the application to re-enable
22 * the interrupt (via A_*_INTR_UNMASK) when it's appropriate.
24 * Note that many combinations of interrupt functions and
25 * interrupt vectors are NOT supported: Callers should use
26 * only the macros defined in cmnos_api.h to access the
29 #include "cmnos_api.h"
31 typedef uint32_t A_old_intr_t;
33 //////////////////////////////////////////////////////////////////
34 // this is copied from mercury/cmnos_xtensa.h
36 * These are CMNOS interrupt manifest constants.
37 * They have specially-chosen values that align with hardware and or
38 * operating system values (see cmnos_interrupt_info).
40 #if defined(__XTENSA__)
42 * Enumeration of low and medium priority interrupt numbers
43 * which match the CPU hardware configuration:
46 /* XTensa Level 1 interrupt */
47 #define A_INUM_SOFTWARE 0 /* currently unused */
49 /* XTensa Level2 interrupts */
50 #define A_INUM_XTTIMER 1 /* currently unused */
52 #define A_INUM_TBD_0 2 /* TBD */
53 #define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */
54 #define A_INUM_GMAC_DMA 4 /* GMAC DMA interrupt */
55 #define A_INUM_GMAC_MDIO 5 /* GMAC MDIO interrupt */
56 #define A_INUM_HOST_DMA 6 /* HOST DMA */
57 #define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */
58 #define A_INUM_TBD_8 8 /* TBD */
59 #define A_INUM_TBD_9 9 /* TBD */
60 #define A_INUM_USB_CTRL 10 /* USB core control */
61 #define A_INUM_USB_DMA 11 /* USB DMA */
62 #define A_INUM_TBD_12 12 /* TBD */
63 #define A_INUM_TBD_13 13 /* TBD */
64 #define A_INUM_EMUX_CPU 14 /* EMUX CPU */
65 #define A_INUM_GPIO_CPU 15 /* GPIO CPU interrupt */
66 #define A_INUM_TBD_16 16 /* TBD */
67 #define A_INUM_PCIE_CPU 17 /* CPU PCIE interrupt */
68 #define A_INUM_RST_CPU_NMI 18 /* RST CPU nmi interrupt */
70 /* Number of interrupts that map directly into CPU/hal interrupt bits. */
71 #define NUM_DIRECT_INTR 19
74 //////////////////////////////////////////////////////////////////
76 #define CMNOS_IMASK_XTTIMER (1<<A_INUM_XTTIMER)
77 #define CMNOS_IMASK_USB_CTRL (1<<A_INUM_USB_CTRL)
78 #define CMNOS_IMASK_GMAC_DMA (1<<A_INUM_GMAC_DMA)
79 #define CMNOS_IMASK_GMAC_MDIO (1<<A_INUM_GMAC_MDIO)
80 #define CMNOS_IMASK_HOST_DMA (1<<A_INUM_HOST_DMA)
81 #define CMNOS_IMASK_CPU_GEN_TIMER (1<<A_INUM_CPU_GEN_TIMER)
83 #define CMNOS_IMASK_EMUX_CPU (1<<A_INUM_EMUX_CPU)
84 #define CMNOS_IMASK_GPIO_CPU (1<<A_INUM_GPIO_CPU)
85 #define CMNOS_IMASK_PCIE_CPU (1<<A_INUM_PCIE_CPU)
86 #define CMNOS_IMASK_RST_CPU_NMI (1<<A_INUM_RST_CPU_NMI)
90 typedef enum inum_intr {
95 /* add intr above here */
99 //////////////////////////////////////////////////////////////////
102 * An interrupt handler, which is a function called in response
103 * to a hardware interrupt, possibly as a Delayed Service Routine.
105 typedef int (* A_handler_t)(void *);
106 /* Return values from a handler/DSR, A_handler_t */
107 #define A_HANDLER_NOENABLE 0 /* do not re-enable interrupts */
108 #define A_HANDLER_DONE 1 /* all intrs handled, call on next intr */
109 #define A_HANDLER_YIELD 2 /* leave intrs disabled and
110 call back later regardless of intr state */
113 * An Interrupt Service Routine, which must be called
114 * directly in interrupt context (not delayed), and which
115 * must be very small and may not have access to all OS
116 * functions. These are for use only when interrupt
117 * latency is critical; otherwise, an A_handler_t ("dsr")
120 typedef uint32_t (* A_isr_t)(void *);
121 /* Return values from an ISR */
122 #if defined(CYG_ISR_HANDLED)
123 #define A_ISR_HANDLED CYG_ISR_HANDLED
124 #define A_ISR_CALL_DSR CYG_ISR_CALL_DSR
126 #define A_ISR_HANDLED 1
127 #define A_ISR_CALL_DSR 2
131 void (*_intr_init)(void);
132 uint32_t (* _intr_invoke_isr)(uint32_t inum);
133 A_old_intr_t(* _intr_disable)(void);
134 void (* _intr_restore)(A_old_intr_t);
136 void (* _intr_mask_inum)(uint32_t inum);
137 void (* _intr_unmask_inum)(uint32_t inum);
138 void (* _intr_attach_isr)(uint32_t inum, A_isr_t isr, void *arg);
140 BOOLEAN (*_intr_dsrs_pending)(void);
141 void (* _intr_handle_pending_dsrs)(void);
142 uint32_t (* _intr_nmi)(void *);
144 /* Low-level interrupt access, intended for use by OS modules */
145 unsigned int (* _get_intrenable)(void);
146 void (* _set_intrenable)(unsigned int);
147 unsigned int (* _get_intrpending)(void);
148 void (* _unblock_all_intrlvl)(void);
150 #endif /* __INTR_API_H__ */