2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
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17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Copyright (c) 2000-2008 Atheros Communications, Inc., All Rights Reserved
38 * $Id: //depot/sw/branches/fusion_usb/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/athos_main.c#1 $
40 * This file contains type definitions
45 #include "athos_api.h"
50 /* dhry mips stone test */
54 //#include "usb_defs.h"
55 //#include "usb_type.h"
58 #include "xtensa/corebits.h"
59 #include "xtensa/tie/xt_core.h"
67 BOOLEAN download_enable = FALSE;
69 /* #define ALLOCRAM_START 0x512800 */
70 /* #define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE) */
72 #define ALLOCRAM_START SYS_D_RAM_REGION_3_BASE
73 #define ALLOCRAM_SIZE SYS_RAM_BLOCK_SIZE
75 extern unsigned int _text_start_in_rom;
76 extern unsigned int _text_start;
77 extern unsigned int _text_end;
79 extern unsigned int _rodata_start_in_rom;
80 extern unsigned int _lit4_start;
81 extern unsigned int _lit4_end;
84 * This special table is used by Xtensa startup code to copy
85 * ROM-based data into RAM. See Xtensa documentation or
86 * "unpack" code in ResetVector.S for details.
88 const uint32_t _rom_store_table[] = {
89 (uint32_t)&_data_start, (uint32_t)&_data_end, (uint32_t)&_data_start_in_rom,
90 (uint32_t)&_text_start, (uint32_t)&_text_end, (uint32_t)0xf002000,
91 (uint32_t)&_lit4_start, (uint32_t)&_lit4_end, (uint32_t)0xf008000,
92 (uint32_t)0x00500400, (uint32_t)0x00500940, (uint32_t)0x004e0260,
97 #define ATH_DATE_STRING __DATE__" "__TIME__
101 * 03/09: it'll always fall into this exception if we enable this exception handler, need to do more testing, Ryan
104 Magpie_fatal_exception_handler(CPU_exception_frame_t *exc_frame)
106 struct register_dump_s dump;
108 dump.exc_frame = *exc_frame; /* structure copy */
109 dump.badvaddr = XT_RSR_EXCVADDR();
110 dump.exc_frame.xt_exccause = XT_RSR_EXCCAUSE();
111 dump.pc = exc_frame->xt_pc;
114 A_PRINTF("Fatal exception (%d): pc=0x%x badvaddr=0x%x dump area=0x%x\n",
115 dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump);
116 // PRINT_FAILURE_STATE();
118 // A_ASSFAIL(&dump); // misc module
122 //void app_start(void);
125 athos_linkage_check(int sz, struct _A_os_linkage_check *link_check)
127 if (sz != sizeof(struct _A_os_linkage_check)) {
131 if (link_check->version != OS_LINKAGE_VERSION) {
135 if (link_check->table != sizeof(struct _A_magpie_indirection_table) &&
136 (link_check->table != 0)) {
140 return 1; /* successful linkage check */
143 // A_PRINTF("athos_linkage_check failure!\n");
149 #ifdef SYSTEM_MODULE_INTR
151 /* Mask of Interrupt Level bits in Xtensa's Processor Status register */
152 #define XTENSA_PS_INTLEVEL_MASK 0xf
155 athos_block_all_intrlvl(void)
160 * This function doesn't actually block ALL interrupts;
161 * it leaves ERROR & WDT interrupts -- which are fatal
162 * and are at level 3 -- active.
164 asm volatile("rsil %0,2" : "=r" (tmp));
166 return (uint32_t)((A_UINT32)tmp & XTENSA_PS_INTLEVEL_MASK);
170 athos_unblock_all_intrlvl(void)
174 asm volatile("rsil %0, 0" : "=r" (tmp));
178 athos_restore_intrlvl(uint32_t old_intr)
181 athos_unblock_all_intrlvl();
188 AR6002_misaligned_load_handler(CPU_exception_frame_t *exc_frame)
190 struct register_dump_s dump;
193 #if SYSTEM_MODULE_PRINT
194 A_PRINTF("misaligned_load\n\r");
196 A_PUTS("misaligned_load\n\r");
199 dump.exc_frame = *exc_frame; /* structure copy */
200 dump.badvaddr = XT_RSR_EXCVADDR();
201 dump.pc = exc_frame->xt_pc;
203 asm volatile("mov %0,a1" : "=r" (stkptr));
205 /* Stores a0,a1,a2,a3 on stack; but leaves sp unchanged */
206 xthal_window_spill();
211 #define MAGPIE_REGDUMP_FRAMES 5
213 /* Walk back the stack */
214 for (i=0; i<MAGPIE_REGDUMP_FRAMES; i++) {
215 dump.exc_frame.wb[i].a0 = stkptr[-4];
216 dump.exc_frame.wb[i].a1 = stkptr[-3];
217 dump.exc_frame.wb[i].a2 = stkptr[-2];
218 dump.exc_frame.wb[i].a3 = stkptr[-1];
219 if (dump.exc_frame.wb[i].a0 == 0) {
222 stkptr = (uint32_t *)dump.exc_frame.wb[i].a1;
226 A_MISALIGNED_LOAD_HANDLER(&dump);
231 AR6002_fatal_exception_handler(CPU_exception_frame_t *exc_frame)
233 struct register_dump_s dump;
235 dump.exc_frame = *exc_frame; /* structure copy */
236 dump.badvaddr = XT_RSR_EXCVADDR();
237 dump.exc_frame.xt_exccause = XT_RSR_EXCCAUSE();
238 dump.pc = exc_frame->xt_pc;
241 #if SYSTEM_MODULE_PRINT
242 A_PRINTF("Fatal exception (%d): \tpc=0x%x \n\r\tbadvaddr=0x%x \n\r\tdump area=0x%x\n",
243 dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump);
244 PRINT_FAILURE_STATE();
246 A_PUTS("Fatal exception\n\r");
251 // trigger wdt, in case hang
253 //HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, 0x03);
254 //HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_ADDR, 0x10);
263 typedef void (*INSTFN)(void *);
266 * These are all modules that reside in ROM which are installed
267 * by default by the operating system. Other ROM modules may
268 * be installed by the application if they are needed.
271 void (* install_fn)(void *);
273 } basic_ROM_module_table[] =
276 #if SYSTEM_MODULE_MEM
277 {(INSTFN)cmnos_mem_module_install, (void *)&A_CMN(mem)},
280 #if SYSTEM_MODULE_MISC
281 {(INSTFN)cmnos_misc_module_install, (void *)&A_CMN(misc)},
284 #if SYSTEM_MODULE_PRINT
285 {(INSTFN)cmnos_printf_module_install, (void *)&A_CMN(printf)},
288 #if SYSTEM_MODULE_UART
289 {(INSTFN)cmnos_uart_module_install, (void *)&A_CMN(uart)},
292 #if SYSTEM_MODULE_USB
293 {(INSTFN)cmnos_usb_module_install, (void *)&A_CMN(usb)},
296 #if SYSTEM_MODULE_INTR
297 {(INSTFN)cmnos_intr_module_install, (void *)&A_CMN(intr)},
300 #if SYSTEM_MODULE_TIMER
301 {(INSTFN)cmnos_timer_module_install, (void *)&A_CMN(timer)},
304 #if SYSTEM_MODULE_CLOCK
305 {(INSTFN)cmnos_clock_module_install, (void *)&A_CMN(clock)},
308 #if SYSTEM_MODULE_ALLOCRAM
309 {(INSTFN)cmnos_allocram_module_install, (void *)&A_CMN(allocram)},
312 #if SYSTEM_MODULE_ROM_PATCH
313 {(INSTFN)cmnos_romp_module_install, (void *)&A_CMN(romp)},
316 #if SYSTEM_MODULE_WDT
317 {(INSTFN)cmnos_wdt_module_install, (void *)&A_CMN(wdt_timer)},
320 #if SYSTEM_MODULE_EEPROM
321 {(INSTFN)cmnos_eep_module_install, (void *)&A_CMN(eep)},
323 {(INSTFN)cmnos_string_module_install, (void *)&A_CMN(string)},
324 {(INSTFN)cmnos_tasklet_module_install, (void *)&A_CMN(tasklet)},
325 {(INSTFN)vdesc_module_install, (void *)&A_INDIR(vdesc)},
326 {(INSTFN)vbuf_module_install, (void *)&A_INDIR(vbuf)},
327 {(INSTFN)generic_hif_module_install, (void *)&A_INDIR(hif)},
328 {(INSTFN)buf_pool_module_install, (void *)&A_INDIR(buf_pool)},
329 {(INSTFN)usbfifo_module_install, (void *)&A_INDIR(usbfifo_api)},
330 {(INSTFN)dma_engine_module_install, (void *)&A_INDIR(dma_engine)},
331 {(INSTFN)dma_lib_module_install, (void *)&A_INDIR(dma_lib)},
334 #define BASIC_ROM_MODULE_TABLE_SZ (sizeof(basic_ROM_module_table)/sizeof(basic_ROM_module_table[0]))
337 generic_hif_module_install(struct hif_api *apis)
341 hostif = A_IS_HOST_PRESENT();
345 hif_usb_module_install(apis);
351 athos_indirection_table_install(void)
355 /* Sanity: start with a clear table */
357 //char *tbl = (char *)_A_OS_INDIRECTION_TABLE;
358 char *tbl = (char *)_A_MAGPIE_INDIRECTION_TABLE;
360 //for (i=0; i<_A_OS_INDIRECTION_TABLE_SIZE; i++) {
361 for (i=0; i<_A_MAGPIE_INDIRECTION_TABLE_SIZE; i++) {
366 /* Install basic ROM modules */
367 for (i=0; i<BASIC_ROM_MODULE_TABLE_SZ; i++) {
368 basic_ROM_module_table[i].install_fn(basic_ROM_module_table[i].api_tbl);
372 DBG_MODULE_INSTALL(); // move DBG to indirection table
375 //_A_OS_INDIRECTION_TABLE->cmnos.app_start = app_start;
376 //_A_OS_INDIRECTION_TABLE->cmnos.hal_linkage_check = athos_linkage_check;
377 //_A_MAGPIE_INDIRECTION_TABLE->cmnos.app_start = app_start;
378 _A_MAGPIE_INDIRECTION_TABLE->cmnos.hal_linkage_check = athos_linkage_check;
380 // _A_OS_INDIRECTION_TABLE->cmnos.start_bss = &START_BSS;
382 #if SYSTEM_MODULE_INTR
383 /* Install a few CPU-specific functions */
384 _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._get_intrenable = xthal_get_intenable;
385 _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._set_intrenable = xthal_set_intenable;
386 _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._get_intrpending = xthal_get_interrupt;
387 _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._unblock_all_intrlvl = athos_unblock_all_intrlvl;
388 _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._intr_disable = athos_block_all_intrlvl;
389 _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._intr_restore = athos_restore_intrlvl;
392 /* UNALIGNED references are used for ASSERTs */
393 (void)_xtos_set_exception_handler(EXCCAUSE_UNALIGNED, AR6002_misaligned_load_handler);
394 (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, AR6002_fatal_exception_handler);
395 (void)_xtos_set_exception_handler(EXCCAUSE_ILLEGAL, AR6002_fatal_exception_handler);
396 (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_ERROR, AR6002_fatal_exception_handler);
397 (void)_xtos_set_exception_handler(EXCCAUSE_PRIVILEGED, AR6002_fatal_exception_handler);
398 (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_DATA_ERROR, AR6002_fatal_exception_handler);
399 (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, AR6002_fatal_exception_handler);
400 (void)_xtos_set_exception_handler(EXCCAUSE_DIVIDE_BY_ZERO, AR6002_fatal_exception_handler);
404 #ifdef SYSTEM_MODULE_INTR
406 * All interrupts pass through here. Yes, it adds a
407 * bit of overhead; but it may be very helpful with
408 * debugging, ROM patching, and workarounds.
410 * NB: Assembler code that calls this loops through all
411 * pending & enabled interrupts.
414 athos_interrupt_handler(unsigned int inum, unsigned int *interrupt_frame)
421 athos_interrupt_init(void)
423 #ifdef SYSTEM_MODULE_INTR
425 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x20;
427 for (i=0; i<NUM_DIRECT_INTR; i++) {
428 (void)_xtos_set_interrupt_handler(i, athos_interrupt_handler);
431 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x21;
433 // A_MC_REG_WRITE(ADDR_ERROR_CONTROL_ADDRESS, ADDR_ERROR_CONTROL_ENABLE_MASK);
435 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x22;
436 athos_unblock_all_intrlvl();
442 void athos_init(A_HOSTIF hif)
445 ///////////////////////////////////////////////////////
446 //init each module, should be put together..
447 A_CLOCK_INIT(SYSTEM_CLK);
455 void led_on(unsigned int bit)
457 *(unsigned long *)0x5200c = 1<<bit;
460 void led_off(unsigned int bit)
462 *(unsigned long *)0x52010 = 1<<bit;
480 #define LED_ON_OFF_FREQ 500
486 if(i==LED_ON_OFF_FREQ*1)
488 else if (i==LED_ON_OFF_FREQ*2)
490 else if (i==LED_ON_OFF_FREQ*3)
492 else if (i==LED_ON_OFF_FREQ*4)
494 else if (i==LED_ON_OFF_FREQ*5)
496 else if (i==LED_ON_OFF_FREQ*6)
506 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0xe;
507 CURRENT_PROGRAM = (uint32_t)bootload;
508 A_PUTS("8. wait for read/read_comp.... \n\r");
511 /* update wdt timer */
514 /* high priority tasks */
520 if( download_enable )
527 change_magpie_clk(uint32_t cpu_freq, uint32_t ahb_div)
529 volatile uint32_t i = 0;
530 volatile uint32_t rd_data = 0, wd_data = 0;
532 /* Put the PLL into reset */
533 rd_data = HAL_WORD_REG_READ(0x00050010) | (1<<1);
534 HAL_WORD_REG_WRITE(0x00050010,rd_data);
536 HAL_WORD_REG_WRITE(0x00056004, 0x11);
537 rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
539 /* Wait for the update bit to get cleared */
541 rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
543 /* Setting of the PLL */
544 if (cpu_freq== 100) wd_data = 0x142; /* PLL 400 MHz*/
545 else if (cpu_freq== 105) wd_data = 0x152; /* PLL 420 MHz */
546 else if (cpu_freq== 110) wd_data = 0x162; /* PLL 440 MHz*/
547 else if (cpu_freq== 115) wd_data = 0x172; /* PLL 460 MHz */
548 else if (cpu_freq== 120) wd_data = 0x182; /* PLL 480 MHz */
549 else if (cpu_freq== 125) wd_data = 0x192; /* PLL 500 MHz */
550 else if (cpu_freq== 130) wd_data = 0x1a2; /* PLL 520 MHz */
551 else if (cpu_freq== 135) wd_data = 0x1b2; /* PLL 540 MHz */
552 else if (cpu_freq== 140) wd_data = 0x1c2; /* PLL 560 MHz */
553 else if (cpu_freq== 145) wd_data = 0x1d2; /* PLL 580 MHz */
554 else if (cpu_freq== 150) wd_data = 0x1e2; /* PLL 600 MHz */
555 else if (cpu_freq== 155) wd_data = 0x1f2; /* PLL 620 MHz */
556 else if (cpu_freq== 160) wd_data = 0x202; /* PLL 640 MHz */
557 else if (cpu_freq== 165) wd_data = 0x212; /* PLL 660 MHz */
558 else if (cpu_freq== 170) wd_data = 0x222; /* PLL 680 MHz */
559 else if (cpu_freq== 175) wd_data = 0x232; /* PLL 700 MHz */
560 else if (cpu_freq== 180) wd_data = 0x242; /* PLL 720 MHz */
561 else if (cpu_freq== 185) wd_data = 0x252; /* PLL 740 MHz */
562 else if (cpu_freq== 190) wd_data = 0x262; /* PLL 760 MHz */
563 else if (cpu_freq== 195) wd_data = 0x272; /* PLL 780 MHz */
564 else if (cpu_freq== 200) wd_data = 0x142; /* PLL 400 MHz */
565 else if (cpu_freq== 210) wd_data = 0x152; /* PLL 420 MHz */
566 else if (cpu_freq== 220) wd_data = 0x162; /* PLL 440 MHz */
567 else if (cpu_freq== 230) wd_data = 0x172; /* PLL 460 MHz */
568 else if (cpu_freq== 240) wd_data = 0x182; /* PLL 480 MHz */
569 else if (cpu_freq== 250) wd_data = 0x192; /* PLL 500 MHz */
570 else if (cpu_freq== 260) wd_data = 0x1a2; /* PLL 520 MHz */
571 else if (cpu_freq== 270) wd_data = 0x1b2; /* PLL 540 MHz */
572 else if (cpu_freq== 280) wd_data = 0x1c2; /* PLL 560 MHz */
573 else if (cpu_freq== 290) wd_data = 0x1d2; /* PLL 580 MHz */
574 else if (cpu_freq== 300) wd_data = 0x1e2; /* PLL 600 MHz */
575 else if (cpu_freq== 310) wd_data = 0x1f2; /* PLL 620 MHz */
576 else if (cpu_freq== 320) wd_data = 0x202; /* PLL 640 MHz */
577 else if (cpu_freq== 330) wd_data = 0x212; /* PLL 660 MHz */
578 else if (cpu_freq== 340) wd_data = 0x222; /* PLL 680 MHz */
579 else if (cpu_freq== 350) wd_data = 0x232; /* PLL 700 MHz */
580 else if (cpu_freq== 360) wd_data = 0x242; /* PLL 720 MHz */
581 else if (cpu_freq== 370) wd_data = 0x252; /* PLL 740 MHz */
582 else if (cpu_freq== 380) wd_data = 0x262; /* PLL 760 MHz */
583 else if (cpu_freq== 390) wd_data = 0x272; /* PLL 780 MHz */
584 else if (cpu_freq== 400) wd_data = 0x282; /* PLL 800 MHz */
585 else wd_data = 0x142; /* PLL 400 MHz*/
587 HAL_WORD_REG_WRITE(0x00056000, wd_data);
589 /* Pull CPU PLL out of Reset */
590 rd_data = HAL_WORD_REG_READ(0x00050010) & ~(1<<1);
591 HAL_WORD_REG_WRITE(0x00050010,rd_data);
593 /* CPU & AHB settings */
594 rd_data = HAL_WORD_REG_READ(0x00056004);
596 /* > 200 Mhz CPU clock (PLL / 2) or < 200 Mhz (PLL / 4) */
598 rd_data = (rd_data & ~(0xff<<16)) | (1<<16);
600 rd_data = (rd_data & ~(0xff<<16)) | (2<<16);
602 /* AHB Clock, AHB_FREQ = CPU_FREQ / ahb_div */
605 rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | 0x1;
608 rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | (1<<8) | 0x1;
611 rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | (2<<8) | 0x1;
614 rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | (1<<8) | 0x1;
618 HAL_WORD_REG_WRITE(0x00056004, rd_data);
619 rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
622 rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
628 A_UART_HWINIT((cpu_freq / ahb_div) * (1000*1000), 115200);
630 // A_PRINTF("reg_read(0x56000): %p \n", HAL_WORD_REG_READ(0x00056000));
631 // A_PRINTF("reg_read(0x56004): %p \n", HAL_WORD_REG_READ(0x00056004));
633 /* set the current reference clock */
634 // A_CLOCK_INIT(cpu_freq);
639 * rom1.0 fix: turn off rc if no patch/eeprom exist
643 extern BOOLEAN eep_state;
645 // clear the cmnos_eeprom init state
648 // reset the pcie_rc shift, pll and phy
649 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT10|BIT9|BIT8|BIT7)));
651 // reset ahb_arb of pcie_rc
652 HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
657 /* uint32_t reset_temp; */
659 T_BOOT_TYPE rst_status;
662 ///////////////////////////////////
663 athos_indirection_table_install();
665 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x1;
666 CURRENT_PROGRAM = (uint32_t)bootentry;
667 // athos module install
668 athos_init(hostif); // move all the athos indirection table init function to here
670 athos_interrupt_init(); // install all interrupt function to known state
672 A_WDT_DISABLE(); // make srue wdt is diable
674 rst_status = A_WDT_LASTBOOT();
676 // pump up flash clock to 12.5Mhz
677 HAL_WORD_REG_WRITE(0x5b01c, 0x401);
681 * 1. turn on CPU PLL, reg(0x560000), 0x305
682 * 2. pll reset reg(0x50010), 0x03
683 * 3. pll reset reg(0x50010), 0x01
685 * - after enabling CPU PLL, left the interface pll setting
686 * be done in each interface
688 * e.g usb_init we mdid
689 * 4. usb divide reg(0x56008), 0x0808
690 * 5. clear register reg(0x50010), bit0, bit3, bit4
691 * 6. set register reg(0x50010), bit0, bit3, bit4
692 * 7. clear register reg(0x50010), bit0, bit3, bit4
694 * - wait for 200ms for usb phy 30mhz stable -
696 * 8. usb clock up, proceed reset of things
699 /* reset_temp = HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR); */
700 /* A_PRINTF("reset temp is %x \n",reset_temp); */
701 /* HAL_WORD_REG_WRITE( MAGPIE_REG_RST_RESET_ADDR, 0); */
704 /*! move the whole cpu pll setup to host interface specific
705 * since when bootup, we have an external clock source
707 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x2;
709 hostif = A_IS_HOST_PRESENT();
712 * GPIO_FUNCTION(0x28) - config uart (sin, sout) pair,
714 * pci host interface will only have (GPIO1, GPIO0), other hif (usb, pcie, gmac)
715 * will use (GPIO5, GPIO4)
725 HAL_WORD_REG_WRITE( MAGPIE_REG_GPIO_FUNCTION, (HAL_WORD_REG_READ(MAGPIE_REG_GPIO_FUNCTION)&(~(BIT4|BIT5|BIT6|BIT7|BIT8))) );
726 HAL_WORD_REG_WRITE( MAGPIE_REG_GPIO_FUNCTION, (HAL_WORD_REG_READ(MAGPIE_REG_GPIO_FUNCTION)|(BIT8)) );
729 change_magpie_clk(200, 2);
731 // power on self test
732 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x5;
733 A_PUTS("\n - Boot from SFLASH - \n\r");
735 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x9;
738 * check the host interface type,
740 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x15;
741 hostif = A_IS_HOST_PRESENT();
743 retEEP = A_EEP_IS_EXIST();
747 if( hostif == HIF_USB )
749 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0xb;
751 if( retEEP == RET_SUCCESS)
754 /* read the usb descriptor information from rom to ram */
762 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0xd;
771 *(unsigned long *)0x52000 = 0x7ebff; // set bit10/bit12 output mode
772 *(unsigned long *)0x0053fff8 = 0x0;
774 // for debug purpose in case we don't know where we are
775 // keep this address update, so that we could trace the where is is
776 DEBUG_SYSTEM_STATE = 0x0;
780 A_PRINTF("FLASH_READ_COMP, jump to firmware\n");