8 #define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211
9 #define VERIFY_CHECKSUM_BY_BOOTCODE 1
11 /***********************************************************************/
12 /* for SEEPROM Boot */
13 /***********************************************************************/
14 #define WLAN_BOOT_SIGNATURE (0x19710303)
16 #define WLAN_SIGNATURE_ADDR (0x102000)
18 #define cMAX_ADDR 0x10000
20 #define cEEPROM_SIZE 0x800 // 2k word (4k byte)
22 #define cRESERVE_LOAD_SPACE 0
24 // start addr. of boot code
25 #define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800
27 /************************** Register Addr Process *********************/
28 #define mpADDR(addr) ((volatile uint16_t*) (addr))
29 #define mADDR(addr) (*mpADDR(addr))
30 #define muADDR(addr) ((uint16_t) (&(addr)))
32 #define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
33 #define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
34 //#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
36 #define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
37 #define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
39 #define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
40 #define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
43 /************************** Register Deinition ***************************/
44 //#define USB_BASE_ADDR_SOC 0x8000
46 //#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC)
48 #define cSOC_USB_OFST (0x100)
50 #define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0
52 #define cSOC_CBUS_CTL_OFFSET 0xF0
54 #define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS
56 #define ZM_MAIN_CTRL_OFFSET 0x00
57 #define ZM_DEVICE_ADDRESS_OFFSET 0x01
58 #define ZM_TEST_OFFSET 0x02
59 #define ZM_PHY_TEST_SELECT_OFFSET 0x08
60 #define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A
61 #define ZM_CX_CONFIG_STATUS_OFFSET 0x0B
62 #define ZM_EP0_DATA1_OFFSET 0x0C
63 #define ZM_EP0_DATA2_OFFSET 0x0D
64 #define ZM_EP0_DATA_OFFSET 0x0C
66 #define ZM_INTR_MASK_BYTE_0_OFFSET 0x11
67 #define ZM_INTR_MASK_BYTE_1_OFFSET 0x12
68 #define ZM_INTR_MASK_BYTE_2_OFFSET 0x13
69 #define ZM_INTR_MASK_BYTE_3_OFFSET 0x14
70 #define ZM_INTR_MASK_BYTE_4_OFFSET 0x15
71 #define ZM_INTR_MASK_BYTE_5_OFFSET 0x16
72 #define ZM_INTR_MASK_BYTE_6_OFFSET 0x17
73 #define ZM_INTR_MASK_BYTE_7_OFFSET 0x18
75 #define ZM_INTR_GROUP_OFFSET 0x20
76 #define ZM_INTR_SOURCE_0_OFFSET 0x21
77 #define ZM_INTR_SOURCE_1_OFFSET 0x22
78 #define ZM_INTR_SOURCE_2_OFFSET 0x23
79 #define ZM_INTR_SOURCE_3_OFFSET 0x24
80 #define ZM_INTR_SOURCE_4_OFFSET 0x25
81 #define ZM_INTR_SOURCE_5_OFFSET 0x26
82 #define ZM_INTR_SOURCE_6_OFFSET 0x27
83 #define ZM_INTR_SOURCE_7_OFFSET 0x28
85 #define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F
86 #define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E
88 #define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F
89 #define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E
91 #define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE
92 #define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE
93 #define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF
94 #define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF
96 #define ZM_EP3_DATA_OFFSET 0xF8
97 #define ZM_EP4_DATA_OFFSET 0xFC
99 #define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108
100 #define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110
101 #define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114
103 #define ZM_ADDR_CONV 0x0
105 #define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
107 #define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
109 #define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
111 #define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
113 #define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV)
115 #define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
117 #define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
119 #define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
121 #define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
123 #define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
125 #define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
127 #define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
129 #define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
131 #define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
133 #define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
135 #define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
137 #define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
139 #define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
141 #define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
143 #define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
145 #define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
147 #define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
149 #define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
151 #define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
153 #define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
155 #define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
157 #define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
159 #define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
161 #define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
163 #define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
165 #define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
167 #define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET)
169 #define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET)
171 #define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET)
173 #define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
175 #define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET)
177 #define bmHIGH_SPEED BIT6
178 #define bmCWR_BUF_END BIT1
180 #define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
181 //#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG
182 //#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG
183 //#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG
184 #define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
185 #define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
187 #define mGetByte0(data) ( data & 0xff )
188 #define mGetByte1(data) ( (data >> 8) & 0xff )
189 #define mGetByte2(data) ( (data >> 16) & 0xff )
190 #define mGetByte3(data) ( (data >> 24) & 0xff )
192 //#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6)
193 //#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7)
194 //#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
195 //#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
197 #define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
198 #define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
199 #define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
200 #define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
202 #define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
203 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
204 #define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
205 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
206 #define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
207 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
209 #define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
210 USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
212 #define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
213 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
214 #define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
215 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
216 #define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
217 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
218 #define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
219 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
220 // USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
222 #define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
223 USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
227 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
228 #define HS_C1_I0_A0_EP1_bInterval 00
230 #define HS_C1_I0_A0_EP_NUMBER 0x06
231 #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
232 #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
233 #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
235 #define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH)
236 #define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH)
238 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
239 //#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval
241 #define HS_CONFIGURATION_NUMBER 1
242 #define FS_CONFIGURATION_NUMBER 1
244 #define fDOUBLE_BUF 1
245 #define fDOUBLE_BUF_IN 1
247 #define fFLASH_DISK 0
248 #define fENABLE_ISO 0
250 #if (HS_CONFIGURATION_NUMBER >= 1)
251 // Configuration 0X01
252 #define HS_C1_INTERFACE_NUMBER 0x01
254 #define HS_C1_iConfiguration 0x00
255 #define HS_C1_bmAttribute 0x80
256 #if !(fFLASH_DISK && !fFLASH_BOOT)
257 #define HS_C1_iMaxPower 0xFA
259 #define HS_C1_iMaxPower 0x32
262 #if (HS_C1_INTERFACE_NUMBER >= 1)
264 #define HS_C1_I0_ALT_NUMBER 0X01
265 #if (HS_C1_I0_ALT_NUMBER >= 1)
266 // AlternateSetting 0X00
267 #define HS_C1_I0_A0_bInterfaceNumber 0X00
268 #define HS_C1_I0_A0_bAlternateSetting 0X00
270 //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
271 #define HS_C1_I0_A0_EP_NUMBER 0x06
273 //#define HS_C1_I0_A0_EP_NUMBER 0X03
275 #if !(fFLASH_DISK && !fFLASH_BOOT)
276 #define HS_C1_I0_A0_bInterfaceClass 0XFF
277 #define HS_C1_I0_A0_bInterfaceSubClass 0X00
278 #define HS_C1_I0_A0_bInterfaceProtocol 0X00
280 #define HS_C1_I0_A0_bInterfaceClass 0X08
281 #define HS_C1_I0_A0_bInterfaceSubClass 0X06
282 #define HS_C1_I0_A0_bInterfaceProtocol 0X50
284 #define HS_C1_I0_A0_iInterface 0X00
286 #if (HS_C1_I0_A0_EP_NUMBER >= 1)
288 #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
291 #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
293 #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
295 #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
296 #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
298 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
299 #define HS_C1_I0_A0_EP1_bInterval 00
301 #if (HS_C1_I0_A0_EP_NUMBER >= 2)
303 #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
306 #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
308 #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
310 #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
311 #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
312 #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
313 #define HS_C1_I0_A0_EP2_bInterval 00
315 #if (HS_C1_I0_A0_EP_NUMBER >= 3)
317 #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
318 #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
319 #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
320 #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
321 #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
322 #define HS_C1_I0_A0_EP3_bInterval 01
324 // Note: HS Bulk type require max pkt size = 512
325 // ==> must use Interrupt type for max pkt size = 64
326 #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
328 #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
329 #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
330 #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
331 #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT
332 #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
333 #define HS_C1_I0_A0_EP4_bInterval 01
335 #if (HS_C1_I0_A0_EP_NUMBER >= 5)
337 #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
339 #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
341 #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
343 #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
344 #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
345 #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
346 #define HS_C1_I0_A0_EP5_bInterval 00
348 #if (HS_C1_I0_A0_EP_NUMBER >= 6)
350 #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
352 #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
354 #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
356 #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
357 #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
358 #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
359 #define HS_C1_I0_A0_EP6_bInterval 00
365 #if (HS_CONFIGURATION_NUMBER >= 1)
367 #if (HS_C1_INTERFACE_NUMBER >= 1)
369 #if (HS_C1_I0_ALT_NUMBER >= 1)
370 // AlternateSetting 0
371 #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
372 #if (HS_C1_I0_A0_EP_NUMBER >= 1)
374 #define HS_C1_I0_A0_EP1_FIFO_START FIFO0
375 #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
376 #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
377 #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
378 #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
380 #if (HS_C1_I0_A0_EP_NUMBER >= 2)
383 #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
385 #define HS_C1_I0_A0_EP2_FIFO_START FIFO2
387 #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
388 #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
389 #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
390 #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
392 #if (HS_C1_I0_A0_EP_NUMBER >= 3)
395 // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
396 #define HS_C1_I0_A0_EP3_FIFO_START FIFO14
397 #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
398 #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
399 #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
400 #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
402 #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
404 #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
405 #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
406 #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
407 #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
408 #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
410 #if (HS_C1_I0_A0_EP_NUMBER >= 5)
412 #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
413 #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
414 #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
415 #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
416 #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
418 #if (HS_C1_I0_A0_EP_NUMBER >= 6)
420 #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
421 #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
422 #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
423 #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
424 #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
428 #if (HS_C1_I0_ALT_NUMBER >= 2)
429 // AlternateSetting 1
430 #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
431 #if (HS_C1_I0_A1_EP_NUMBER >= 1)
433 #define HS_C1_I0_A1_EP1_FIFO_START FIFO0
434 #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
435 #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
436 #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
437 #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
439 #if (HS_C1_I0_A1_EP_NUMBER >= 2)
441 #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
442 #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
443 #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
444 #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
445 #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
447 #if (HS_C1_I0_A1_EP_NUMBER >= 3)
449 #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
450 #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
451 #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
452 #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
453 #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
457 #if (HS_C1_I0_ALT_NUMBER == 1)
458 #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
459 #elif (HS_C1_I0_ALT_NUMBER == 2)
460 #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
464 #if (HS_C1_INTERFACE_NUMBER >= 2)
466 #if (HS_C1_I1_ALT_NUMBER >= 1)
467 // AlternateSetting 0
468 #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
469 #if (HS_C1_I1_A0_EP_NUMBER >= 1)
471 #define HS_C1_I1_A0_EP1_FIFO_START FIFO0
472 #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
473 #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
474 #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
475 #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
477 #if (HS_C1_I1_A0_EP_NUMBER >= 2)
479 #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
480 #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
481 #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
482 #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
483 #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
485 #if (HS_C1_I1_A0_EP_NUMBER >= 3)
487 #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
488 #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
489 #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
490 #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
491 #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
495 #if (HS_C1_I1_ALT_NUMBER >= 2)
496 // AlternateSetting 1
497 #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
498 #if (HS_C1_I1_A1_EP_NUMBER >= 1)
500 #define HS_C1_I1_A1_EP1_FIFO_START FIFO0
501 #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
502 #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
503 #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
504 #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
506 #if (HS_C1_I1_A1_EP_NUMBER >= 2)
508 #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
509 #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
510 #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
511 #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
512 #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
514 #if (HS_C1_I1_A1_EP_NUMBER >= 3)
516 #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
517 #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
518 #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
519 #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
520 #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
524 #if (HS_C1_I1_ALT_NUMBER == 1)
525 #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH)
526 #elif (HS_C1_I1_ALT_NUMBER == 2)
527 #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
531 #if (HS_C1_INTERFACE_NUMBER == 1)
532 #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
533 #elif (HS_C1_INTERFACE_NUMBER == 2)
534 #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
538 #if (FS_CONFIGURATION_NUMBER >= 1)
539 // Configuration 0X01
540 #define FS_C1_INTERFACE_NUMBER 0X01
542 #define FS_C1_iConfiguration 0X00
543 #define FS_C1_bmAttribute 0X80
544 #define FS_C1_iMaxPower 0XFA
546 #if (FS_C1_INTERFACE_NUMBER >= 1)
548 #define FS_C1_I0_ALT_NUMBER 0X01
549 #if (FS_C1_I0_ALT_NUMBER >= 1)
550 // AlternateSetting 0X00
551 #define FS_C1_I0_A0_bInterfaceNumber 0X00
552 #define FS_C1_I0_A0_bAlternateSetting 0X00
554 //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
555 #define FS_C1_I0_A0_EP_NUMBER 0x05
557 //#define FS_C1_I0_A0_EP_NUMBER 0X03
559 #if !(fFLASH_DISK && !fFLASH_BOOT)
560 #define FS_C1_I0_A0_bInterfaceClass 0XFF
561 #define FS_C1_I0_A0_bInterfaceSubClass 0X00
562 #define FS_C1_I0_A0_bInterfaceProtocol 0X00
564 #define FS_C1_I0_A0_bInterfaceClass 0X08
565 #define FS_C1_I0_A0_bInterfaceSubClass 0X06
566 #define FS_C1_I0_A0_bInterfaceProtocol 0X50
568 #define FS_C1_I0_A0_iInterface 0X00
570 #if (FS_C1_I0_A0_EP_NUMBER >= 1)
572 #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
575 #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
577 #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
579 #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
580 #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
582 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
583 #define FS_C1_I0_A0_EP1_bInterval 00
585 #if (FS_C1_I0_A0_EP_NUMBER >= 2)
587 #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
590 #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
592 #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
594 #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
595 #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
596 #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
597 #define FS_C1_I0_A0_EP2_bInterval 00
599 #if (FS_C1_I0_A0_EP_NUMBER >= 3)
601 #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
602 #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
603 #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
604 #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
605 #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
606 #define FS_C1_I0_A0_EP3_bInterval 01
608 #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
610 #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
611 #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
612 #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
613 #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK
614 #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
615 #define FS_C1_I0_A0_EP4_bInterval 00
617 #if (FS_C1_I0_A0_EP_NUMBER >= 5)
619 #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
621 #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
623 #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
625 #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
626 #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
627 #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
628 #define FS_C1_I0_A0_EP5_bInterval 00
630 #if (FS_C1_I0_A0_EP_NUMBER >= 6)
632 #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
634 #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
636 #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
638 #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
639 #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
640 #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
641 #define FS_C1_I0_A0_EP6_bInterval 00
647 #if (FS_CONFIGURATION_NUMBER >= 1)
649 #if (FS_C1_INTERFACE_NUMBER >= 1)
651 #if (FS_C1_I0_ALT_NUMBER >= 1)
652 // AlternateSetting 0
653 #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
654 #if (FS_C1_I0_A0_EP_NUMBER >= 1)
656 #define FS_C1_I0_A0_EP1_FIFO_START FIFO0
657 #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
658 #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
659 #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
660 #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
662 #if (FS_C1_I0_A0_EP_NUMBER >= 2)
664 #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
665 #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
666 #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
667 #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
668 #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
670 #if (FS_C1_I0_A0_EP_NUMBER >= 3)
673 // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
674 #define FS_C1_I0_A0_EP3_FIFO_START FIFO14
675 #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
676 #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
677 #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
678 #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
680 #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
682 #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
683 #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
684 #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
685 #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
686 #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
688 #if (FS_C1_I0_A0_EP_NUMBER >= 5)
690 #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
691 #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
692 #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
693 #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
694 #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
696 #if (FS_C1_I0_A0_EP_NUMBER >= 6)
698 #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
699 #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
700 #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
701 #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
702 #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
706 #if (FS_C1_I0_ALT_NUMBER >= 2)
707 // AlternateSetting 1
708 #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
709 #if (FS_C1_I0_A1_EP_NUMBER >= 1)
711 #define FS_C1_I0_A1_EP1_FIFO_START FIFO0
712 #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
713 #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
714 #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
715 #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
717 #if (FS_C1_I0_A1_EP_NUMBER >= 2)
719 #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
720 #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
721 #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
722 #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
723 #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
725 #if (FS_C1_I0_A1_EP_NUMBER >= 3)
727 #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
728 #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
729 #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
730 #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
731 #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
735 #if (FS_C1_I0_ALT_NUMBER == 1)
736 #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH)
737 #elif (FS_C1_I0_ALT_NUMBER == 2)
738 #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
742 #if (FS_C1_INTERFACE_NUMBER >= 2)
744 #if (FS_C1_I1_ALT_NUMBER >= 1)
745 // AlternateSetting 0
746 #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
747 #if (FS_C1_I1_A0_EP_NUMBER >= 1)
749 #define FS_C1_I1_A0_EP1_FIFO_START FIFO0
750 #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
751 #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
752 #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
753 #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
755 #if (FS_C1_I1_A0_EP_NUMBER >= 2)
757 #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
758 #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
759 #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
760 #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
761 #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
763 #if (FS_C1_I1_A0_EP_NUMBER >= 3)
765 #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
766 #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
767 #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
768 #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
769 #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
773 #if (FS_C1_I1_ALT_NUMBER >= 2)
774 // AlternateSetting 1
775 #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
776 #if (FS_C1_I1_A1_EP_NUMBER >= 1)
778 #define FS_C1_I1_A1_EP1_FIFO_START FIFO0
779 #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
780 #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
781 #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
782 #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
784 #if (FS_C1_I1_A1_EP_NUMBER >= 2)
786 #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
787 #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
788 #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
789 #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
790 #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
792 #if (FS_C1_I1_A1_EP_NUMBER >= 3)
794 #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
795 #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
796 #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
797 #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
798 #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
802 #if (FS_C1_I1_ALT_NUMBER == 1)
803 #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH)
804 #elif (FS_C1_I1_ALT_NUMBER == 2)
805 #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
809 #if (FS_C1_INTERFACE_NUMBER == 1)
810 #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH)
811 #elif (FS_C1_INTERFACE_NUMBER == 2)
812 #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
816 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
817 #define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
818 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
820 #define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
821 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
823 #define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
824 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode
826 #define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
827 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode
829 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
830 #define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
831 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable
833 #define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
834 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable
836 #define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
837 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode
839 #define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
840 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode
842 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
843 #define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
844 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
846 #define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
847 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
849 #define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
850 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode
852 #define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
853 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode
855 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
856 #define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
858 #define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
860 #define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode
862 #define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode
864 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
866 #define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \
867 USB_UP_PACKET_MODE(); \
870 #define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \
871 USB_LP_DN_PACKET_MODE(); \
872 USB_ENABLE_LP_DN_DMA()
874 #define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \
875 USB_MP_DN_PACKET_MODE(); \
876 USB_ENABLE_MP_DN_DMA();
878 #define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \
879 USB_HP_DN_PACKET_MODE(); \
880 USB_ENABLE_HP_DN_DMA();
882 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
883 #define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \
884 USB_UP_STREAM_MODE(); \
887 #define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \
888 USB_LP_DN_STREAM_MODE(); \
889 USB_ENABLE_LP_DN_DMA()
891 #define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \
892 USB_MP_DN_STREAM_MODE(); \
893 USB_ENABLE_MP_DN_DMA();
895 #define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \
896 USB_HP_DN_STREAM_MODE(); \
897 USB_ENABLE_HP_DN_DMA();
899 #define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
900 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
901 #define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea
902 #define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea