1 /*************************************************************************/
2 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
4 /* Module Name : uart.h */
7 /* This file contains definition of uart registers, marco and api. */
12 /*************************************************************************/
19 /************************* Register Process marco ************************/
20 #define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val))
21 #define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr))
23 /************************** Register deinition ***************************/
24 #define RBR_ADDRESS 0x00051000
25 #define RBR_OFFSET 0x00000000
28 #define RBR_RBR_MASK 0x000000ff
29 #define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
30 #define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
32 #define THR_ADDRESS 0x00051000
33 #define THR_OFFSET 0x00000000
36 #define THR_THR_MASK 0x000000ff
37 #define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
38 #define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
40 #define DLL_ADDRESS 0x00051000
41 #define DLL_OFFSET 0x00000000
44 #define DLL_DLL_MASK 0x000000ff
45 #define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
46 #define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
48 #define DLH_ADDRESS 0x00051004
49 #define DLH_OFFSET 0x00000004
52 #define DLH_DLH_MASK 0x000000ff
53 #define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
54 #define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
56 #define IER_ADDRESS 0x00051004
57 #define IER_OFFSET 0x00000004
58 #define IER_EDDSI_MSB 3
59 #define IER_EDDSI_LSB 3
60 #define IER_EDDSI_MASK 0x00000008
61 #define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
62 #define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
63 #define IER_ELSI_MSB 2
64 #define IER_ELSI_LSB 2
65 #define IER_ELSI_MASK 0x00000004
66 #define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
67 #define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
68 #define IER_ETBEI_MSB 1
69 #define IER_ETBEI_LSB 1
70 #define IER_ETBEI_MASK 0x00000002
71 #define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
72 #define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
73 #define IER_ERBFI_MSB 0
74 #define IER_ERBFI_LSB 0
75 #define IER_ERBFI_MASK 0x00000001
76 #define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
77 #define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
79 #define IIR_ADDRESS 0x00051008
80 #define IIR_OFFSET 0x00000008
81 #define IIR_FIFO_STATUS_MSB 7
82 #define IIR_FIFO_STATUS_LSB 6
83 #define IIR_FIFO_STATUS_MASK 0x000000c0
84 #define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
85 #define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
88 #define IIR_IID_MASK 0x0000000f
89 #define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
90 #define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
92 #define FCR_ADDRESS 0x00051008
93 #define FCR_OFFSET 0x00000008
94 #define FCR_RCVR_TRIG_MSB 7
95 #define FCR_RCVR_TRIG_LSB 6
96 #define FCR_RCVR_TRIG_MASK 0x000000c0
97 #define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
98 #define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
99 #define FCR_DMA_MODE_MSB 3
100 #define FCR_DMA_MODE_LSB 3
101 #define FCR_DMA_MODE_MASK 0x00000008
102 #define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
103 #define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
104 #define FCR_XMIT_FIFO_RST_MSB 2
105 #define FCR_XMIT_FIFO_RST_LSB 2
106 #define FCR_XMIT_FIFO_RST_MASK 0x00000004
107 #define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
108 #define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
109 #define FCR_RCVR_FIFO_RST_MSB 1
110 #define FCR_RCVR_FIFO_RST_LSB 1
111 #define FCR_RCVR_FIFO_RST_MASK 0x00000002
112 #define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
113 #define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
114 #define FCR_FIFO_EN_MSB 0
115 #define FCR_FIFO_EN_LSB 0
116 #define FCR_FIFO_EN_MASK 0x00000001
117 #define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
118 #define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
120 #define LCR_ADDRESS 0x0005100c
121 #define LCR_OFFSET 0x0000000c
122 #define LCR_DLAB_MSB 7
123 #define LCR_DLAB_LSB 7
124 #define LCR_DLAB_MASK 0x00000080
125 #define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
126 #define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
127 #define LCR_BREAK_MSB 6
128 #define LCR_BREAK_LSB 6
129 #define LCR_BREAK_MASK 0x00000040
130 #define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
131 #define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
132 #define LCR_EPS_MSB 4
133 #define LCR_EPS_LSB 4
134 #define LCR_EPS_MASK 0x00000010
135 #define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
136 #define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
137 #define LCR_PEN_MSB 3
138 #define LCR_PEN_LSB 3
139 #define LCR_PEN_MASK 0x00000008
140 #define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
141 #define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
142 #define LCR_STOP_MSB 2
143 #define LCR_STOP_LSB 2
144 #define LCR_STOP_MASK 0x00000004
145 #define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
146 #define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
147 #define LCR_CLS_MSB 1
148 #define LCR_CLS_LSB 0
149 #define LCR_CLS_MASK 0x00000003
150 #define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
151 #define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
153 #define MCR_ADDRESS 0x00051010
154 #define MCR_OFFSET 0x00000010
155 #define MCR_LOOPBACK_MSB 5
156 #define MCR_LOOPBACK_LSB 5
157 #define MCR_LOOPBACK_MASK 0x00000020
158 #define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
159 #define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
160 #define MCR_OUT2_MSB 3
161 #define MCR_OUT2_LSB 3
162 #define MCR_OUT2_MASK 0x00000008
163 #define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
164 #define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
165 #define MCR_OUT1_MSB 2
166 #define MCR_OUT1_LSB 2
167 #define MCR_OUT1_MASK 0x00000004
168 #define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
169 #define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
170 #define MCR_RTS_MSB 1
171 #define MCR_RTS_LSB 1
172 #define MCR_RTS_MASK 0x00000002
173 #define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
174 #define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
175 #define MCR_DTR_MSB 0
176 #define MCR_DTR_LSB 0
177 #define MCR_DTR_MASK 0x00000001
178 #define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
179 #define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
181 #define LSR_ADDRESS 0x00051014
182 #define LSR_OFFSET 0x00000014
183 #define LSR_FERR_MSB 7
184 #define LSR_FERR_LSB 7
185 #define LSR_FERR_MASK 0x00000080
186 #define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
187 #define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
188 #define LSR_TEMT_MSB 6
189 #define LSR_TEMT_LSB 6
190 #define LSR_TEMT_MASK 0x00000040
191 #define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
192 #define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
193 #define LSR_THRE_MSB 5
194 #define LSR_THRE_LSB 5
195 #define LSR_THRE_MASK 0x00000020
196 #define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
197 #define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
200 #define LSR_BI_MASK 0x00000010
201 #define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
202 #define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
205 #define LSR_FE_MASK 0x00000008
206 #define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
207 #define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
210 #define LSR_PE_MASK 0x00000004
211 #define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
212 #define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
215 #define LSR_OE_MASK 0x00000002
216 #define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
217 #define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
220 #define LSR_DR_MASK 0x00000001
221 #define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
222 #define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
224 #define MSR_ADDRESS 0x00051018
225 #define MSR_OFFSET 0x00000018
226 #define MSR_DCD_MSB 7
227 #define MSR_DCD_LSB 7
228 #define MSR_DCD_MASK 0x00000080
229 #define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
230 #define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
233 #define MSR_RI_MASK 0x00000040
234 #define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
235 #define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
236 #define MSR_DSR_MSB 5
237 #define MSR_DSR_LSB 5
238 #define MSR_DSR_MASK 0x00000020
239 #define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
240 #define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
241 #define MSR_CTS_MSB 4
242 #define MSR_CTS_LSB 4
243 #define MSR_CTS_MASK 0x00000010
244 #define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
245 #define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
246 #define MSR_DDCD_MSB 3
247 #define MSR_DDCD_LSB 3
248 #define MSR_DDCD_MASK 0x00000008
249 #define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
250 #define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
251 #define MSR_TERI_MSB 2
252 #define MSR_TERI_LSB 2
253 #define MSR_TERI_MASK 0x00000004
254 #define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
255 #define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
256 #define MSR_DDSR_MSB 1
257 #define MSR_DDSR_LSB 1
258 #define MSR_DDSR_MASK 0x00000002
259 #define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
260 #define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
261 #define MSR_DCTS_MSB 0
262 #define MSR_DCTS_LSB 0
263 #define MSR_DCTS_MASK 0x00000001
264 #define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
265 #define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
268 /************************** config definition ***************************/
269 #define UART_FIFO_SIZE 512 //Must be 2^N
271 #define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing,
272 /*********************** data struction definition ************************/
273 // data struction definition
276 uint8_t buf[UART_FIFO_SIZE];
278 uint16_t start_index;
280 uint32_t overrun_err;
287 struct uart_api *_uart;
288 struct uart_fifo _tx;
292 /******** hardware API table structure (API descriptions below) *************/
294 uint32_t (*_uart_init)(void);
295 void (*_uart_char_put)(uint8_t ch);
296 uint16_t (*_uart_char_get)(uint8_t* ch);
297 void (*_uart_str_out)(uint8_t* str);
298 void (*_uart_task)(void);
299 uint32_t (*_uart_status)(void);
\r
300 void (*_uart_config)(uint16_t flag);
301 void (*_uart_hwinit)(uint32_t freq, uint32_t baud);
302 //void (*_uart_config)(uint8_t cmd, void *pData);
305 /************************* EXPORT function ***************************/
308 #endif // end of _UART_API_H_