5 #include <adf_os_types.h>
10 #define GMAC_MAX_PKT_LEN 1600
11 #define GMAC_MAX_DESC 5
13 #define GMAC_DISCV_PKT_SZ 1024
14 #define GMAC_DISCV_WAIT 2000
16 #define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/
17 #define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/
19 #define ETH_P_ATH 0x88bd
21 typedef enum hif_gmac_pipe{
22 HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/
23 HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/
27 void (*gmac_boot_init)(void);
30 void cmnos_gmac_module_install(struct gmac_api *boot_apis);
31 void hif_gmac_module_install(struct hif_api *apis);
33 enum __gmac_mii_mode {
42 GMAC_HST_QUERY = 0x0001,
43 GMAC_HST_REPLY = 0x0002,
44 GMAC_TGT_QUERY = 0x0003,
45 GMAC_TGT_REPLY = 0x0004
49 MAG_REG_GPIO_OE = 0x00052000,/*GPIO Output Enable*/
50 MAG_REG_RST = 0x00050010,/*Magpie reset reg*/
51 MAG_REG_RST_AHB = 0x00050018,/*Magpie AHB_ARB reset reg*/
52 MAG_REG_MII0_CTRL = 0x00054100,/*Magpie MII0 Control reg*/
53 MAG_REG_STAT_CTRL = 0x00054104,/*Magpie Status reg*/
55 MAG_REG_ETH_PLL = 0x5600c,
56 MAG_REG_ETHPLL_BYPASS = 0x56010,
60 GMAC_REG_BASE = 0x00060000,
61 GMAC_REG_MAC_CFG1 = 0x00 + GMAC_REG_BASE,/*MAC config 1*/
62 GMAC_REG_MAC_CFG2 = 0x04 + GMAC_REG_BASE,/*MAC config 2*/
63 GMAC_REG_IPG_IFG = 0x08 + GMAC_REG_BASE,/*Inter-packet-gap*/
64 GMAC_REG_HALF_DPLX = 0x0c + GMAC_REG_BASE,/*Half duplex*/
65 GMAC_REG_MAX_FRAME = 0x10 + GMAC_REG_BASE,/*Max frame length*/
66 GMAC_REG_MII_CFG = 0x20 + GMAC_REG_BASE,/*MII mgmt config*/
67 GMAC_REG_MII_CMD = 0x24 + GMAC_REG_BASE,/*MII mgmt command*/
68 GMAC_REG_MII_ADDR = 0x28 + GMAC_REG_BASE,/*MII mgmt address*/
69 GMAC_REG_MII_CTRL = 0x2c + GMAC_REG_BASE,/*MII mgmt control*/
70 GMAC_REG_MII_STAT = 0x30 + GMAC_REG_BASE,/*MII mgmt status*/
71 GMAC_REG_MII_PSTAT = 0x34 + GMAC_REG_BASE,/*MII mgmt Phy status/ind*/
72 GMAC_REG_IF_CTRL = 0x38 + GMAC_REG_BASE,/*Interface control*/
73 GMAC_REG_IF_STAT = 0x3c + GMAC_REG_BASE,/*Interface status*/
74 GMAC_REG_MAC_ADDR1 = 0x40 + GMAC_REG_BASE,/*MAC address 1*/
75 GMAC_REG_MAC_ADDR2 = 0x44 + GMAC_REG_BASE,/*MAC address 2*/
76 GMAC_REG_FIFO_CFG0 = 0x48 + GMAC_REG_BASE,/*FIFO config reg0*/
77 GMAC_REG_FIFO_CFG1 = 0x4c + GMAC_REG_BASE,/*FIFO config reg1*/
78 GMAC_REG_FIFO_CFG2 = 0x50 + GMAC_REG_BASE,/*FIFO config reg2*/
79 GMAC_REG_FIFO_CFG3 = 0x54 + GMAC_REG_BASE,/*FIFO config reg3*/
80 GMAC_REG_FIFO_CFG4 = 0x58 + GMAC_REG_BASE,/*FIFO config reg4*/
81 GMAC_REG_FIFO_CFG5 = 0x5c + GMAC_REG_BASE,/*FIFO config reg5*/
82 GMAC_REG_FIFO_RAM0 = 0x60 + GMAC_REG_BASE,/*FIFO RAM access reg0*/
83 GMAC_REG_FIFO_RAM1 = 0x64 + GMAC_REG_BASE,/*FIFO RAM access reg1*/
84 GMAC_REG_FIFO_RAM2 = 0x68 + GMAC_REG_BASE,/*FIFO RAM access reg2*/
85 GMAC_REG_FIFO_RAM3 = 0x6c + GMAC_REG_BASE,/*FIFO RAM access reg3*/
86 GMAC_REG_FIFO_RAM4 = 0x70 + GMAC_REG_BASE,/*FIFO RAM access reg4*/
87 GMAC_REG_FIFO_RAM5 = 0x74 + GMAC_REG_BASE,/*FIFO RAM access reg5*/
88 GMAC_REG_FIFO_RAM6 = 0x78 + GMAC_REG_BASE,/*FIFO RAM access reg6*/
89 GMAC_REG_FIFO_RAM7 = 0x7c + GMAC_REG_BASE,/*FIFO RAM access reg7*/
93 RST_GMAC = (1 << 9),/*Reset the GMAC */
94 RST_MII = (3 << 11),/*Reset the MII*/
95 RST_OTHERS = 0x5df,/*Reset everybody other than GMAC & MII*/
98 enum __mag_reg_rst_ahb{
101 enum __mag_mii0_ctrl_mode{
102 MII0_CTRL_MODE_GMII = 0x00, /* GMII*/
103 MII0_CTRL_MODE_MII = 0x01, /*MII*/
104 MII0_CTRL_MODE_RGMII = 0x02,/* RGMII */
105 MII0_CTRL_MODE_RMII = 0x03, /* RMII */
106 MII0_CTRL_MASTER_MODE = 0x04 /* master mode */
108 enum __mag_mii0_ctrl_speed {
109 MII0_CTLR_SPEED_10 = 0x00, /* 10 mbps*/
110 MII0_CTRL_SPEED_100 = 0x10, /*MII control address 100 Mbps*/
111 MII0_CTRL_SPEED_1000 = 0x20 /* 1000 */
115 enum __gmac_reg_mac_cfg1{
116 MAC_CFG1_TX_EN = (1 << 0),/*TX enable*/
117 MAC_CFG1_RX_EN = (1 << 2),/*RX enable*/
118 MAC_CFG1_TX_FLOW = (1 << 4),/*TX Flow control enable*/
119 MAC_CFG1_RX_FLOW = (1 << 5),/*RX Flow control enable*/
120 MAC_CFG1_LOOP_EN = (1 << 8),/*Enable loopback*/
122 enum __gmac_reg_mac_cfg2{
123 MAC_CFG2_FULL_DUP = (1 << 0),/*Enable Full Duplex*/
124 MAC_CFG2_PAD_CRC = (1 << 2),/*Enable MAC based CRC insertion*/
125 MAC_CFG2_CHK_LEN = (1 << 4),/*Check Length field*/
126 MAC_CFG2_HUGE_FRM = (1 << 5),/*Allow sending huge frames*/
127 MAC_CFG2_MII = (1 << 8),/*MAC is MII in mode*/
128 MAC_CFG2_GMII = (1 << 9),/*MAC is in GMII mode*/
129 MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/
131 enum __gmac_reg_mii_cfg{
132 MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/
136 /* following are only for F1 phy on emulation board.*/
137 enum __gmac_reg_mii_addr{
138 MII_ADDR_RESET = 0x000,/*Flush the MII address register*/
139 MII_ADDR_STATS = 0x001,/* Stauts register*/
140 MII_ADDR_PHY_IDENT_1 = 0x002,/* phy identifier [18:3]*/
141 MII_ADDR_PHY_IDENT_2 = 0x003,/* phy identifier [19:24]*/
142 MII_ADDR_AUTONEG_ADV = 0x004,/* Autonegotiaion advertise*/
143 MII_ADDR_LINKPART_ABILITY = 0x0005,/* link partner ability*/
144 MII_ADDR_AUTONEG_EXP = 0x0006,/* Autonegotiation expansion*/
145 MII_ADDR_NEXTPG_TX = 0x0007,/* Next page transmit*/
146 MII_ADDR_LINKPART_NEXTPG = 0x0008,/* Link partnet next page*/
147 MII_ADDR_1000BASET_CNTRL = 0x0009,/* 1000 base-t control*/
148 MII_ADDR_1000BSAET_STATUS = 0x000a,/* 1000 base-t status*/
149 MII_ADDR_EXTENDED_STATUS = 0x000f,/* extended status*/
150 MII_ADDR_FUNCTION_CTRL = 0x0010,/* function control*/
151 MII_ADDR_PHY_REG = 0x0011,/*Phy Status Reg*/
152 MII_ADDR_INTERRUPT_ENA = 0x0012,/* interrupt enable*/
153 MII_ADDR_INTERRUPT_STATUS = 0x0013,/* interrupt status*/
154 MII_ADDR_EXTPHY_CTRL = 0x0014,/* extemded phy specific control*/
155 MII_ADDR_CABDET_CTRL = 0x0016,/* cable detect testser control*/
156 MII_ADDR_LED_CTRL = 0x0018,/* LED control*/
157 MII_ADDR_MANLED_OVER = 0x0019,/* Manual LED override*/
158 MII_ADDR_CABDET_STAT = 0x001c,/* cable detect tester status*/
159 MII_ADDR_DEBUGPORT_OFF = 0x001d,/* Debug port address offset*/
160 MII_ADDR_DEBUGPORT_DATA = 0x001e,/* Debug port data */
163 /* definitions for MII_ADDR_RESET register definitions*/
164 #define MII_ADDR_RESET_RESTART_AUTONEG (1 << 9)
165 #define MII_ADDR_RESET_ENABLE_AUTONEG (1 << 12)
166 #define MII_ADDR_RESET_ENABLE_LOOPBACK (1<<14)
167 #define MII_ADDR_RESET_SOFT_RESET (1<<15)
168 /* flags for autonegotiaion register MII_ADDR_AUTONEG_ADV,
169 All writes to this register should be followed by a soft
171 The list is not exhaustive, only required fields added
173 #define MII_AUTONEG_10BT_HALF (1<<5)
174 #define MII_AUTONEG_10BT_FULL (1<<6)
175 #define MII_AUTONEG_100BT_HALF (1<<7)
176 #define MII_AUTONEG_100BT_FULL (1<<8)
177 #define MII_AUTONEG_PAUSE (1<<9)
178 #define MII_1000BASET_1000BT_HALF (1<<8)
179 #define MII_1000BASET_1000BT_FULL (1<<9)
180 enum __gmac_reg_mii_ctrl{
181 MII_CTRL_FULL_DPLX = 0x0100,/*Full Duplex mode*/
182 MII_CTRL_SPEED_100 = 0x2000,/*Link Speed 100 Mbps*/
183 MII_CTRL_LOOPBACK = 0x4000,/*Enable Loopback mode at PHY*/
184 MII_CTRL_RESET = 0x8000,/*BMCR reset*/
186 enum __gma_reg_mii_cmd{
188 MII_CMD_READ = 0x1,/*Perform a Read cycle*/
190 enum __gmac_reg_fifo_cfg0{
191 FIFO_CFG0_EN = 0x1f00,/*Enable all the Fifo module*/
193 enum __gmac_reg_fifo_cfg1{
194 FIFO_CFG1_SIZE_2K = (0x7ff << 16),/*Fifo size is 2K*/
196 enum __gmac_reg_fifo_cfg4{
197 FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/
199 enum __gmac_reg_if_ctrl{
200 IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/
204 #define MAX_MDIO_IO_LEN 14
205 #define MDIO_REG_WIDTH 4
206 #define MDIO_REG_BASE 0x54200
207 #define MDIO_REG_TO_OFFSET( __reg_number__)\
208 (MDIO_REG_BASE + (MDIO_REG_WIDTH * (__reg_number__)))
210 #define MDIO_OWN_TGT 0x01
211 #define MDIO_OWN_HST 0x02
212 #define MDIO_REG_WRITE_DELAY 5 /* 5 micro seconds */
214 /*************************GMAC Data types*******************************/
215 typedef enum __gmac_pkt_type{
221 unsigned char dst[ETH_ALEN];/*destination eth addr */
222 unsigned char src[ETH_ALEN]; /*source ether addr*/
223 A_UINT16 etype;/*ether type*/
224 }__attribute__((packed));
226 * @brief this is will be in big endian format
238 }__attribute__((packed));
240 typedef struct __gmac_hdr{
243 A_UINT16 align_pad;/*pad it for 4 byte boundary*/
244 }__attribute__((packed)) __gmac_hdr_t;
246 /*********************************GMAC softC************************/
248 typedef struct __gmac_softc{