2 * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
5 * It pulls definitions tailored for a specific Xtensa processor configuration.
7 * Sources for binaries meant to be configuration-independent generally avoid
8 * including this file (they may use the configuration-specific HAL library).
9 * It is normal for the HAL library source itself to include this file.
13 * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
14 * These coded instructions, statements, and computer programs are the
15 * copyrighted works and confidential proprietary information of Tensilica Inc.
16 * They may not be modified, copied, reproduced, distributed, or disclosed to
17 * third parties in any manner, medium, or form, in whole or in part, without
18 * the prior written consent of Tensilica Inc.
22 #ifndef XTENSA_CONFIG_CORE_H
23 #define XTENSA_CONFIG_CORE_H
25 /* CONFIGURATION INDEPENDENT DEFINITIONS: */
27 #include <xtensa/hal.h>
32 /* CONFIGURATION SPECIFIC DEFINITIONS: */
34 #include <xtensa/config/core-isa.h>
35 #include <xtensa/config/core-matmap.h>
36 #include <xtensa/config/tie.h>
39 #include "core-matmap.h"
43 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
45 #include <xtensa/config/tie-asm.h>
49 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/
52 /*----------------------------------------------------------------------
54 ----------------------------------------------------------------------*/
57 * Separators for macros that expand into arrays.
58 * These can be predefined by files that #include this one,
59 * when different separators are required.
61 /* Element separator for macros that expand into 1-dimensional arrays: */
65 /* Array separator for macros that expand into 2-dimensional arrays: */
67 #define XCHAL_SEP2 },{
72 /*----------------------------------------------------------------------
74 ----------------------------------------------------------------------*/
77 # define XCHAL_HAVE_LE 0
78 # define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
80 # define XCHAL_HAVE_LE 1
81 # define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN
86 /*----------------------------------------------------------------------
88 ----------------------------------------------------------------------*/
90 /* Indexing macros: */
91 #define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
92 #define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
93 #define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
94 #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
95 #define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM
96 #define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */
97 #define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
98 #define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
99 #define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
100 #define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
101 #define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
102 #define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
105 #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
106 #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
107 #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
108 /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
110 /* These values are constant for existing Xtensa processor implementations: */
111 #define XCHAL_INTLEVEL0_MASK 0x00000000
112 #define XCHAL_INTLEVEL8_MASK 0x00000000
113 #define XCHAL_INTLEVEL9_MASK 0x00000000
114 #define XCHAL_INTLEVEL10_MASK 0x00000000
115 #define XCHAL_INTLEVEL11_MASK 0x00000000
116 #define XCHAL_INTLEVEL12_MASK 0x00000000
117 #define XCHAL_INTLEVEL13_MASK 0x00000000
118 #define XCHAL_INTLEVEL14_MASK 0x00000000
119 #define XCHAL_INTLEVEL15_MASK 0x00000000
121 /* Array of masks of interrupts at each interrupt level: */
122 #define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \
123 XCHAL_SEP XCHAL_INTLEVEL1_MASK \
124 XCHAL_SEP XCHAL_INTLEVEL2_MASK \
125 XCHAL_SEP XCHAL_INTLEVEL3_MASK \
126 XCHAL_SEP XCHAL_INTLEVEL4_MASK \
127 XCHAL_SEP XCHAL_INTLEVEL5_MASK \
128 XCHAL_SEP XCHAL_INTLEVEL6_MASK \
129 XCHAL_SEP XCHAL_INTLEVEL7_MASK \
130 XCHAL_SEP XCHAL_INTLEVEL8_MASK \
131 XCHAL_SEP XCHAL_INTLEVEL9_MASK \
132 XCHAL_SEP XCHAL_INTLEVEL10_MASK \
133 XCHAL_SEP XCHAL_INTLEVEL11_MASK \
134 XCHAL_SEP XCHAL_INTLEVEL12_MASK \
135 XCHAL_SEP XCHAL_INTLEVEL13_MASK \
136 XCHAL_SEP XCHAL_INTLEVEL14_MASK \
137 XCHAL_SEP XCHAL_INTLEVEL15_MASK
139 /* These values are constant for existing Xtensa processor implementations: */
140 #define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
141 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
142 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
143 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
144 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
145 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
146 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
147 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
148 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
150 /* Mask of all low-priority interrupts: */
151 #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK
153 /* Mask of all interrupts masked by PS.EXCM (or CEXCM): */
154 #define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
156 /* Array of masks of interrupts at each range 1..n of interrupt levels: */
157 #define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \
158 XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \
159 XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \
160 XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \
161 XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \
162 XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \
163 XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \
164 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
165 XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \
166 XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \
167 XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \
168 XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \
169 XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \
170 XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \
171 XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \
172 XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK
174 #if 0 /*XCHAL_HAVE_NMI*/
175 /* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */
176 # define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1)
179 /* Array of levels of each possible interrupt: */
180 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
181 XCHAL_SEP XCHAL_INT1_LEVEL \
182 XCHAL_SEP XCHAL_INT2_LEVEL \
183 XCHAL_SEP XCHAL_INT3_LEVEL \
184 XCHAL_SEP XCHAL_INT4_LEVEL \
185 XCHAL_SEP XCHAL_INT5_LEVEL \
186 XCHAL_SEP XCHAL_INT6_LEVEL \
187 XCHAL_SEP XCHAL_INT7_LEVEL \
188 XCHAL_SEP XCHAL_INT8_LEVEL \
189 XCHAL_SEP XCHAL_INT9_LEVEL \
190 XCHAL_SEP XCHAL_INT10_LEVEL \
191 XCHAL_SEP XCHAL_INT11_LEVEL \
192 XCHAL_SEP XCHAL_INT12_LEVEL \
193 XCHAL_SEP XCHAL_INT13_LEVEL \
194 XCHAL_SEP XCHAL_INT14_LEVEL \
195 XCHAL_SEP XCHAL_INT15_LEVEL \
196 XCHAL_SEP XCHAL_INT16_LEVEL \
197 XCHAL_SEP XCHAL_INT17_LEVEL \
198 XCHAL_SEP XCHAL_INT18_LEVEL \
199 XCHAL_SEP XCHAL_INT19_LEVEL \
200 XCHAL_SEP XCHAL_INT20_LEVEL \
201 XCHAL_SEP XCHAL_INT21_LEVEL \
202 XCHAL_SEP XCHAL_INT22_LEVEL \
203 XCHAL_SEP XCHAL_INT23_LEVEL \
204 XCHAL_SEP XCHAL_INT24_LEVEL \
205 XCHAL_SEP XCHAL_INT25_LEVEL \
206 XCHAL_SEP XCHAL_INT26_LEVEL \
207 XCHAL_SEP XCHAL_INT27_LEVEL \
208 XCHAL_SEP XCHAL_INT28_LEVEL \
209 XCHAL_SEP XCHAL_INT29_LEVEL \
210 XCHAL_SEP XCHAL_INT30_LEVEL \
211 XCHAL_SEP XCHAL_INT31_LEVEL
213 /* Array of types of each possible interrupt: */
214 #define XCHAL_INT_TYPES XCHAL_INT0_TYPE \
215 XCHAL_SEP XCHAL_INT1_TYPE \
216 XCHAL_SEP XCHAL_INT2_TYPE \
217 XCHAL_SEP XCHAL_INT3_TYPE \
218 XCHAL_SEP XCHAL_INT4_TYPE \
219 XCHAL_SEP XCHAL_INT5_TYPE \
220 XCHAL_SEP XCHAL_INT6_TYPE \
221 XCHAL_SEP XCHAL_INT7_TYPE \
222 XCHAL_SEP XCHAL_INT8_TYPE \
223 XCHAL_SEP XCHAL_INT9_TYPE \
224 XCHAL_SEP XCHAL_INT10_TYPE \
225 XCHAL_SEP XCHAL_INT11_TYPE \
226 XCHAL_SEP XCHAL_INT12_TYPE \
227 XCHAL_SEP XCHAL_INT13_TYPE \
228 XCHAL_SEP XCHAL_INT14_TYPE \
229 XCHAL_SEP XCHAL_INT15_TYPE \
230 XCHAL_SEP XCHAL_INT16_TYPE \
231 XCHAL_SEP XCHAL_INT17_TYPE \
232 XCHAL_SEP XCHAL_INT18_TYPE \
233 XCHAL_SEP XCHAL_INT19_TYPE \
234 XCHAL_SEP XCHAL_INT20_TYPE \
235 XCHAL_SEP XCHAL_INT21_TYPE \
236 XCHAL_SEP XCHAL_INT22_TYPE \
237 XCHAL_SEP XCHAL_INT23_TYPE \
238 XCHAL_SEP XCHAL_INT24_TYPE \
239 XCHAL_SEP XCHAL_INT25_TYPE \
240 XCHAL_SEP XCHAL_INT26_TYPE \
241 XCHAL_SEP XCHAL_INT27_TYPE \
242 XCHAL_SEP XCHAL_INT28_TYPE \
243 XCHAL_SEP XCHAL_INT29_TYPE \
244 XCHAL_SEP XCHAL_INT30_TYPE \
245 XCHAL_SEP XCHAL_INT31_TYPE
247 /* Array of masks of interrupts for each type of interrupt: */
248 #define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \
249 XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \
250 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \
251 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \
252 XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \
253 XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \
254 XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR
256 /* Interrupts that can be cleared using the INTCLEAR special register: */
257 #define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
258 /* Interrupts that can be triggered using the INTSET special register: */
259 #define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE
261 /* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */
262 #define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \
263 XCHAL_SEP XCHAL_TIMER1_INTERRUPT \
264 XCHAL_SEP XCHAL_TIMER2_INTERRUPT \
265 XCHAL_SEP XCHAL_TIMER3_INTERRUPT
269 /* For backward compatibility and for the array macros, define macros for
270 * each unconfigured interrupt number (unfortunately, the value of
271 * XTHAL_INTTYPE_UNCONFIGURED is not zero): */
272 #if XCHAL_NUM_INTERRUPTS == 0
273 # define XCHAL_INT0_LEVEL 0
274 # define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED
276 #if XCHAL_NUM_INTERRUPTS <= 1
277 # define XCHAL_INT1_LEVEL 0
278 # define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED
280 #if XCHAL_NUM_INTERRUPTS <= 2
281 # define XCHAL_INT2_LEVEL 0
282 # define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED
284 #if XCHAL_NUM_INTERRUPTS <= 3
285 # define XCHAL_INT3_LEVEL 0
286 # define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED
288 #if XCHAL_NUM_INTERRUPTS <= 4
289 # define XCHAL_INT4_LEVEL 0
290 # define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED
292 #if XCHAL_NUM_INTERRUPTS <= 5
293 # define XCHAL_INT5_LEVEL 0
294 # define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED
296 #if XCHAL_NUM_INTERRUPTS <= 6
297 # define XCHAL_INT6_LEVEL 0
298 # define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED
300 #if XCHAL_NUM_INTERRUPTS <= 7
301 # define XCHAL_INT7_LEVEL 0
302 # define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED
304 #if XCHAL_NUM_INTERRUPTS <= 8
305 # define XCHAL_INT8_LEVEL 0
306 # define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED
308 #if XCHAL_NUM_INTERRUPTS <= 9
309 # define XCHAL_INT9_LEVEL 0
310 # define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED
312 #if XCHAL_NUM_INTERRUPTS <= 10
313 # define XCHAL_INT10_LEVEL 0
314 # define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED
316 #if XCHAL_NUM_INTERRUPTS <= 11
317 # define XCHAL_INT11_LEVEL 0
318 # define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED
320 #if XCHAL_NUM_INTERRUPTS <= 12
321 # define XCHAL_INT12_LEVEL 0
322 # define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED
324 #if XCHAL_NUM_INTERRUPTS <= 13
325 # define XCHAL_INT13_LEVEL 0
326 # define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED
328 #if XCHAL_NUM_INTERRUPTS <= 14
329 # define XCHAL_INT14_LEVEL 0
330 # define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED
332 #if XCHAL_NUM_INTERRUPTS <= 15
333 # define XCHAL_INT15_LEVEL 0
334 # define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED
336 #if XCHAL_NUM_INTERRUPTS <= 16
337 # define XCHAL_INT16_LEVEL 0
338 # define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED
340 #if XCHAL_NUM_INTERRUPTS <= 17
341 # define XCHAL_INT17_LEVEL 0
342 # define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
344 #if XCHAL_NUM_INTERRUPTS <= 18
345 # define XCHAL_INT18_LEVEL 0
346 # define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
348 #if XCHAL_NUM_INTERRUPTS <= 19
349 # define XCHAL_INT19_LEVEL 0
350 # define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
352 #if XCHAL_NUM_INTERRUPTS <= 20
353 # define XCHAL_INT20_LEVEL 0
354 # define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
356 #if XCHAL_NUM_INTERRUPTS <= 21
357 # define XCHAL_INT21_LEVEL 0
358 # define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
360 #if XCHAL_NUM_INTERRUPTS <= 22
361 # define XCHAL_INT22_LEVEL 0
362 # define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
364 #if XCHAL_NUM_INTERRUPTS <= 23
365 # define XCHAL_INT23_LEVEL 0
366 # define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
368 #if XCHAL_NUM_INTERRUPTS <= 24
369 # define XCHAL_INT24_LEVEL 0
370 # define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
372 #if XCHAL_NUM_INTERRUPTS <= 25
373 # define XCHAL_INT25_LEVEL 0
374 # define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
376 #if XCHAL_NUM_INTERRUPTS <= 26
377 # define XCHAL_INT26_LEVEL 0
378 # define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
380 #if XCHAL_NUM_INTERRUPTS <= 27
381 # define XCHAL_INT27_LEVEL 0
382 # define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
384 #if XCHAL_NUM_INTERRUPTS <= 28
385 # define XCHAL_INT28_LEVEL 0
386 # define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
388 #if XCHAL_NUM_INTERRUPTS <= 29
389 # define XCHAL_INT29_LEVEL 0
390 # define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
392 #if XCHAL_NUM_INTERRUPTS <= 30
393 # define XCHAL_INT30_LEVEL 0
394 # define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
396 #if XCHAL_NUM_INTERRUPTS <= 31
397 # define XCHAL_INT31_LEVEL 0
398 # define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
403 * Masks and levels corresponding to each *external* interrupt.
406 #define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM)
407 #define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
408 #define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM)
409 #define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
410 #define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM)
411 #define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
412 #define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM)
413 #define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
414 #define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM)
415 #define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
416 #define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM)
417 #define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
418 #define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM)
419 #define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
420 #define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM)
421 #define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
422 #define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM)
423 #define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
424 #define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM)
425 #define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
426 #define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM)
427 #define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
428 #define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM)
429 #define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
430 #define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM)
431 #define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
432 #define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM)
433 #define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
434 #define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM)
435 #define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
436 #define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM)
437 #define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
438 #define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM)
439 #define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
440 #define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM)
441 #define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
442 #define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM)
443 #define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
444 #define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM)
445 #define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
446 #define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM)
447 #define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
448 #define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM)
449 #define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
450 #define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM)
451 #define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
452 #define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM)
453 #define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
454 #define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM)
455 #define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
456 #define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM)
457 #define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
458 #define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM)
459 #define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
460 #define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM)
461 #define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
462 #define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM)
463 #define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
464 #define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM)
465 #define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
466 #define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM)
467 #define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
468 #define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM)
469 #define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
472 /*----------------------------------------------------------------------
473 EXCEPTIONS and VECTORS
474 ----------------------------------------------------------------------*/
476 /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
477 #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
478 #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
479 #ifdef XCHAL_USER_VECTOR_VADDR
480 #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
481 #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
483 #ifdef XCHAL_USER_VECTOR_PADDR
484 # define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
485 # define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
487 #ifdef XCHAL_KERNEL_VECTOR_VADDR
488 # define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
489 # define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
491 #ifdef XCHAL_KERNEL_VECTOR_PADDR
492 # define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
493 # define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
498 # define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
499 /* This one should only get defined if the corresponding intlevel paddr macro exists: */
500 # define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
504 /* Indexing macros: */
505 #define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
506 #define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
509 * General Exception Causes
510 * (values of EXCCAUSE special register set by general exceptions,
511 * which vector to the user, kernel, or double-exception vectors).
513 * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros
514 * defined in <xtensa/corebits.h>. (Note that these have slightly
515 * different names, they don't just have the XCHAL_ prefix removed.)
517 #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */
518 #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */
519 #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */
520 #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
521 #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
522 #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */
523 #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
524 #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */
525 #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
526 #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */
528 #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
529 #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
530 #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
531 #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */
532 #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */
534 #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */
535 #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */
536 #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */
537 #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */
538 #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */
539 #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */
541 #define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */
542 #define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */
543 #define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */
544 #define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */
545 #define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */
546 #define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */
547 #define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */
548 #define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */
549 #define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */
554 * Miscellaneous special register fields.
556 * For each special register, and each field within each register:
557 * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
558 * XCHAL_<regname>_<field>_BITS is the number of bits in the field.
559 * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
561 * XCHAL_<regname>_<field>_SHIFT is the position of the field within
562 * the register, starting from the least significant bit.
564 * DEPRECATED. Please use the equivalent macros defined in
565 * <xtensa/corebits.h>. (Note that these have different names.)
568 /* DBREAKC (special register number 160): */
569 #define XCHAL_DBREAKC_VALIDMASK 0xC000003F
570 #define XCHAL_DBREAKC_MASK_BITS 6
571 #define XCHAL_DBREAKC_MASK_NUM 64
572 #define XCHAL_DBREAKC_MASK_SHIFT 0
573 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F
574 #define XCHAL_DBREAKC_LOADBREAK_BITS 1
575 #define XCHAL_DBREAKC_LOADBREAK_NUM 2
576 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30
577 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000
578 #define XCHAL_DBREAKC_STOREBREAK_BITS 1
579 #define XCHAL_DBREAKC_STOREBREAK_NUM 2
580 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31
581 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000
582 /* PS (special register number 230): */
583 #define XCHAL_PS_VALIDMASK 0x00070F3F
584 #define XCHAL_PS_INTLEVEL_BITS 4
585 #define XCHAL_PS_INTLEVEL_NUM 16
586 #define XCHAL_PS_INTLEVEL_SHIFT 0
587 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F
588 #define XCHAL_PS_EXCM_BITS 1
589 #define XCHAL_PS_EXCM_NUM 2
590 #define XCHAL_PS_EXCM_SHIFT 4
591 #define XCHAL_PS_EXCM_MASK 0x00000010
592 #define XCHAL_PS_UM_BITS 1
593 #define XCHAL_PS_UM_NUM 2
594 #define XCHAL_PS_UM_SHIFT 5
595 #define XCHAL_PS_UM_MASK 0x00000020
596 #define XCHAL_PS_RING_BITS 2
597 #define XCHAL_PS_RING_NUM 4
598 #define XCHAL_PS_RING_SHIFT 6
599 #define XCHAL_PS_RING_MASK 0x000000C0
600 #define XCHAL_PS_OWB_BITS 4
601 #define XCHAL_PS_OWB_NUM 16
602 #define XCHAL_PS_OWB_SHIFT 8
603 #define XCHAL_PS_OWB_MASK 0x00000F00
604 #define XCHAL_PS_CALLINC_BITS 2
605 #define XCHAL_PS_CALLINC_NUM 4
606 #define XCHAL_PS_CALLINC_SHIFT 16
607 #define XCHAL_PS_CALLINC_MASK 0x00030000
608 #define XCHAL_PS_WOE_BITS 1
609 #define XCHAL_PS_WOE_NUM 2
610 #define XCHAL_PS_WOE_SHIFT 18
611 #define XCHAL_PS_WOE_MASK 0x00040000
612 /* EXCCAUSE (special register number 232): */
613 #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F
614 #define XCHAL_EXCCAUSE_BITS 6
615 #define XCHAL_EXCCAUSE_NUM 64
616 #define XCHAL_EXCCAUSE_SHIFT 0
617 #define XCHAL_EXCCAUSE_MASK 0x0000003F
618 /* DEBUGCAUSE (special register number 233): */
619 #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F
620 #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1
621 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2
622 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0
623 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001
624 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1
625 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2
626 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1
627 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002
628 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1
629 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2
630 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2
631 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004
632 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1
633 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2
634 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3
635 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008
636 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1
637 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2
638 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4
639 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010
640 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1
641 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2
642 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5
643 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020
648 /*----------------------------------------------------------------------
650 ----------------------------------------------------------------------*/
652 /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
656 /*----------------------------------------------------------------------
657 INTERNAL I/D RAM/ROMs and XLMI
658 ----------------------------------------------------------------------*/
660 #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
661 #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
662 #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
663 #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
665 #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */
666 #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */
667 #define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */
668 #define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */
669 #define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */
670 #define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */
671 #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
672 #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
673 #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
674 #define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */
675 #define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */
676 #define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */
677 #define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */
678 #define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */
679 #define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */
680 #define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */
681 #define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */
682 #define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */
683 #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
684 #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
685 #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
686 #define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */
687 #define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */
688 #define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */
692 /*----------------------------------------------------------------------
694 ----------------------------------------------------------------------*/
697 /* Max for both I-cache and D-cache (used for general alignment): */
698 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
699 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH
700 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE
702 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH
703 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
706 #define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH)
707 #define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH)
708 /* Max for both I and D caches (used for cache-coherency page alignment): */
709 #if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
710 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH
711 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE
713 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH
714 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE
717 /* Instruction cache tag bits: */
718 #define XCHAL_ICACHE_TAG_V_SHIFT 0
719 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */
720 #if XCHAL_ICACHE_WAYS > 1
721 # define XCHAL_ICACHE_TAG_F_SHIFT 1
722 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */
724 # define XCHAL_ICACHE_TAG_F_SHIFT 0
725 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */
727 #if XCHAL_ICACHE_LINE_LOCKABLE
728 # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1)
729 # define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */
731 # define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT
732 # define XCHAL_ICACHE_TAG_L 0 /* no lock bit */
734 /* Data cache tag bits: */
735 #define XCHAL_DCACHE_TAG_V_SHIFT 0
736 #define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */
737 #if XCHAL_DCACHE_WAYS > 1
738 # define XCHAL_DCACHE_TAG_F_SHIFT 1
739 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */
741 # define XCHAL_DCACHE_TAG_F_SHIFT 0
742 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */
744 #if XCHAL_DCACHE_IS_WRITEBACK
745 # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1)
746 # define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */
748 # define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT
749 # define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */
751 #if XCHAL_DCACHE_LINE_LOCKABLE
752 # define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1)
753 # define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */
755 # define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT
756 # define XCHAL_DCACHE_TAG_L 0 /* no lock bit */
760 /*----------------------------------------------------------------------
762 ----------------------------------------------------------------------*/
764 /* See <xtensa/config/core-matmap.h> for more details. */
766 #define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
768 /* Indexing macros: */
769 #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
770 #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
771 #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
772 #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
773 #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
774 #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
775 #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
776 #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
778 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
779 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
782 /* Number of entries per autorefill way: */
783 #define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
784 #define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
787 * Determine whether we have a full MMU (with Page Table and Protection)
788 * usable for an MMU-based OS:
791 #if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
792 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
794 # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
799 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
801 #if XCHAL_HAVE_PTP_MMU
802 #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
803 #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
804 #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
805 #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
806 #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
807 #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
809 #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
810 #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
811 #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
812 #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
813 #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
814 #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
816 #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
817 #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
818 /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
822 /*----------------------------------------------------------------------
824 ----------------------------------------------------------------------*/
826 /* Data alignment required if used for instructions: */
827 #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
828 # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH
830 # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH
834 * Names kept for backward compatibility.
835 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
836 * under which they are released. In the T10##.# era there was no distinction.)
838 #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR
839 #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR
840 #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME
845 /*----------------------------------------------------------------------
846 COPROCESSORS and EXTRA STATE
847 ----------------------------------------------------------------------*/
849 #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE
850 #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN
851 #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE
852 #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN
854 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
856 #define xchal_extratie_load xchal_ncptie_load
857 #define xchal_extratie_store xchal_ncptie_store
858 #define xchal_extratie_load_a2 xchal_ncptie_load_a2
859 #define xchal_extratie_store_a2 xchal_ncptie_store_a2
860 #define xchal_extra_load xchal_ncp_load
861 #define xchal_extra_store xchal_ncp_store
862 #define xchal_extra_load_a2 xchal_ncp_load_a2
863 #define xchal_extra_store_a2 xchal_ncp_store_a2
864 #define xchal_extra_load_funcbody xchal_ncp_load_a2
865 #define xchal_extra_store_funcbody xchal_ncp_store_a2
867 /* Empty placeholder macros for undefined coprocessors: */
868 # ifndef XCHAL_CP0_NAME
869 # define xchal_cp0_store_a2 xchal_cp0_store a2, a3
870 # define xchal_cp0_load_a2 xchal_cp0_load a2, a3
871 .macro xchal_cp0_store ptr tmp
873 .macro xchal_cp0_load ptr tmp
876 # ifndef XCHAL_CP1_NAME
877 # define xchal_cp1_store_a2 xchal_cp1_store a2, a3
878 # define xchal_cp1_load_a2 xchal_cp1_load a2, a3
879 .macro xchal_cp1_store ptr tmp
881 .macro xchal_cp1_load ptr tmp
884 # ifndef XCHAL_CP2_NAME
885 # define xchal_cp2_store_a2 xchal_cp2_store a2, a3
886 # define xchal_cp2_load_a2 xchal_cp2_load a2, a3
887 .macro xchal_cp2_store ptr tmp
889 .macro xchal_cp2_load ptr tmp
892 # ifndef XCHAL_CP3_NAME
893 # define xchal_cp3_store_a2 xchal_cp3_store a2, a3
894 # define xchal_cp3_load_a2 xchal_cp3_load a2, a3
895 .macro xchal_cp3_store ptr tmp
897 .macro xchal_cp3_load ptr tmp
900 # ifndef XCHAL_CP4_NAME
901 # define xchal_cp4_store_a2 xchal_cp4_store a2, a3
902 # define xchal_cp4_load_a2 xchal_cp4_load a2, a3
903 .macro xchal_cp4_store ptr tmp
905 .macro xchal_cp4_load ptr tmp
908 # ifndef XCHAL_CP5_NAME
909 # define xchal_cp5_store_a2 xchal_cp5_store a2, a3
910 # define xchal_cp5_load_a2 xchal_cp5_load a2, a3
911 .macro xchal_cp5_store ptr tmp
913 .macro xchal_cp5_load ptr tmp
916 # ifndef XCHAL_CP6_NAME
917 # define xchal_cp6_store_a2 xchal_cp6_store a2, a3
918 # define xchal_cp6_load_a2 xchal_cp6_load a2, a3
919 .macro xchal_cp6_store ptr tmp
921 .macro xchal_cp6_load ptr tmp
924 # ifndef XCHAL_CP7_NAME
925 # define xchal_cp7_store_a2 xchal_cp7_store a2, a3
926 # define xchal_cp7_load_a2 xchal_cp7_load a2, a3
927 .macro xchal_cp7_store ptr tmp
929 .macro xchal_cp7_load ptr tmp
933 /********************
934 * Macros to create functions that save and restore the state of *any* TIE
935 * coprocessor (by dynamic index).
939 * Macro that expands to the body of a function
940 * that stores the selected coprocessor's state (registers etc).
941 * Entry: a2 = ptr to save area in which to save cp state
942 * a3 = coprocessor number
943 * Exit: any register a2-a15 (?) may have been clobbered.
945 .macro xchal_cpi_store_funcbody
946 # ifdef XCHAL_CP0_NAME
952 # ifdef XCHAL_CP1_NAME
958 # ifdef XCHAL_CP2_NAME
964 # ifdef XCHAL_CP3_NAME
970 # ifdef XCHAL_CP4_NAME
976 # ifdef XCHAL_CP5_NAME
982 # ifdef XCHAL_CP6_NAME
988 # ifdef XCHAL_CP7_NAME
998 * Macro that expands to the body of a function
999 * that loads the selected coprocessor's state (registers etc).
1000 * Entry: a2 = ptr to save area from which to restore cp state
1001 * a3 = coprocessor number
1002 * Exit: any register a2-a15 (?) may have been clobbered.
1004 .macro xchal_cpi_load_funcbody
1005 # ifdef XCHAL_CP0_NAME
1011 # ifdef XCHAL_CP1_NAME
1017 # ifdef XCHAL_CP2_NAME
1023 # ifdef XCHAL_CP3_NAME
1029 # ifdef XCHAL_CP4_NAME
1035 # ifdef XCHAL_CP5_NAME
1041 # ifdef XCHAL_CP6_NAME
1047 # ifdef XCHAL_CP7_NAME
1056 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/
1059 /* Other default macros for undefined coprocessors: */
1060 #ifndef XCHAL_CP0_NAME
1061 # define XCHAL_CP0_SA_SIZE 0
1062 # define XCHAL_CP0_SA_ALIGN 1
1063 # define XCHAL_CP0_NAME 0
1064 # define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
1065 # define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
1067 #ifndef XCHAL_CP1_NAME
1068 # define XCHAL_CP1_SA_SIZE 0
1069 # define XCHAL_CP1_SA_ALIGN 1
1070 # define XCHAL_CP1_NAME 0
1071 # define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
1072 # define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
1074 #ifndef XCHAL_CP2_NAME
1075 # define XCHAL_CP2_SA_SIZE 0
1076 # define XCHAL_CP2_SA_ALIGN 1
1077 # define XCHAL_CP2_NAME 0
1078 # define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
1079 # define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
1081 #ifndef XCHAL_CP3_NAME
1082 # define XCHAL_CP3_SA_SIZE 0
1083 # define XCHAL_CP3_SA_ALIGN 1
1084 # define XCHAL_CP3_NAME 0
1085 # define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
1086 # define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
1088 #ifndef XCHAL_CP4_NAME
1089 # define XCHAL_CP4_SA_SIZE 0
1090 # define XCHAL_CP4_SA_ALIGN 1
1091 # define XCHAL_CP4_NAME 0
1092 # define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
1093 # define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
1095 #ifndef XCHAL_CP5_NAME
1096 # define XCHAL_CP5_SA_SIZE 0
1097 # define XCHAL_CP5_SA_ALIGN 1
1098 # define XCHAL_CP5_NAME 0
1099 # define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
1100 # define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
1102 #ifndef XCHAL_CP6_NAME
1103 # define XCHAL_CP6_SA_SIZE 0
1104 # define XCHAL_CP6_SA_ALIGN 1
1105 # define XCHAL_CP6_NAME 0
1106 # define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
1107 # define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
1109 #ifndef XCHAL_CP7_NAME
1110 # define XCHAL_CP7_SA_SIZE 0
1111 # define XCHAL_CP7_SA_ALIGN 1
1112 # define XCHAL_CP7_NAME 0
1113 # define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
1114 # define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
1117 /* Indexing macros: */
1118 #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
1119 #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
1120 #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
1121 #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
1123 #define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */
1125 /* Link-time HAL global variables that report coprocessor numbers by name
1126 (names are case-preserved from the original TIE): */
1127 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
1128 # define _XCJOIN(a,b) a ## b
1129 # define XCJOIN(a,b) _XCJOIN(a,b)
1130 # ifdef XCHAL_CP0_NAME
1131 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
1132 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
1134 # ifdef XCHAL_CP1_NAME
1135 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
1136 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
1138 # ifdef XCHAL_CP2_NAME
1139 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
1140 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
1142 # ifdef XCHAL_CP3_NAME
1143 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
1144 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
1146 # ifdef XCHAL_CP4_NAME
1147 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
1148 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
1150 # ifdef XCHAL_CP5_NAME
1151 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
1152 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
1154 # ifdef XCHAL_CP6_NAME
1155 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
1156 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
1158 # ifdef XCHAL_CP7_NAME
1159 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
1160 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
1167 /*----------------------------------------------------------------------
1169 ----------------------------------------------------------------------*/
1172 #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
1173 #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
1174 #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
1176 #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
1177 #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
1178 #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
1180 /* Belongs in xtensa/hal.h: */
1181 #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
1185 * Because information as to exactly which hardware version is targeted
1186 * by a given software build is not always available, compile-time HAL
1187 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
1188 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
1189 * under which they are released. In the T10##.# era there was no distinction.)
1191 #if XCHAL_HW_CONFIGID_RELIABLE
1192 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
1193 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
1194 # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
1195 # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
1197 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
1198 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
1200 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
1201 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
1203 # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
1204 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
1205 # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
1213 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
1214 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
1216 #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
1217 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
1218 || XCHAL_HW_RELEASE_AT(1050,0)))
1222 #endif /*XTENSA_CONFIG_CORE_H*/