1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 * Copyright The Asahi Linux Contributors
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
59 compatible = "apple,blizzard";
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 operating-points-v2 = <&ecluster_opp>;
65 capacity-dmips-mhz = <756>;
66 performance-domains = <&cpufreq_e>;
67 next-level-cache = <&l2_cache_0>;
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
73 compatible = "apple,blizzard";
76 enable-method = "spin-table";
77 cpu-release-addr = <0 0>; /* To be filled by loader */
78 operating-points-v2 = <&ecluster_opp>;
79 capacity-dmips-mhz = <756>;
80 performance-domains = <&cpufreq_e>;
81 next-level-cache = <&l2_cache_0>;
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
87 compatible = "apple,blizzard";
90 enable-method = "spin-table";
91 cpu-release-addr = <0 0>; /* To be filled by loader */
92 operating-points-v2 = <&ecluster_opp>;
93 capacity-dmips-mhz = <756>;
94 performance-domains = <&cpufreq_e>;
95 next-level-cache = <&l2_cache_0>;
96 i-cache-size = <0x20000>;
97 d-cache-size = <0x10000>;
101 compatible = "apple,blizzard";
104 enable-method = "spin-table";
105 cpu-release-addr = <0 0>; /* To be filled by loader */
106 operating-points-v2 = <&ecluster_opp>;
107 capacity-dmips-mhz = <756>;
108 performance-domains = <&cpufreq_e>;
109 next-level-cache = <&l2_cache_0>;
110 i-cache-size = <0x20000>;
111 d-cache-size = <0x10000>;
115 compatible = "apple,avalanche";
118 enable-method = "spin-table";
119 cpu-release-addr = <0 0>; /* To be filled by loader */
120 operating-points-v2 = <&pcluster_opp>;
121 capacity-dmips-mhz = <1024>;
122 performance-domains = <&cpufreq_p>;
123 next-level-cache = <&l2_cache_1>;
124 i-cache-size = <0x30000>;
125 d-cache-size = <0x20000>;
129 compatible = "apple,avalanche";
132 enable-method = "spin-table";
133 cpu-release-addr = <0 0>; /* To be filled by loader */
134 operating-points-v2 = <&pcluster_opp>;
135 capacity-dmips-mhz = <1024>;
136 performance-domains = <&cpufreq_p>;
137 next-level-cache = <&l2_cache_1>;
138 i-cache-size = <0x30000>;
139 d-cache-size = <0x20000>;
143 compatible = "apple,avalanche";
146 enable-method = "spin-table";
147 cpu-release-addr = <0 0>; /* To be filled by loader */
148 operating-points-v2 = <&pcluster_opp>;
149 capacity-dmips-mhz = <1024>;
150 performance-domains = <&cpufreq_p>;
151 next-level-cache = <&l2_cache_1>;
152 i-cache-size = <0x30000>;
153 d-cache-size = <0x20000>;
157 compatible = "apple,avalanche";
160 enable-method = "spin-table";
161 cpu-release-addr = <0 0>; /* To be filled by loader */
162 operating-points-v2 = <&pcluster_opp>;
163 capacity-dmips-mhz = <1024>;
164 performance-domains = <&cpufreq_p>;
165 next-level-cache = <&l2_cache_1>;
166 i-cache-size = <0x30000>;
167 d-cache-size = <0x20000>;
170 l2_cache_0: l2-cache-0 {
171 compatible = "cache";
174 cache-size = <0x400000>;
177 l2_cache_1: l2-cache-1 {
178 compatible = "cache";
181 cache-size = <0x1000000>;
185 ecluster_opp: opp-table-0 {
186 compatible = "operating-points-v2";
190 opp-hz = /bits/ 64 <600000000>;
192 clock-latency-ns = <7500>;
195 opp-hz = /bits/ 64 <912000000>;
197 clock-latency-ns = <20000>;
200 opp-hz = /bits/ 64 <1284000000>;
202 clock-latency-ns = <22000>;
205 opp-hz = /bits/ 64 <1752000000>;
207 clock-latency-ns = <30000>;
210 opp-hz = /bits/ 64 <2004000000>;
212 clock-latency-ns = <35000>;
215 opp-hz = /bits/ 64 <2256000000>;
217 clock-latency-ns = <39000>;
220 opp-hz = /bits/ 64 <2424000000>;
222 clock-latency-ns = <53000>;
226 pcluster_opp: opp-table-1 {
227 compatible = "operating-points-v2";
231 opp-hz = /bits/ 64 <660000000>;
233 clock-latency-ns = <9000>;
236 opp-hz = /bits/ 64 <924000000>;
238 clock-latency-ns = <19000>;
241 opp-hz = /bits/ 64 <1188000000>;
243 clock-latency-ns = <22000>;
246 opp-hz = /bits/ 64 <1452000000>;
248 clock-latency-ns = <24000>;
251 opp-hz = /bits/ 64 <1704000000>;
253 clock-latency-ns = <26000>;
256 opp-hz = /bits/ 64 <1968000000>;
258 clock-latency-ns = <28000>;
261 opp-hz = /bits/ 64 <2208000000>;
263 clock-latency-ns = <30000>;
266 opp-hz = /bits/ 64 <2400000000>;
268 clock-latency-ns = <33000>;
271 opp-hz = /bits/ 64 <2568000000>;
273 clock-latency-ns = <34000>;
276 opp-hz = /bits/ 64 <2724000000>;
278 clock-latency-ns = <36000>;
281 opp-hz = /bits/ 64 <2868000000>;
283 clock-latency-ns = <41000>;
286 opp-hz = /bits/ 64 <2988000000>;
288 clock-latency-ns = <42000>;
291 opp-hz = /bits/ 64 <3096000000>;
293 clock-latency-ns = <44000>;
296 opp-hz = /bits/ 64 <3204000000>;
298 clock-latency-ns = <46000>;
300 /* Not available until CPU deep sleep is implemented */
303 opp-hz = /bits/ 64 <3324000000>;
305 clock-latency-ns = <62000>;
309 opp-hz = /bits/ 64 <3408000000>;
311 clock-latency-ns = <62000>;
315 opp-hz = /bits/ 64 <3504000000>;
317 clock-latency-ns = <62000>;
324 compatible = "arm,armv8-timer";
325 interrupt-parent = <&aic>;
326 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
327 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
328 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
329 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
330 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
334 compatible = "apple,blizzard-pmu";
335 interrupt-parent = <&aic>;
336 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
340 compatible = "apple,avalanche-pmu";
341 interrupt-parent = <&aic>;
342 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
346 compatible = "fixed-clock";
348 clock-frequency = <24000000>;
349 clock-output-names = "clkref";
353 * This is a fabulated representation of the input clock
354 * to NCO since we don't know the true clock tree.
356 nco_clkref: clock-ref-nco {
357 compatible = "fixed-clock";
359 clock-output-names = "nco_ref";
363 compatible = "simple-bus";
364 #address-cells = <2>;
370 cpufreq_e: cpufreq@210e20000 {
371 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
372 reg = <0x2 0x10e20000 0 0x1000>;
373 #performance-domain-cells = <0>;
376 cpufreq_p: cpufreq@211e20000 {
377 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
378 reg = <0x2 0x11e20000 0 0x1000>;
379 #performance-domain-cells = <0>;
382 sio_dart: iommu@235004000 {
383 compatible = "apple,t8110-dart";
384 reg = <0x2 0x35004000 0x0 0x4000>;
385 interrupt-parent = <&aic>;
386 interrupts = <AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH>;
388 power-domains = <&ps_sio_cpu>;
391 i2c0: i2c@235010000 {
392 compatible = "apple,t8112-i2c", "apple,i2c";
393 reg = <0x2 0x35010000 0x0 0x4000>;
395 interrupt-parent = <&aic>;
396 interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>;
397 pinctrl-0 = <&i2c0_pins>;
398 pinctrl-names = "default";
399 #address-cells = <0x1>;
401 power-domains = <&ps_i2c0>;
405 i2c1: i2c@235014000 {
406 compatible = "apple,t8112-i2c", "apple,i2c";
407 reg = <0x2 0x35014000 0x0 0x4000>;
409 interrupt-parent = <&aic>;
410 interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>;
411 pinctrl-0 = <&i2c1_pins>;
412 pinctrl-names = "default";
413 #address-cells = <0x1>;
415 power-domains = <&ps_i2c1>;
419 i2c2: i2c@235018000 {
420 compatible = "apple,t8112-i2c", "apple,i2c";
421 reg = <0x2 0x35018000 0x0 0x4000>;
423 interrupt-parent = <&aic>;
424 interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>;
425 pinctrl-0 = <&i2c2_pins>;
426 pinctrl-names = "default";
427 #address-cells = <0x1>;
429 power-domains = <&ps_i2c2>;
433 i2c3: i2c@23501c000 {
434 compatible = "apple,t8112-i2c", "apple,i2c";
435 reg = <0x2 0x3501c000 0x0 0x4000>;
437 interrupt-parent = <&aic>;
438 interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>;
439 pinctrl-0 = <&i2c3_pins>;
440 pinctrl-names = "default";
441 #address-cells = <0x1>;
443 power-domains = <&ps_i2c3>;
447 i2c4: i2c@235020000 {
448 compatible = "apple,t8112-i2c", "apple,i2c";
449 reg = <0x2 0x35020000 0x0 0x4000>;
451 interrupt-parent = <&aic>;
452 interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>;
453 pinctrl-0 = <&i2c4_pins>;
454 pinctrl-names = "default";
455 #address-cells = <0x1>;
457 power-domains = <&ps_i2c4>;
461 fpwm1: pwm@235044000 {
462 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm";
463 reg = <0x2 0x35044000 0x0 0x4000>;
464 power-domains = <&ps_fpwm1>;
470 serial0: serial@235200000 {
471 compatible = "apple,s5l-uart";
472 reg = <0x2 0x35200000 0x0 0x1000>;
474 interrupt-parent = <&aic>;
475 interrupts = <AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH>;
477 * TODO: figure out the clocking properly, there may
478 * be a third selectable clock.
480 clocks = <&clkref>, <&clkref>;
481 clock-names = "uart", "clk_uart_baud0";
482 power-domains = <&ps_uart0>;
486 serial2: serial@235208000 {
487 compatible = "apple,s5l-uart";
488 reg = <0x2 0x35208000 0x0 0x1000>;
490 interrupt-parent = <&aic>;
491 interrupts = <AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clkref>, <&clkref>;
493 clock-names = "uart", "clk_uart_baud0";
494 power-domains = <&ps_uart2>;
498 admac: dma-controller@238200000 {
499 compatible = "apple,t8112-admac", "apple,admac";
500 reg = <0x2 0x38200000 0x0 0x34000>;
502 interrupts-extended = <0>,
503 <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>,
507 iommus = <&sio_dart 2>;
508 power-domains = <&ps_sio_adma>;
509 resets = <&ps_audio_p>;
513 compatible = "apple,t8112-mca", "apple,mca";
514 reg = <0x2 0x38400000 0x0 0x18000>,
515 <0x2 0x38300000 0x0 0x30000>;
517 interrupt-parent = <&aic>;
518 interrupts = <AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH>,
519 <AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH>,
520 <AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH>,
521 <AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH>,
522 <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>,
523 <AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH>;
525 resets = <&ps_audio_p>;
526 clocks = <&nco 0>, <&nco 1>, <&nco 2>,
527 <&nco 3>, <&nco 4>, <&nco 4>;
528 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
529 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
530 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
531 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
532 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
533 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>,
534 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>,
535 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>;
536 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
537 "tx1a", "rx1a", "tx1b", "rx1b",
538 "tx2a", "rx2a", "tx2b", "rx2b",
539 "tx3a", "rx3a", "tx3b", "rx3b",
540 "tx4a", "rx4a", "tx4b", "rx4b",
541 "tx5a", "rx5a", "tx5b", "rx5b";
543 #sound-dai-cells = <1>;
546 nco: clock-controller@23b044000 {
547 compatible = "apple,t8112-nco", "apple,nco";
548 reg = <0x2 0x3b044000 0x0 0x14000>;
549 clocks = <&nco_clkref>;
553 aic: interrupt-controller@23b0c0000 {
554 compatible = "apple,t8112-aic", "apple,aic2";
555 #interrupt-cells = <3>;
556 interrupt-controller;
557 reg = <0x2 0x3b0c0000 0x0 0x8000>,
558 <0x2 0x3b0c8000 0x0 0x4>;
559 reg-names = "core", "event";
560 power-domains = <&ps_aic>;
563 e-core-pmu-affinity {
564 apple,fiq-index = <AIC_CPU_PMU_E>;
565 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
568 p-core-pmu-affinity {
569 apple,fiq-index = <AIC_CPU_PMU_P>;
570 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
575 pmgr: power-management@23b700000 {
576 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
577 #address-cells = <1>;
579 reg = <0x2 0x3b700000 0 0x14000>;
580 /* child nodes are added in t8103-pmgr.dtsi */
583 pinctrl_ap: pinctrl@23c100000 {
584 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
585 reg = <0x2 0x3c100000 0x0 0x100000>;
586 power-domains = <&ps_gpio>;
590 gpio-ranges = <&pinctrl_ap 0 0 213>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 interrupt-parent = <&aic>;
596 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>,
597 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>,
598 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>,
599 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>,
600 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>,
601 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>,
602 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>;
604 i2c0_pins: i2c0-pins {
605 pinmux = <APPLE_PINMUX(111, 1)>,
606 <APPLE_PINMUX(110, 1)>;
609 i2c1_pins: i2c1-pins {
610 pinmux = <APPLE_PINMUX(113, 1)>,
611 <APPLE_PINMUX(112, 1)>;
614 i2c2_pins: i2c2-pins {
615 pinmux = <APPLE_PINMUX(87, 1)>,
616 <APPLE_PINMUX(86, 1)>;
619 i2c3_pins: i2c3-pins {
620 pinmux = <APPLE_PINMUX(54, 1)>,
621 <APPLE_PINMUX(53, 1)>;
624 i2c4_pins: i2c4-pins {
625 pinmux = <APPLE_PINMUX(131, 1)>,
626 <APPLE_PINMUX(130, 1)>;
629 spi3_pins: spi3-pins {
630 pinmux = <APPLE_PINMUX(46, 1)>,
631 <APPLE_PINMUX(47, 1)>,
632 <APPLE_PINMUX(48, 1)>,
633 <APPLE_PINMUX(49, 1)>;
636 pcie_pins: pcie-pins {
637 pinmux = <APPLE_PINMUX(162, 1)>,
638 <APPLE_PINMUX(163, 1)>,
639 <APPLE_PINMUX(164, 1)>;
640 // TODO: 1 more CLKREQs
644 pinctrl_nub: pinctrl@23d1f0000 {
645 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
646 reg = <0x2 0x3d1f0000 0x0 0x4000>;
647 power-domains = <&ps_nub_gpio>;
651 gpio-ranges = <&pinctrl_nub 0 0 24>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
656 interrupt-parent = <&aic>;
657 interrupts = <AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH>,
658 <AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH>,
659 <AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH>,
660 <AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH>,
661 <AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH>,
662 <AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH>,
663 <AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH>;
666 pmgr_mini: power-management@23d280000 {
667 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
668 #address-cells = <1>;
670 reg = <0x2 0x3d280000 0 0x4000>;
671 /* child nodes are added in t8103-pmgr.dtsi */
674 wdt: watchdog@23d2b0000 {
675 compatible = "apple,t8112-wdt", "apple,wdt";
676 reg = <0x2 0x3d2b0000 0x0 0x4000>;
678 interrupt-parent = <&aic>;
679 interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>;
682 pinctrl_smc: pinctrl@23e820000 {
683 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
684 reg = <0x2 0x3e820000 0x0 0x4000>;
688 gpio-ranges = <&pinctrl_smc 0 0 18>;
691 interrupt-controller;
692 #interrupt-cells = <2>;
693 interrupt-parent = <&aic>;
694 interrupts = <AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH>,
695 <AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH>,
696 <AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH>,
697 <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>,
698 <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>,
699 <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>,
700 <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>;
703 pinctrl_aop: pinctrl@24a820000 {
704 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
705 reg = <0x2 0x4a820000 0x0 0x4000>;
709 gpio-ranges = <&pinctrl_aop 0 0 54>;
712 interrupt-controller;
713 #interrupt-cells = <2>;
714 interrupt-parent = <&aic>;
715 interrupts = <AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH>,
716 <AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH>,
717 <AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH>,
718 <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>,
719 <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>,
720 <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>,
721 <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>;
724 ans_mbox: mbox@277408000 {
725 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";
726 reg = <0x2 0x77408000 0x0 0x4000>;
727 interrupt-parent = <&aic>;
728 interrupts = <AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH>,
729 <AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH>,
730 <AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH>,
731 <AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH>;
732 interrupt-names = "send-empty", "send-not-empty",
733 "recv-empty", "recv-not-empty";
735 power-domains = <&ps_ans>;
738 sart: sart@27bc50000 {
739 compatible = "apple,t8112-sart", "apple,t6000-sart";
740 reg = <0x2 0x7bc50000 0x0 0x10000>;
741 power-domains = <&ps_ans>;
745 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2";
746 reg = <0x2 0x7bcc0000 0x0 0x40000>,
747 <0x2 0x77400000 0x0 0x4000>;
748 reg-names = "nvme", "ans";
749 interrupt-parent = <&aic>;
750 interrupts = <AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH>;
751 mboxes = <&ans_mbox>;
752 apple,sart = <&sart>;
753 power-domains = <&ps_ans>, <&ps_apcie_st>;
754 power-domain-names = "ans", "apcie0";
758 pcie0_dart: iommu@681008000 {
759 compatible = "apple,t8110-dart";
760 reg = <0x6 0x81008000 0x0 0x4000>;
762 interrupt-parent = <&aic>;
763 interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>;
764 power-domains = <&ps_apcie_gp>;
767 pcie1_dart: iommu@682008000 {
768 compatible = "apple,t8110-dart";
769 reg = <0x6 0x82008000 0x0 0x4000>;
771 interrupt-parent = <&aic>;
772 interrupts = <AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH>;
773 power-domains = <&ps_apcie_gp>;
777 pcie2_dart: iommu@683008000 {
778 compatible = "apple,t8110-dart";
779 reg = <0x6 0x83008000 0x0 0x4000>;
781 interrupt-parent = <&aic>;
782 interrupts = <AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH>;
783 power-domains = <&ps_apcie_gp>;
787 pcie3_dart: iommu@684008000 {
788 compatible = "apple,t8110-dart";
789 reg = <0x6 0x84008000 0x0 0x4000>;
791 interrupt-parent = <&aic>;
792 interrupts = <AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH>;
793 power-domains = <&ps_apcie_gp>;
797 pcie0: pcie@690000000 {
798 compatible = "apple,t8112-pcie", "apple,pcie";
801 reg = <0x6 0x90000000 0x0 0x1000000>,
802 <0x6 0x80000000 0x0 0x100000>,
803 <0x6 0x81000000 0x0 0x4000>,
804 <0x6 0x82000000 0x0 0x4000>,
805 <0x6 0x83000000 0x0 0x4000>,
806 <0x6 0x84000000 0x0 0x4000>;
807 reg-names = "config", "rc", "port0", "port1", "port2", "port3";
809 interrupt-parent = <&aic>;
810 interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>,
811 <AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>,
812 <AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH>,
813 <AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>;
816 msi-parent = <&pcie0>;
817 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>;
819 iommu-map = <0x100 &pcie0_dart 0 1>,
820 <0x200 &pcie1_dart 1 1>,
821 <0x300 &pcie2_dart 2 1>,
822 <0x400 &pcie3_dart 3 1>;
823 iommu-map-mask = <0xff00>;
826 #address-cells = <3>;
828 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
829 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
831 power-domains = <&ps_apcie_gp>;
832 pinctrl-0 = <&pcie_pins>;
833 pinctrl-names = "default";
837 reg = <0x0 0x0 0x0 0x0 0x0>;
838 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>;
840 #address-cells = <3>;
844 interrupt-controller;
845 #interrupt-cells = <1>;
847 interrupt-map-mask = <0 0 0 7>;
848 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
849 <0 0 0 2 &port00 0 0 0 1>,
850 <0 0 0 3 &port00 0 0 0 2>,
851 <0 0 0 4 &port00 0 0 0 3>;
856 reg = <0x800 0x0 0x0 0x0 0x0>;
857 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>;
859 #address-cells = <3>;
863 interrupt-controller;
864 #interrupt-cells = <1>;
866 interrupt-map-mask = <0 0 0 7>;
867 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
868 <0 0 0 2 &port01 0 0 0 1>,
869 <0 0 0 3 &port01 0 0 0 2>,
870 <0 0 0 4 &port01 0 0 0 3>;
877 reg = <0x1000 0x0 0x0 0x0 0x0>;
878 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>;
880 #address-cells = <3>;
884 interrupt-controller;
885 #interrupt-cells = <1>;
887 interrupt-map-mask = <0 0 0 7>;
888 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
889 <0 0 0 2 &port02 0 0 0 1>,
890 <0 0 0 3 &port02 0 0 0 2>,
891 <0 0 0 4 &port02 0 0 0 3>;
896 /* TODO: GPIO unknown */
899 reg = <0x1800 0x0 0x0 0x0 0x0>;
900 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
902 #address-cells = <3>;
906 interrupt-controller;
907 #interrupt-cells = <1>;
909 interrupt-map-mask = <0 0 0 7>;
910 interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
911 <0 0 0 2 &port03 0 0 0 1>,
912 <0 0 0 3 &port03 0 0 0 2>,
913 <0 0 0 4 &port03 0 0 0 3>;
921 #include "t8112-pmgr.dtsi"