1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Apple T6002 "M1 Ultra" SoC
5 * Other names: H13J, "Jade 2C"
7 * Copyright The Asahi Linux Contributors
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
68 compatible = "apple,icestorm";
71 enable-method = "spin-table";
72 cpu-release-addr = <0 0>; /* To be filled by loader */
73 next-level-cache = <&l2_cache_3>;
74 i-cache-size = <0x20000>;
75 d-cache-size = <0x10000>;
76 operating-points-v2 = <&icestorm_opp>;
77 capacity-dmips-mhz = <714>;
78 performance-domains = <&cpufreq_e_die1>;
82 compatible = "apple,icestorm";
85 enable-method = "spin-table";
86 cpu-release-addr = <0 0>; /* To be filled by loader */
87 next-level-cache = <&l2_cache_3>;
88 i-cache-size = <0x20000>;
89 d-cache-size = <0x10000>;
90 operating-points-v2 = <&icestorm_opp>;
91 capacity-dmips-mhz = <714>;
92 performance-domains = <&cpufreq_e_die1>;
96 compatible = "apple,firestorm";
99 enable-method = "spin-table";
100 cpu-release-addr = <0 0>; /* To be filled by loader */
101 next-level-cache = <&l2_cache_4>;
102 i-cache-size = <0x30000>;
103 d-cache-size = <0x20000>;
104 operating-points-v2 = <&firestorm_opp>;
105 capacity-dmips-mhz = <1024>;
106 performance-domains = <&cpufreq_p0_die1>;
110 compatible = "apple,firestorm";
113 enable-method = "spin-table";
114 cpu-release-addr = <0 0>; /* To be filled by loader */
115 next-level-cache = <&l2_cache_4>;
116 i-cache-size = <0x30000>;
117 d-cache-size = <0x20000>;
118 operating-points-v2 = <&firestorm_opp>;
119 capacity-dmips-mhz = <1024>;
120 performance-domains = <&cpufreq_p0_die1>;
124 compatible = "apple,firestorm";
127 enable-method = "spin-table";
128 cpu-release-addr = <0 0>; /* To be filled by loader */
129 next-level-cache = <&l2_cache_4>;
130 i-cache-size = <0x30000>;
131 d-cache-size = <0x20000>;
132 operating-points-v2 = <&firestorm_opp>;
133 capacity-dmips-mhz = <1024>;
134 performance-domains = <&cpufreq_p0_die1>;
138 compatible = "apple,firestorm";
141 enable-method = "spin-table";
142 cpu-release-addr = <0 0>; /* To be filled by loader */
143 next-level-cache = <&l2_cache_4>;
144 i-cache-size = <0x30000>;
145 d-cache-size = <0x20000>;
146 operating-points-v2 = <&firestorm_opp>;
147 capacity-dmips-mhz = <1024>;
148 performance-domains = <&cpufreq_p0_die1>;
152 compatible = "apple,firestorm";
155 enable-method = "spin-table";
156 cpu-release-addr = <0 0>; /* To be filled by loader */
157 next-level-cache = <&l2_cache_5>;
158 i-cache-size = <0x30000>;
159 d-cache-size = <0x20000>;
160 operating-points-v2 = <&firestorm_opp>;
161 capacity-dmips-mhz = <1024>;
162 performance-domains = <&cpufreq_p1_die1>;
166 compatible = "apple,firestorm";
169 enable-method = "spin-table";
170 cpu-release-addr = <0 0>; /* To be filled by loader */
171 next-level-cache = <&l2_cache_5>;
172 i-cache-size = <0x30000>;
173 d-cache-size = <0x20000>;
174 operating-points-v2 = <&firestorm_opp>;
175 capacity-dmips-mhz = <1024>;
176 performance-domains = <&cpufreq_p1_die1>;
180 compatible = "apple,firestorm";
183 enable-method = "spin-table";
184 cpu-release-addr = <0 0>; /* To be filled by loader */
185 next-level-cache = <&l2_cache_5>;
186 i-cache-size = <0x30000>;
187 d-cache-size = <0x20000>;
188 operating-points-v2 = <&firestorm_opp>;
189 capacity-dmips-mhz = <1024>;
190 performance-domains = <&cpufreq_p1_die1>;
194 compatible = "apple,firestorm";
197 enable-method = "spin-table";
198 cpu-release-addr = <0 0>; /* To be filled by loader */
199 next-level-cache = <&l2_cache_5>;
200 i-cache-size = <0x30000>;
201 d-cache-size = <0x20000>;
202 operating-points-v2 = <&firestorm_opp>;
203 capacity-dmips-mhz = <1024>;
204 performance-domains = <&cpufreq_p1_die1>;
207 l2_cache_3: l2-cache-3 {
208 compatible = "cache";
211 cache-size = <0x400000>;
214 l2_cache_4: l2-cache-4 {
215 compatible = "cache";
218 cache-size = <0xc00000>;
221 l2_cache_5: l2-cache-5 {
222 compatible = "cache";
225 cache-size = <0xc00000>;
229 die0: soc@200000000 {
230 compatible = "simple-bus";
231 #address-cells = <2>;
233 ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
234 <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
235 <0x7 0x0 0x7 0x0 0xf 0x80000000>;
238 // filled via templated includes at the end of the file
241 die1: soc@2200000000 {
242 compatible = "simple-bus";
243 #address-cells = <2>;
245 ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
246 <0x7 0x0 0x27 0x0 0xf 0x80000000>;
249 // filled via templated includes at the end of the file
257 #include "t600x-die0.dtsi"
258 #include "t600x-dieX.dtsi"
261 #include "t600x-pmgr.dtsi"
262 #include "t600x-gpio-pins.dtsi"
271 #include "t600x-dieX.dtsi"
272 #include "t600x-nvme.dtsi"
275 #include "t600x-pmgr.dtsi"
282 e-core-pmu-affinity {
283 apple,fiq-index = <AIC_CPU_PMU_E>;
284 cpus = <&cpu_e00 &cpu_e01
288 p-core-pmu-affinity {
289 apple,fiq-index = <AIC_CPU_PMU_P>;
290 cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
291 &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
292 &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
293 &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
299 // On t6002, the die0 GPU power domain needs both AFR power domains
300 power-domains = <&ps_afr>, <&ps_afr_die1>;