2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __SYSTEM_GLOBAL_H_INCLUDED__
16 #define __SYSTEM_GLOBAL_H_INCLUDED__
18 #include <hive_isp_css_defs.h>
19 #include <type_support.h>
22 * The longest allowed (uninteruptible) bus transfer, does not
23 * take stalling into account
25 #define HIVE_ISP_MAX_BURST_LENGTH 1024
28 * Maximum allowed burst length in words for the ISP DMA
29 * This value is set to 2 to prevent the ISP DMA from blocking
30 * the bus for too long; as the input system can only buffer
31 * 2 lines on Moorefield and Cherrytrail, the input system buffers
32 * may overflow if blocked for too long (BZ 2726).
34 #define ISP_DMA_MAX_BURST_LENGTH 2
37 * Create a list of HAS and IS properties that defines the system
39 * The configuration assumes the following
40 * - The system is hetereogeneous; Multiple cells and devices classes
41 * - The cell and device instances are homogeneous, each device type
42 * belongs to the same class
43 * - Device instances supporting a subset of the class capabilities are
46 * We could manage different device classes through the enumerated
47 * lists (C) or the use of classes (C++), but that is presently not
50 * N.B. the 3 input formatters are of 2 different classess
53 #define USE_INPUT_SYSTEM_VERSION_2401
55 #define IS_ISP_2400_SYSTEM
57 * Since this file is visible everywhere and the system definition
58 * macros are not, detect the separate definitions for {host, SP, ISP}
60 * The 2401 system has the nice property that it uses a vanilla 2400 SP
61 * so the SP will believe it is a 2400 system rather than 2401...
63 /* #if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) || defined(__scalar_processor_2401) */
64 #if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada)
65 #define IS_ISP_2401_MAMOIADA_SYSTEM
66 #define HAS_ISP_2401_MAMOIADA
68 /* #elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) || defined(__scalar_processor_2400)*/
69 #elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada)
70 #define IS_ISP_2400_MAMOIADA_SYSTEM
71 #define HAS_ISP_2400_MAMOIADA
74 #error "system_global.h: 2400_SYSTEM must be one of {2400, 2401 }"
77 #define HAS_MMU_VERSION_2
78 #define HAS_DMA_VERSION_2
79 #define HAS_GDC_VERSION_2
80 #define HAS_VAMEM_VERSION_2
81 #define HAS_HMEM_VERSION_1
82 #define HAS_BAMEM_VERSION_2
83 #define HAS_IRQ_VERSION_2
84 #define HAS_IRQ_MAP_VERSION_2
85 #define HAS_INPUT_FORMATTER_VERSION_2
86 /* 2401: HAS_INPUT_SYSTEM_VERSION_3 */
87 /* 2400: HAS_INPUT_SYSTEM_VERSION_2 */
88 #define HAS_INPUT_SYSTEM_VERSION_2
89 #define HAS_INPUT_SYSTEM_VERSION_2401
90 #define HAS_BUFFERED_SENSOR
91 #define HAS_FIFO_MONITORS_VERSION_2
92 /* #define HAS_GP_REGS_VERSION_2 */
93 #define HAS_GP_DEVICE_VERSION_2
94 #define HAS_GPIO_VERSION_1
95 #define HAS_TIMED_CTRL_VERSION_1
96 #define HAS_RX_VERSION_2
97 #define HAS_NO_INPUT_FORMATTER
98 /*#define HAS_NO_PACKED_RAW_PIXELS*/
99 /*#define HAS_NO_DVS_6AXIS_CONFIG_UPDATE*/
101 #define DMA_DDR_TO_VAMEM_WORKAROUND
102 #define DMA_DDR_TO_HMEM_WORKAROUND
106 * Semi global. "HRT" is accessible from SP, but
107 * the HRT types do not fully apply
109 #define HRT_VADDRESS_WIDTH 32
110 /* Surprise, this is a local property*/
111 /*#define HRT_ADDRESS_WIDTH 64 */
112 #define HRT_DATA_WIDTH 32
114 #define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3)
115 #define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8)
117 /* The main bus connecting all devices */
118 #define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
119 #define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
121 #define CSI2P_DISABLE_ISYS2401_ONLINE_MODE
123 /* per-frame parameter handling support */
124 #define SH_CSS_ENABLE_PER_FRAME_PARAMS
126 typedef uint32_t hrt_bus_align_t;
129 * Enumerate the devices, device access through the API is by ID,
130 * through the DLI by address. The enumerator terminators are used
131 * to size the wiring arrays and as an exception value.
148 #if defined(IS_ISP_2401_MAMOIADA_SYSTEM)
154 #elif defined(IS_ISP_2400_MAMOIADA_SYSTEM)
161 #error "system_global.h: SYSTEM must be one of {2400, 2401}"
175 /* this extra define is needed because we want to use it also
176 in the preprocessor, and that doesn't work with enums.
178 #define N_GDC_ID_CPP 2
198 ISYS_IRQ0_ID = 0, /* port a */
199 ISYS_IRQ1_ID, /* port b */
200 ISYS_IRQ2_ID, /* port c */
205 IRQ0_ID = 0, /* GP IRQ block */
206 IRQ1_ID, /* Input formatter */
207 IRQ2_ID, /* input system */
208 IRQ3_ID, /* input selector */
213 FIFO_MONITOR0_ID = 0,
218 * Deprecated: Since all gp_reg instances are different
219 * and put in the address maps of other devices we cannot
220 * enumerate them as that assumes the instrances are the
223 * We define a single GP_DEVICE containing all gp_regs
224 * w.r.t. a single base address
259 INPUT_FORMATTER0_ID = 0,
264 } input_formatter_ID_t;
266 /* The IF RST is outside the IF */
267 #define INPUT_FORMATTER0_SRST_OFFSET 0x0824
268 #define INPUT_FORMATTER1_SRST_OFFSET 0x0624
269 #define INPUT_FORMATTER2_SRST_OFFSET 0x0424
270 #define INPUT_FORMATTER3_SRST_OFFSET 0x0224
272 #define INPUT_FORMATTER0_SRST_MASK 0x0001
273 #define INPUT_FORMATTER1_SRST_MASK 0x0002
274 #define INPUT_FORMATTER2_SRST_MASK 0x0004
275 #define INPUT_FORMATTER3_SRST_MASK 0x0008
278 INPUT_SYSTEM0_ID = 0,
294 #define N_RX_CHANNEL_ID 4
296 /* Generic port enumeration with an internal port type ID */
309 CAPTURE_UNIT0_ID = 0,
312 ACQUISITION_UNIT0_ID,
321 #define N_CAPTURE_UNIT_ID 3
322 #define N_ACQUISITION_UNIT_ID 1
323 #define N_CTRL_UNIT_ID 1
326 * Input-buffer Controller.
329 IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
330 IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
331 IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
334 /** end of Input-buffer Controller */
340 STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
341 STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
342 STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
348 * Stream2MMIO 0 has 8 SIDs that are indexed by
349 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
351 * Stream2MMIO 1 has 4 SIDs that are indexed by
352 * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
354 * Stream2MMIO 2 has 4 SIDs that are indexed by
355 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
357 STREAM2MMIO_SID0_ID = 0,
366 } stream2mmio_sid_ID_t;
367 /** end of Stream2MMIO */
370 * Input System 2401: CSI-MIPI recevier.
373 CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
374 CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
375 CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
377 } csi_rx_backend_ID_t;
380 CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
381 CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
382 CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
383 #define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID+1)
384 } csi_rx_frontend_ID_t;
387 CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
388 CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
389 CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
390 CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
392 } csi_rx_fe_dlane_ID_t;
393 /** end of CSI-MIPI receiver */
396 ISYS2401_DMA0_ID = 0,
401 * Pixel-generator. ("system_global.h")
409 /** end of pixel-generator. ("system_global.h") */
412 INPUT_SYSTEM_CSI_PORT0_ID = 0,
413 INPUT_SYSTEM_CSI_PORT1_ID,
414 INPUT_SYSTEM_CSI_PORT2_ID,
416 INPUT_SYSTEM_PIXELGEN_PORT0_ID,
417 INPUT_SYSTEM_PIXELGEN_PORT1_ID,
418 INPUT_SYSTEM_PIXELGEN_PORT2_ID,
420 N_INPUT_SYSTEM_INPUT_PORT_ID
421 } input_system_input_port_ID_t;
423 #define N_INPUT_SYSTEM_CSI_PORT 3
426 ISYS2401_DMA_CHANNEL_0 = 0,
427 ISYS2401_DMA_CHANNEL_1,
428 ISYS2401_DMA_CHANNEL_2,
429 ISYS2401_DMA_CHANNEL_3,
430 ISYS2401_DMA_CHANNEL_4,
431 ISYS2401_DMA_CHANNEL_5,
432 ISYS2401_DMA_CHANNEL_6,
433 ISYS2401_DMA_CHANNEL_7,
434 ISYS2401_DMA_CHANNEL_8,
435 ISYS2401_DMA_CHANNEL_9,
436 ISYS2401_DMA_CHANNEL_10,
437 ISYS2401_DMA_CHANNEL_11,
438 N_ISYS2401_DMA_CHANNEL
439 } isys2401_dma_channel;
441 enum ia_css_isp_memories {
442 IA_CSS_ISP_PMEM0 = 0,
453 #define IA_CSS_NUM_MEMORIES 9
454 /* For driver compatability */
455 #define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
456 #define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
458 #endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */