4 * Copyright 2013 Freescale Semiconductor, Inc.
5 * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
6 * Li Yang <leoli@freescale.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/syscore_ops.h>
26 #include <sysdev/fsl_soc.h>
29 #include <asm/mpic_timer.h>
31 #define FSL_GLOBAL_TIMER 0x1
34 * Divide by 64 0x00000300
35 * Divide by 32 0x00000200
36 * Divide by 16 0x00000100
37 * Divide by 8 0x00000000 (Hardware default div)
39 #define MPIC_TIMER_TCR_CLKDIV 0x00000300
41 #define MPIC_TIMER_TCR_ROVR_OFFSET 24
43 #define TIMER_STOP 0x80000000
44 #define GTCCR_TOG 0x80000000
45 #define TIMERS_PER_GROUP 4
46 #define MAX_TICKS (~0U >> 1)
47 #define MAX_TICKS_CASCADE (~0U)
48 #define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num))
62 u32 tcr_value; /* TCR register: CASC & ROVR value */
63 unsigned int cascade_map; /* cascade map */
64 unsigned int timer_num; /* cascade control timer */
67 struct timer_group_priv {
68 struct timer_regs __iomem *regs;
69 struct mpic_timer timer[TIMERS_PER_GROUP];
70 struct list_head node;
71 unsigned int timerfreq;
75 void __iomem *group_tcr;
78 static struct cascade_priv cascade_timer[] = {
79 /* cascade timer 0 and 1 */
81 /* cascade timer 1 and 2 */
83 /* cascade timer 2 and 3 */
87 static LIST_HEAD(timer_group_list);
89 static void convert_ticks_to_time(struct timer_group_priv *priv,
90 const u64 ticks, time64_t *time)
92 *time = (u64)div_u64(ticks, priv->timerfreq);
95 /* the time set by the user is converted to "ticks" */
96 static int convert_time_to_ticks(struct timer_group_priv *priv,
97 time64_t time, u64 *ticks)
99 u64 max_value; /* prevent u64 overflow */
101 max_value = div_u64(ULLONG_MAX, priv->timerfreq);
103 if (time > max_value)
106 *ticks = (u64)time * (u64)priv->timerfreq;
111 /* detect whether there is a cascade timer available */
112 static struct mpic_timer *detect_idle_cascade_timer(
113 struct timer_group_priv *priv)
115 struct cascade_priv *casc_priv;
117 unsigned int array_size = ARRAY_SIZE(cascade_timer);
122 casc_priv = cascade_timer;
123 for (i = 0; i < array_size; i++) {
124 spin_lock_irqsave(&priv->lock, flags);
125 map = casc_priv->cascade_map & priv->idle;
126 if (map == casc_priv->cascade_map) {
127 num = casc_priv->timer_num;
128 priv->timer[num].cascade_handle = casc_priv;
131 priv->idle &= ~casc_priv->cascade_map;
132 spin_unlock_irqrestore(&priv->lock, flags);
133 return &priv->timer[num];
135 spin_unlock_irqrestore(&priv->lock, flags);
142 static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
145 struct cascade_priv *casc_priv;
150 /* set group tcr reg for cascade */
151 casc_priv = priv->timer[num].cascade_handle;
155 tcr = casc_priv->tcr_value |
156 (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
157 setbits32(priv->group_tcr, tcr);
159 tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
161 out_be32(&priv->regs[num].gtccr, 0);
162 out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
164 out_be32(&priv->regs[num - 1].gtccr, 0);
165 out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
170 static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
173 struct mpic_timer *allocated_timer;
175 /* Two cascade timers: Support the maximum time */
176 const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
179 if (ticks > max_ticks)
182 /* detect idle timer */
183 allocated_timer = detect_idle_cascade_timer(priv);
184 if (!allocated_timer)
187 /* set ticks to timer */
188 ret = set_cascade_timer(priv, ticks, allocated_timer->num);
192 return allocated_timer;
195 static struct mpic_timer *get_timer(time64_t time)
197 struct timer_group_priv *priv;
198 struct mpic_timer *timer;
206 list_for_each_entry(priv, &timer_group_list, node) {
207 ret = convert_time_to_ticks(priv, time, &ticks);
211 if (ticks > MAX_TICKS) {
212 if (!(priv->flags & FSL_GLOBAL_TIMER))
215 timer = get_cascade_timer(priv, ticks);
222 for (i = 0; i < TIMERS_PER_GROUP; i++) {
223 /* one timer: Reverse allocation */
224 num = TIMERS_PER_GROUP - 1 - i;
225 spin_lock_irqsave(&priv->lock, flags);
226 if (priv->idle & (1 << i)) {
228 priv->idle &= ~(1 << i);
229 /* set ticks & stop timer */
230 out_be32(&priv->regs[num].gtbcr,
232 out_be32(&priv->regs[num].gtccr, 0);
233 priv->timer[num].cascade_handle = NULL;
234 spin_unlock_irqrestore(&priv->lock, flags);
235 return &priv->timer[num];
237 spin_unlock_irqrestore(&priv->lock, flags);
245 * mpic_start_timer - start hardware timer
246 * @handle: the timer to be started.
248 * It will do ->fn(->dev) callback from the hardware interrupt at
249 * the 'time64_t' point in the future.
251 void mpic_start_timer(struct mpic_timer *handle)
253 struct timer_group_priv *priv = container_of(handle,
254 struct timer_group_priv, timer[handle->num]);
256 clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
258 EXPORT_SYMBOL(mpic_start_timer);
261 * mpic_stop_timer - stop hardware timer
262 * @handle: the timer to be stoped
264 * The timer periodically generates an interrupt. Unless user stops the timer.
266 void mpic_stop_timer(struct mpic_timer *handle)
268 struct timer_group_priv *priv = container_of(handle,
269 struct timer_group_priv, timer[handle->num]);
270 struct cascade_priv *casc_priv;
272 setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
274 casc_priv = priv->timer[handle->num].cascade_handle;
276 out_be32(&priv->regs[handle->num].gtccr, 0);
277 out_be32(&priv->regs[handle->num - 1].gtccr, 0);
279 out_be32(&priv->regs[handle->num].gtccr, 0);
282 EXPORT_SYMBOL(mpic_stop_timer);
285 * mpic_get_remain_time - get timer time
286 * @handle: the timer to be selected.
287 * @time: time for timer
289 * Query timer remaining time.
291 void mpic_get_remain_time(struct mpic_timer *handle, time64_t *time)
293 struct timer_group_priv *priv = container_of(handle,
294 struct timer_group_priv, timer[handle->num]);
295 struct cascade_priv *casc_priv;
300 casc_priv = priv->timer[handle->num].cascade_handle;
302 tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
303 tmp_ticks &= ~GTCCR_TOG;
304 ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
305 tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
308 ticks = in_be32(&priv->regs[handle->num].gtccr);
312 convert_ticks_to_time(priv, ticks, time);
314 EXPORT_SYMBOL(mpic_get_remain_time);
317 * mpic_free_timer - free hardware timer
318 * @handle: the timer to be removed.
322 * Note: can not be used in interrupt context.
324 void mpic_free_timer(struct mpic_timer *handle)
326 struct timer_group_priv *priv = container_of(handle,
327 struct timer_group_priv, timer[handle->num]);
329 struct cascade_priv *casc_priv;
332 mpic_stop_timer(handle);
334 casc_priv = priv->timer[handle->num].cascade_handle;
336 free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
338 spin_lock_irqsave(&priv->lock, flags);
341 tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
342 MPIC_TIMER_TCR_ROVR_OFFSET);
343 clrbits32(priv->group_tcr, tcr);
344 priv->idle |= casc_priv->cascade_map;
345 priv->timer[handle->num].cascade_handle = NULL;
347 priv->idle |= TIMER_OFFSET(handle->num);
349 spin_unlock_irqrestore(&priv->lock, flags);
351 EXPORT_SYMBOL(mpic_free_timer);
354 * mpic_request_timer - get a hardware timer
355 * @fn: interrupt handler function
356 * @dev: callback function of the data
357 * @time: time for timer
359 * This executes the "request_irq", returning NULL
360 * else "handle" on success.
362 struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
365 struct mpic_timer *allocated_timer;
368 if (list_empty(&timer_group_list))
374 allocated_timer = get_timer(time);
375 if (!allocated_timer)
378 ret = request_irq(allocated_timer->irq, fn,
379 IRQF_TRIGGER_LOW, "global-timer", dev);
381 mpic_free_timer(allocated_timer);
385 allocated_timer->dev = dev;
387 return allocated_timer;
389 EXPORT_SYMBOL(mpic_request_timer);
391 static int timer_group_get_freq(struct device_node *np,
392 struct timer_group_priv *priv)
396 if (priv->flags & FSL_GLOBAL_TIMER) {
397 struct device_node *dn;
399 dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
401 of_property_read_u32(dn, "clock-frequency",
407 if (priv->timerfreq <= 0)
410 if (priv->flags & FSL_GLOBAL_TIMER) {
411 div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
412 priv->timerfreq /= div;
418 static int timer_group_get_irq(struct device_node *np,
419 struct timer_group_priv *priv)
421 const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
428 unsigned int irq_index = 0;
432 p = of_get_property(np, "fsl,available-ranges", &len);
433 if (p && len % (2 * sizeof(u32)) != 0) {
434 pr_err("%pOF: malformed available-ranges property.\n", np);
440 len = sizeof(all_timer);
443 len /= 2 * sizeof(u32);
445 for (i = 0; i < len; i++) {
447 count = p[i * 2 + 1];
448 for (j = 0; j < count; j++) {
449 irq = irq_of_parse_and_map(np, irq_index);
451 pr_err("%pOF: irq parse and map failed.\n", np);
456 priv->idle |= TIMER_OFFSET((offset + j));
457 priv->timer[offset + j].irq = irq;
458 priv->timer[offset + j].num = offset + j;
466 static void timer_group_init(struct device_node *np)
468 struct timer_group_priv *priv;
472 priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
474 pr_err("%pOF: cannot allocate memory for group.\n", np);
478 if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
479 priv->flags |= FSL_GLOBAL_TIMER;
481 priv->regs = of_iomap(np, i++);
483 pr_err("%pOF: cannot ioremap timer register address.\n", np);
487 if (priv->flags & FSL_GLOBAL_TIMER) {
488 priv->group_tcr = of_iomap(np, i++);
489 if (!priv->group_tcr) {
490 pr_err("%pOF: cannot ioremap tcr address.\n", np);
495 ret = timer_group_get_freq(np, priv);
497 pr_err("%pOF: cannot get timer frequency.\n", np);
501 ret = timer_group_get_irq(np, priv);
503 pr_err("%pOF: cannot get timer irqs.\n", np);
507 spin_lock_init(&priv->lock);
509 /* Init FSL timer hardware */
510 if (priv->flags & FSL_GLOBAL_TIMER)
511 setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
513 list_add_tail(&priv->node, &timer_group_list);
522 iounmap(priv->group_tcr);
527 static void mpic_timer_resume(void)
529 struct timer_group_priv *priv;
531 list_for_each_entry(priv, &timer_group_list, node) {
532 /* Init FSL timer hardware */
533 if (priv->flags & FSL_GLOBAL_TIMER)
534 setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
538 static const struct of_device_id mpic_timer_ids[] = {
539 { .compatible = "fsl,mpic-global-timer", },
543 static struct syscore_ops mpic_timer_syscore_ops = {
544 .resume = mpic_timer_resume,
547 static int __init mpic_timer_init(void)
549 struct device_node *np = NULL;
551 for_each_matching_node(np, mpic_timer_ids)
552 timer_group_init(np);
554 register_syscore_ops(&mpic_timer_syscore_ops);
556 if (list_empty(&timer_group_list))
561 subsys_initcall(mpic_timer_init);