2 * MPC85xx/86xx PCI Express structure define
4 * Copyright 2007,2011 Freescale Semiconductor, Inc
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 #ifndef __POWERPC_FSL_PCI_H
15 #define __POWERPC_FSL_PCI_H
17 struct platform_device;
20 /* FSL PCI controller BRR1 register */
21 #define PCI_FSL_BRR1 0xbf8
22 #define PCI_FSL_BRR1_VER 0xffff
24 #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
25 #define PCIE_LTSSM_L0 0x16 /* L0 state */
26 #define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
27 #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
28 #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
29 #define PIWAR_EN 0x80000000 /* Enable */
30 #define PIWAR_PF 0x20000000 /* prefetch */
31 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
32 #define PIWAR_READ_SNOOP 0x00050000
33 #define PIWAR_WRITE_SNOOP 0x00005000
34 #define PIWAR_SZ_MASK 0x0000003f
36 #define PEX_PMCR_PTOMR 0x1
37 #define PEX_PMCR_EXL2S 0x2
39 #define PME_DISR_EN_PTOD 0x00008000
40 #define PME_DISR_EN_ENL23D 0x00002000
41 #define PME_DISR_EN_EXL23D 0x00001000
43 /* PCI/PCI Express outbound window reg */
44 struct pci_outbound_window_regs {
45 __be32 potar; /* 0x.0 - Outbound translation address register */
46 __be32 potear; /* 0x.4 - Outbound translation extended address register */
47 __be32 powbar; /* 0x.8 - Outbound window base address register */
49 __be32 powar; /* 0x.10 - Outbound window attributes register */
53 /* PCI/PCI Express inbound window reg */
54 struct pci_inbound_window_regs {
55 __be32 pitar; /* 0x.0 - Inbound translation address register */
57 __be32 piwbar; /* 0x.8 - Inbound window base address register */
58 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
59 __be32 piwar; /* 0x.10 - Inbound window attributes register */
63 /* PCI/PCI Express IO block registers for 85xx/86xx */
65 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
66 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
67 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
68 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
69 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
70 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
71 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
73 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
74 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
75 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
76 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
78 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
79 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
81 /* PCI/PCI Express outbound window 0-4
82 * Window 0 is the default window and is the only window enabled upon reset.
83 * The default outbound register set is used when a transaction misses
84 * in all of the other outbound windows.
86 struct pci_outbound_window_regs pow[5];
88 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
90 /* PCI/PCI Express inbound window 3-0
91 * inbound window 1 supports only a 32-bit base address and does not
92 * define an inbound window base extended address register.
94 struct pci_inbound_window_regs piw[4];
96 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
98 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
100 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
102 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
104 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
105 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
106 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
107 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
109 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
111 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
112 #define PEX_CSR0_LTSSM_MASK 0xFC
113 #define PEX_CSR0_LTSSM_SHIFT 2
114 #define PEX_CSR0_LTSSM_L0 0x11
115 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
120 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
121 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
122 extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
123 extern int mpc83xx_add_bridge(struct device_node *dev);
124 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
126 extern struct device_node *fsl_pci_primary;
129 void fsl_pci_assign_primary(void);
131 static inline void fsl_pci_assign_primary(void) {}
134 #ifdef CONFIG_FSL_PCI
135 extern int fsl_pci_mcheck_exception(struct pt_regs *);
137 static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
140 #endif /* __POWERPC_FSL_PCI_H */
141 #endif /* __KERNEL__ */