2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/msi.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/of_platform.h>
20 #include <linux/interrupt.h>
21 #include <linux/seq_file.h>
22 #include <sysdev/fsl_soc.h>
24 #include <asm/hw_irq.h>
25 #include <asm/ppc-pci.h>
27 #include <asm/fsl_hcalls.h>
32 #define MSIIR_OFFSET_MASK 0xfffff
33 #define MSIIR_IBS_SHIFT 0
34 #define MSIIR_SRS_SHIFT 5
35 #define MSIIR1_IBS_SHIFT 4
36 #define MSIIR1_SRS_SHIFT 0
37 #define MSI_SRS_MASK 0xf
38 #define MSI_IBS_MASK 0x1f
40 #define msi_hwirq(msi, msir_index, intr_index) \
41 ((msir_index) << (msi)->srs_shift | \
42 ((intr_index) << (msi)->ibs_shift))
44 static LIST_HEAD(msi_head);
46 struct fsl_msi_feature {
48 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
51 struct fsl_msi_cascade_data {
52 struct fsl_msi *msi_data;
57 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
59 return in_be32(base + (reg >> 2));
63 * We do not need this actually. The MSIR register has been read once
64 * in the cascade interrupt. So, this MSI interrupt has been acked
66 static void fsl_msi_end_irq(struct irq_data *d)
70 static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
72 struct fsl_msi *msi_data = irqd->domain->host_data;
73 irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
74 int cascade_virq, srs;
76 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
77 cascade_virq = msi_data->cascade_array[srs]->virq;
79 seq_printf(p, " fsl-msi-%d", cascade_virq);
83 static struct irq_chip fsl_msi_chip = {
84 .irq_mask = pci_msi_mask_irq,
85 .irq_unmask = pci_msi_unmask_irq,
86 .irq_ack = fsl_msi_end_irq,
87 .irq_print_chip = fsl_msi_print_chip,
90 static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
93 struct fsl_msi *msi_data = h->host_data;
94 struct irq_chip *chip = &fsl_msi_chip;
96 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
98 irq_set_chip_data(virq, msi_data);
99 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
104 static const struct irq_domain_ops fsl_msi_host_ops = {
105 .map = fsl_msi_host_map,
108 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
112 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
113 irq_domain_get_of_node(msi_data->irqhost));
118 * Reserve all the hwirqs
119 * The available hwirqs will be released in fsl_msi_setup_hwirq()
121 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
122 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
127 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
129 struct msi_desc *entry;
130 struct fsl_msi *msi_data;
131 irq_hw_number_t hwirq;
133 for_each_pci_msi_entry(entry, pdev) {
136 hwirq = virq_to_hw(entry->irq);
137 msi_data = irq_get_chip_data(entry->irq);
138 irq_set_msi_desc(entry->irq, NULL);
139 irq_dispose_mapping(entry->irq);
140 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
146 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
148 struct fsl_msi *fsl_msi_data)
150 struct fsl_msi *msi_data = fsl_msi_data;
151 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
152 u64 address; /* Physical address of the MSIIR */
156 /* If the msi-address-64 property exists, then use it */
157 reg = of_get_property(hose->dn, "msi-address-64", &len);
158 if (reg && (len == sizeof(u64)))
159 address = be64_to_cpup(reg);
161 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
163 msg->address_lo = lower_32_bits(address);
164 msg->address_hi = upper_32_bits(address);
167 * MPIC version 2.0 has erratum PIC1. It causes
168 * that neither MSI nor MSI-X can work fine.
169 * This is a workaround to allow MSI-X to function
170 * properly. It only works for MSI-X, we prevent
171 * MSI on buggy chips in fsl_setup_msi_irqs().
173 if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
174 msg->data = __swab32(hwirq);
178 pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
179 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
180 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
183 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
185 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
186 struct device_node *np;
188 int rc, hwirq = -ENOMEM;
190 struct msi_desc *entry;
192 struct fsl_msi *msi_data;
194 if (type == PCI_CAP_ID_MSI) {
196 * MPIC version 2.0 has erratum PIC1. For now MSI
197 * could not work. So check to prevent MSI from
198 * being used on the board with this erratum.
200 list_for_each_entry(msi_data, &msi_head, list)
201 if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
206 * If the PCI node has an fsl,msi property, then we need to use it
207 * to find the specific MSI.
209 np = of_parse_phandle(hose->dn, "fsl,msi", 0);
211 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
212 of_device_is_compatible(np, "fsl,vmpic-msi") ||
213 of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
214 phandle = np->phandle;
217 "node %pOF has an invalid fsl,msi phandle %u\n",
218 hose->dn, np->phandle);
225 for_each_pci_msi_entry(entry, pdev) {
227 * Loop over all the MSI devices until we find one that has an
228 * available interrupt.
230 list_for_each_entry(msi_data, &msi_head, list) {
232 * If the PCI node has an fsl,msi property, then we
233 * restrict our search to the corresponding MSI node.
234 * The simplest way is to skip over MSI nodes with the
235 * wrong phandle. Under the Freescale hypervisor, this
236 * has the additional benefit of skipping over MSI
237 * nodes that are not mapped in the PAMU.
239 if (phandle && (phandle != msi_data->phandle))
242 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
249 dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
253 virq = irq_create_mapping(msi_data->irqhost, hwirq);
256 dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
257 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
261 /* chip_data is msi_data via host->hostdata in host->map() */
262 irq_set_msi_desc(virq, entry);
264 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
265 pci_write_msi_msg(virq, &msg);
270 /* free by the caller of this function */
274 static irqreturn_t fsl_msi_cascade(int irq, void *data)
276 unsigned int cascade_irq;
277 struct fsl_msi *msi_data;
282 struct fsl_msi_cascade_data *cascade_data = data;
283 irqreturn_t ret = IRQ_NONE;
285 msi_data = cascade_data->msi_data;
287 msir_index = cascade_data->index;
289 if (msir_index >= NR_MSI_REG_MAX)
292 switch (msi_data->feature & FSL_PIC_IP_MASK) {
293 case FSL_PIC_IP_MPIC:
294 msir_value = fsl_msi_read(msi_data->msi_regs,
297 case FSL_PIC_IP_IPIC:
298 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
300 #ifdef CONFIG_EPAPR_PARAVIRT
301 case FSL_PIC_IP_VMPIC: {
303 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
305 pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
306 "irq %u (ret=%u)\n", irq, ret);
315 intr_index = ffs(msir_value) - 1;
317 cascade_irq = irq_linear_revmap(msi_data->irqhost,
318 msi_hwirq(msi_data, msir_index,
319 intr_index + have_shift));
321 generic_handle_irq(cascade_irq);
324 have_shift += intr_index + 1;
325 msir_value = msir_value >> (intr_index + 1);
331 static int fsl_of_msi_remove(struct platform_device *ofdev)
333 struct fsl_msi *msi = platform_get_drvdata(ofdev);
336 if (msi->list.prev != NULL)
337 list_del(&msi->list);
338 for (i = 0; i < NR_MSI_REG_MAX; i++) {
339 if (msi->cascade_array[i]) {
340 virq = msi->cascade_array[i]->virq;
344 free_irq(virq, msi->cascade_array[i]);
345 kfree(msi->cascade_array[i]);
346 irq_dispose_mapping(virq);
349 if (msi->bitmap.bitmap)
350 msi_bitmap_free(&msi->bitmap);
351 if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
352 iounmap(msi->msi_regs);
358 static struct lock_class_key fsl_msi_irq_class;
359 static struct lock_class_key fsl_msi_irq_request_class;
361 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
362 int offset, int irq_index)
364 struct fsl_msi_cascade_data *cascade_data = NULL;
365 int virt_msir, i, ret;
367 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
369 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
370 __func__, irq_index);
374 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
376 dev_err(&dev->dev, "No memory for MSI cascade data\n");
379 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class,
380 &fsl_msi_irq_request_class);
381 cascade_data->index = offset;
382 cascade_data->msi_data = msi;
383 cascade_data->virq = virt_msir;
384 msi->cascade_array[irq_index] = cascade_data;
386 ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
387 "fsl-msi-cascade", cascade_data);
389 dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
394 /* Release the hwirqs corresponding to this MSI register */
395 for (i = 0; i < IRQS_PER_MSI_REG; i++)
396 msi_bitmap_free_hwirqs(&msi->bitmap,
397 msi_hwirq(msi, offset, i), 1);
402 static const struct of_device_id fsl_of_msi_ids[];
403 static int fsl_of_msi_probe(struct platform_device *dev)
405 const struct of_device_id *match;
407 struct resource res, msiir;
408 int err, i, j, irq_index, count;
410 const struct fsl_msi_feature *features;
413 struct pci_controller *phb;
415 match = of_match_device(fsl_of_msi_ids, &dev->dev);
418 features = match->data;
420 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
422 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
424 dev_err(&dev->dev, "No memory for MSI structure\n");
427 platform_set_drvdata(dev, msi);
429 msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
430 NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
432 if (msi->irqhost == NULL) {
433 dev_err(&dev->dev, "No memory for MSI irqhost\n");
439 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
440 * property. Instead, we use hypercalls to access the MSI.
442 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
443 err = of_address_to_resource(dev->dev.of_node, 0, &res);
445 dev_err(&dev->dev, "invalid resource for node %pOF\n",
450 msi->msi_regs = ioremap(res.start, resource_size(&res));
451 if (!msi->msi_regs) {
453 dev_err(&dev->dev, "could not map node %pOF\n",
458 features->msiir_offset + (res.start & 0xfffff);
461 * First read the MSIIR/MSIIR1 offset from dts
462 * On failure use the hardcode MSIIR offset
464 if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
465 msi->msiir_offset = features->msiir_offset +
466 (res.start & MSIIR_OFFSET_MASK);
468 msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
471 msi->feature = features->fsl_pic_ip;
473 /* For erratum PIC1 on MPIC version 2.0*/
474 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
475 && (fsl_mpic_primary_get_version() == 0x0200))
476 msi->feature |= MSI_HW_ERRATA_ENDIAN;
479 * Remember the phandle, so that we can match with any PCI nodes
480 * that have an "fsl,msi" property.
482 msi->phandle = dev->dev.of_node->phandle;
484 err = fsl_msi_init_allocator(msi);
486 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
490 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
492 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
493 of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
494 msi->srs_shift = MSIIR1_SRS_SHIFT;
495 msi->ibs_shift = MSIIR1_IBS_SHIFT;
497 dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
500 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
502 err = fsl_msi_setup_hwirq(msi, dev,
503 irq_index, irq_index);
508 static const u32 all_avail[] =
509 { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
511 msi->srs_shift = MSIIR_SRS_SHIFT;
512 msi->ibs_shift = MSIIR_IBS_SHIFT;
514 if (p && len % (2 * sizeof(u32)) != 0) {
515 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
523 len = sizeof(all_avail);
526 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
527 if (p[i * 2] % IRQS_PER_MSI_REG ||
528 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
529 pr_warn("%s: %pOF: msi available range of %u at %u is not IRQ-aligned\n",
530 __func__, dev->dev.of_node,
531 p[i * 2 + 1], p[i * 2]);
536 offset = p[i * 2] / IRQS_PER_MSI_REG;
537 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
539 for (j = 0; j < count; j++, irq_index++) {
540 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
548 list_add_tail(&msi->list, &msi_head);
551 * Apply the MSI ops to all the controllers.
552 * It doesn't hurt to reassign the same ops,
553 * but bail out if we find another MSI driver.
555 list_for_each_entry(phb, &hose_list, list_node) {
556 if (!phb->controller_ops.setup_msi_irqs) {
557 phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs;
558 phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs;
559 } else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) {
560 dev_err(&dev->dev, "Different MSI driver already installed!\n");
567 fsl_of_msi_remove(dev);
571 static const struct fsl_msi_feature mpic_msi_feature = {
572 .fsl_pic_ip = FSL_PIC_IP_MPIC,
573 .msiir_offset = 0x140,
576 static const struct fsl_msi_feature ipic_msi_feature = {
577 .fsl_pic_ip = FSL_PIC_IP_IPIC,
578 .msiir_offset = 0x38,
581 static const struct fsl_msi_feature vmpic_msi_feature = {
582 .fsl_pic_ip = FSL_PIC_IP_VMPIC,
586 static const struct of_device_id fsl_of_msi_ids[] = {
588 .compatible = "fsl,mpic-msi",
589 .data = &mpic_msi_feature,
592 .compatible = "fsl,mpic-msi-v4.3",
593 .data = &mpic_msi_feature,
596 .compatible = "fsl,ipic-msi",
597 .data = &ipic_msi_feature,
599 #ifdef CONFIG_EPAPR_PARAVIRT
601 .compatible = "fsl,vmpic-msi",
602 .data = &vmpic_msi_feature,
605 .compatible = "fsl,vmpic-msi-v4.3",
606 .data = &vmpic_msi_feature,
612 static struct platform_driver fsl_of_msi_driver = {
615 .of_match_table = fsl_of_msi_ids,
617 .probe = fsl_of_msi_probe,
618 .remove = fsl_of_msi_remove,
621 static __init int fsl_of_msi_init(void)
623 return platform_driver_register(&fsl_of_msi_driver);
626 subsys_initcall(fsl_of_msi_init);