1 // SPDX-License-Identifier: GPL-2.0
3 * General Purpose functions for the global management of the
4 * Communication Processor Module.
5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
7 * In addition to the individual control of the communication
8 * channels, there are a few functions that globally affect the
9 * communication processor.
11 * Buffer descriptors must be allocated from the dual ported memory
12 * space. The allocator for that is here. When the communication
13 * process is reset, we reclaim the memory available. There is
14 * currently no deallocator for this memory.
15 * The amount of space available is platform dependent. On the
16 * MBX, the EPPC software loads additional microcode into the
17 * communication processor, and uses some of the DP ram for this
18 * purpose. Current, the first 512 bytes and the last 256 bytes of
19 * memory are used. Right now I am conservative and only use the
20 * memory that can never be used for microcode. If there are
21 * applications that require more DP ram, we can expand the boundaries
22 * but then we have to be careful of any downloaded microcode.
24 #include <linux/errno.h>
25 #include <linux/sched.h>
26 #include <linux/kernel.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/param.h>
29 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/module.h>
34 #include <linux/spinlock.h>
35 #include <linux/slab.h>
37 #include <asm/pgtable.h>
38 #include <asm/8xx_immap.h>
41 #include <asm/rheap.h>
45 #include <asm/fs_pd.h>
47 #ifdef CONFIG_8xx_GPIO
48 #include <linux/of_gpio.h>
51 #define CPM_MAP_SIZE (0x4000)
53 cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
54 immap_t __iomem *mpc8xx_immr;
55 static cpic8xx_t __iomem *cpic_reg;
57 static struct irq_domain *cpm_pic_host;
59 static void cpm_mask_irq(struct irq_data *d)
61 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
63 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
66 static void cpm_unmask_irq(struct irq_data *d)
68 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
70 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
73 static void cpm_end_irq(struct irq_data *d)
75 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
77 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
80 static struct irq_chip cpm_pic = {
82 .irq_mask = cpm_mask_irq,
83 .irq_unmask = cpm_unmask_irq,
84 .irq_eoi = cpm_end_irq,
91 /* Get the vector by setting the ACK bit and then reading
94 out_be16(&cpic_reg->cpic_civr, 1);
95 cpm_vec = in_be16(&cpic_reg->cpic_civr);
98 return irq_linear_revmap(cpm_pic_host, cpm_vec);
101 static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
104 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
106 irq_set_status_flags(virq, IRQ_LEVEL);
107 irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
111 /* The CPM can generate the error interrupt when there is a race condition
112 * between generating and masking interrupts. All we have to do is ACK it
113 * and return. This is a no-op function so we don't need any special
114 * tests in the interrupt handler.
116 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
121 static struct irqaction cpm_error_irqaction = {
122 .handler = cpm_error_interrupt,
123 .flags = IRQF_NO_THREAD,
127 static const struct irq_domain_ops cpm_pic_host_ops = {
128 .map = cpm_pic_host_map,
131 unsigned int cpm_pic_init(void)
133 struct device_node *np = NULL;
135 unsigned int sirq = 0, hwirq, eirq;
138 pr_debug("cpm_pic_init\n");
140 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
142 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
144 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
148 ret = of_address_to_resource(np, 0, &res);
152 cpic_reg = ioremap(res.start, resource_size(&res));
153 if (cpic_reg == NULL)
156 sirq = irq_of_parse_and_map(np, 0);
160 /* Initialize the CPM interrupt controller. */
161 hwirq = (unsigned int)virq_to_hw(sirq);
162 out_be32(&cpic_reg->cpic_cicr,
163 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
164 ((hwirq/2) << 13) | CICR_HP_MASK);
166 out_be32(&cpic_reg->cpic_cimr, 0);
168 cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
169 if (cpm_pic_host == NULL) {
170 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
175 /* Install our own error handler. */
176 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
178 np = of_find_node_by_type(NULL, "cpm");
180 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
184 eirq = irq_of_parse_and_map(np, 0);
188 if (setup_irq(eirq, &cpm_error_irqaction))
189 printk(KERN_ERR "Could not allocate CPM error IRQ!");
191 setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
198 void __init cpm_reset(void)
200 sysconf8xx_t __iomem *siu_conf;
202 mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
204 printk(KERN_CRIT "Could not map IMMR\n");
208 cpmp = &mpc8xx_immr->im_cpm;
210 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
213 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
217 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
220 #ifdef CONFIG_UCODE_PATCH
221 cpm_load_patch(cpmp);
224 /* Set SDMA Bus Request priority 5.
225 * On 860T, this also enables FEC priority 6. I am not sure
226 * this is what we really want for some applications, but the
227 * manual recommends it.
228 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
230 siu_conf = immr_map(im_siu_conf);
231 if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
232 out_be32(&siu_conf->sc_sdcr, 0x40);
234 out_be32(&siu_conf->sc_sdcr, 1);
235 immr_unmap(siu_conf);
238 static DEFINE_SPINLOCK(cmd_lock);
240 #define MAX_CR_CMD_LOOPS 10000
242 int cpm_command(u32 command, u8 opcode)
247 if (command & 0xffffff0f)
250 spin_lock_irqsave(&cmd_lock, flags);
253 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
254 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
255 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
258 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
261 spin_unlock_irqrestore(&cmd_lock, flags);
264 EXPORT_SYMBOL(cpm_command);
266 /* Set a baud rate generator. This needs lots of work. There are
267 * four BRGs, any of which can be wired to any channel.
268 * The internal baud rate clock is the system clock divided by 16.
269 * This assumes the baudrate is 16x oversampled by the uart.
271 #define BRG_INT_CLK (get_brgfreq())
272 #define BRG_UART_CLK (BRG_INT_CLK/16)
273 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
276 cpm_setbrg(uint brg, uint rate)
280 /* This is good enough to get SMCs running.....
282 bp = &cpmp->cp_brgc1;
284 /* The BRG has a 12-bit counter. For really slow baud rates (or
285 * really fast processors), we may have to further divide by 16.
287 if (((BRG_UART_CLK / rate) - 1) < 4096)
288 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
290 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
291 CPM_BRG_EN | CPM_BRG_DIV16);
293 EXPORT_SYMBOL(cpm_setbrg);
295 struct cpm_ioport16 {
296 __be16 dir, par, odr_sor, dat, intr;
300 struct cpm_ioport32b {
301 __be32 dir, par, odr, dat;
304 struct cpm_ioport32e {
305 __be32 dir, par, sor, odr, dat;
308 static void cpm1_set_pin32(int port, int pin, int flags)
310 struct cpm_ioport32e __iomem *iop;
311 pin = 1 << (31 - pin);
313 if (port == CPM_PORTB)
314 iop = (struct cpm_ioport32e __iomem *)
315 &mpc8xx_immr->im_cpm.cp_pbdir;
317 iop = (struct cpm_ioport32e __iomem *)
318 &mpc8xx_immr->im_cpm.cp_pedir;
320 if (flags & CPM_PIN_OUTPUT)
321 setbits32(&iop->dir, pin);
323 clrbits32(&iop->dir, pin);
325 if (!(flags & CPM_PIN_GPIO))
326 setbits32(&iop->par, pin);
328 clrbits32(&iop->par, pin);
330 if (port == CPM_PORTB) {
331 if (flags & CPM_PIN_OPENDRAIN)
332 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
334 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
337 if (port == CPM_PORTE) {
338 if (flags & CPM_PIN_SECONDARY)
339 setbits32(&iop->sor, pin);
341 clrbits32(&iop->sor, pin);
343 if (flags & CPM_PIN_OPENDRAIN)
344 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
346 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
350 static void cpm1_set_pin16(int port, int pin, int flags)
352 struct cpm_ioport16 __iomem *iop =
353 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
355 pin = 1 << (15 - pin);
360 if (flags & CPM_PIN_OUTPUT)
361 setbits16(&iop->dir, pin);
363 clrbits16(&iop->dir, pin);
365 if (!(flags & CPM_PIN_GPIO))
366 setbits16(&iop->par, pin);
368 clrbits16(&iop->par, pin);
370 if (port == CPM_PORTA) {
371 if (flags & CPM_PIN_OPENDRAIN)
372 setbits16(&iop->odr_sor, pin);
374 clrbits16(&iop->odr_sor, pin);
376 if (port == CPM_PORTC) {
377 if (flags & CPM_PIN_SECONDARY)
378 setbits16(&iop->odr_sor, pin);
380 clrbits16(&iop->odr_sor, pin);
381 if (flags & CPM_PIN_FALLEDGE)
382 setbits16(&iop->intr, pin);
384 clrbits16(&iop->intr, pin);
388 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
390 if (port == CPM_PORTB || port == CPM_PORTE)
391 cpm1_set_pin32(port, pin, flags);
393 cpm1_set_pin16(port, pin, flags);
396 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
404 {CPM_CLK_SCC1, CPM_BRG1, 0},
405 {CPM_CLK_SCC1, CPM_BRG2, 1},
406 {CPM_CLK_SCC1, CPM_BRG3, 2},
407 {CPM_CLK_SCC1, CPM_BRG4, 3},
408 {CPM_CLK_SCC1, CPM_CLK1, 4},
409 {CPM_CLK_SCC1, CPM_CLK2, 5},
410 {CPM_CLK_SCC1, CPM_CLK3, 6},
411 {CPM_CLK_SCC1, CPM_CLK4, 7},
413 {CPM_CLK_SCC2, CPM_BRG1, 0},
414 {CPM_CLK_SCC2, CPM_BRG2, 1},
415 {CPM_CLK_SCC2, CPM_BRG3, 2},
416 {CPM_CLK_SCC2, CPM_BRG4, 3},
417 {CPM_CLK_SCC2, CPM_CLK1, 4},
418 {CPM_CLK_SCC2, CPM_CLK2, 5},
419 {CPM_CLK_SCC2, CPM_CLK3, 6},
420 {CPM_CLK_SCC2, CPM_CLK4, 7},
422 {CPM_CLK_SCC3, CPM_BRG1, 0},
423 {CPM_CLK_SCC3, CPM_BRG2, 1},
424 {CPM_CLK_SCC3, CPM_BRG3, 2},
425 {CPM_CLK_SCC3, CPM_BRG4, 3},
426 {CPM_CLK_SCC3, CPM_CLK5, 4},
427 {CPM_CLK_SCC3, CPM_CLK6, 5},
428 {CPM_CLK_SCC3, CPM_CLK7, 6},
429 {CPM_CLK_SCC3, CPM_CLK8, 7},
431 {CPM_CLK_SCC4, CPM_BRG1, 0},
432 {CPM_CLK_SCC4, CPM_BRG2, 1},
433 {CPM_CLK_SCC4, CPM_BRG3, 2},
434 {CPM_CLK_SCC4, CPM_BRG4, 3},
435 {CPM_CLK_SCC4, CPM_CLK5, 4},
436 {CPM_CLK_SCC4, CPM_CLK6, 5},
437 {CPM_CLK_SCC4, CPM_CLK7, 6},
438 {CPM_CLK_SCC4, CPM_CLK8, 7},
440 {CPM_CLK_SMC1, CPM_BRG1, 0},
441 {CPM_CLK_SMC1, CPM_BRG2, 1},
442 {CPM_CLK_SMC1, CPM_BRG3, 2},
443 {CPM_CLK_SMC1, CPM_BRG4, 3},
444 {CPM_CLK_SMC1, CPM_CLK1, 4},
445 {CPM_CLK_SMC1, CPM_CLK2, 5},
446 {CPM_CLK_SMC1, CPM_CLK3, 6},
447 {CPM_CLK_SMC1, CPM_CLK4, 7},
449 {CPM_CLK_SMC2, CPM_BRG1, 0},
450 {CPM_CLK_SMC2, CPM_BRG2, 1},
451 {CPM_CLK_SMC2, CPM_BRG3, 2},
452 {CPM_CLK_SMC2, CPM_BRG4, 3},
453 {CPM_CLK_SMC2, CPM_CLK5, 4},
454 {CPM_CLK_SMC2, CPM_CLK6, 5},
455 {CPM_CLK_SMC2, CPM_CLK7, 6},
456 {CPM_CLK_SMC2, CPM_CLK8, 7},
461 reg = &mpc8xx_immr->im_cpm.cp_sicr;
466 reg = &mpc8xx_immr->im_cpm.cp_sicr;
471 reg = &mpc8xx_immr->im_cpm.cp_sicr;
476 reg = &mpc8xx_immr->im_cpm.cp_sicr;
481 reg = &mpc8xx_immr->im_cpm.cp_simode;
486 reg = &mpc8xx_immr->im_cpm.cp_simode;
491 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
495 for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
496 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
497 bits = clk_map[i][2];
502 if (i == ARRAY_SIZE(clk_map)) {
503 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
510 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
511 if (mode == CPM_CLK_RTX) {
514 } else if (mode == CPM_CLK_RX) {
520 out_be32(reg, (in_be32(reg) & ~mask) | bits);
526 * GPIO LIB API implementation
528 #ifdef CONFIG_8xx_GPIO
530 struct cpm1_gpio16_chip {
531 struct of_mm_gpio_chip mm_gc;
534 /* shadowed data register to clear/set bits safely */
537 /* IRQ associated with Pins when relevant */
541 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
543 struct cpm1_gpio16_chip *cpm1_gc =
544 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
545 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
547 cpm1_gc->cpdata = in_be16(&iop->dat);
550 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
552 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
553 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
556 pin_mask = 1 << (15 - gpio);
558 return !!(in_be16(&iop->dat) & pin_mask);
561 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
564 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
565 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
568 cpm1_gc->cpdata |= pin_mask;
570 cpm1_gc->cpdata &= ~pin_mask;
572 out_be16(&iop->dat, cpm1_gc->cpdata);
575 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
577 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
578 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
580 u16 pin_mask = 1 << (15 - gpio);
582 spin_lock_irqsave(&cpm1_gc->lock, flags);
584 __cpm1_gpio16_set(mm_gc, pin_mask, value);
586 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
589 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
591 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
592 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
594 return cpm1_gc->irq[gpio] ? : -ENXIO;
597 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
599 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
600 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
601 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
603 u16 pin_mask = 1 << (15 - gpio);
605 spin_lock_irqsave(&cpm1_gc->lock, flags);
607 setbits16(&iop->dir, pin_mask);
608 __cpm1_gpio16_set(mm_gc, pin_mask, val);
610 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
615 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
617 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
618 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
619 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
621 u16 pin_mask = 1 << (15 - gpio);
623 spin_lock_irqsave(&cpm1_gc->lock, flags);
625 clrbits16(&iop->dir, pin_mask);
627 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
632 int cpm1_gpiochip_add16(struct device *dev)
634 struct device_node *np = dev->of_node;
635 struct cpm1_gpio16_chip *cpm1_gc;
636 struct of_mm_gpio_chip *mm_gc;
637 struct gpio_chip *gc;
640 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
644 spin_lock_init(&cpm1_gc->lock);
646 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
649 for (i = 0, j = 0; i < 16; i++)
650 if (mask & (1 << (15 - i)))
651 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
654 mm_gc = &cpm1_gc->mm_gc;
657 mm_gc->save_regs = cpm1_gpio16_save_regs;
659 gc->direction_input = cpm1_gpio16_dir_in;
660 gc->direction_output = cpm1_gpio16_dir_out;
661 gc->get = cpm1_gpio16_get;
662 gc->set = cpm1_gpio16_set;
663 gc->to_irq = cpm1_gpio16_to_irq;
665 gc->owner = THIS_MODULE;
667 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
670 struct cpm1_gpio32_chip {
671 struct of_mm_gpio_chip mm_gc;
674 /* shadowed data register to clear/set bits safely */
678 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
680 struct cpm1_gpio32_chip *cpm1_gc =
681 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
682 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
684 cpm1_gc->cpdata = in_be32(&iop->dat);
687 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
689 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
690 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
693 pin_mask = 1 << (31 - gpio);
695 return !!(in_be32(&iop->dat) & pin_mask);
698 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
701 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
702 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
705 cpm1_gc->cpdata |= pin_mask;
707 cpm1_gc->cpdata &= ~pin_mask;
709 out_be32(&iop->dat, cpm1_gc->cpdata);
712 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
714 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
715 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
717 u32 pin_mask = 1 << (31 - gpio);
719 spin_lock_irqsave(&cpm1_gc->lock, flags);
721 __cpm1_gpio32_set(mm_gc, pin_mask, value);
723 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
726 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
728 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
729 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
730 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
732 u32 pin_mask = 1 << (31 - gpio);
734 spin_lock_irqsave(&cpm1_gc->lock, flags);
736 setbits32(&iop->dir, pin_mask);
737 __cpm1_gpio32_set(mm_gc, pin_mask, val);
739 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
744 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
746 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
747 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
748 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
750 u32 pin_mask = 1 << (31 - gpio);
752 spin_lock_irqsave(&cpm1_gc->lock, flags);
754 clrbits32(&iop->dir, pin_mask);
756 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
761 int cpm1_gpiochip_add32(struct device *dev)
763 struct device_node *np = dev->of_node;
764 struct cpm1_gpio32_chip *cpm1_gc;
765 struct of_mm_gpio_chip *mm_gc;
766 struct gpio_chip *gc;
768 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
772 spin_lock_init(&cpm1_gc->lock);
774 mm_gc = &cpm1_gc->mm_gc;
777 mm_gc->save_regs = cpm1_gpio32_save_regs;
779 gc->direction_input = cpm1_gpio32_dir_in;
780 gc->direction_output = cpm1_gpio32_dir_out;
781 gc->get = cpm1_gpio32_get;
782 gc->set = cpm1_gpio32_set;
784 gc->owner = THIS_MODULE;
786 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
789 #endif /* CONFIG_8xx_GPIO */