2 * Device driver for Microgate SyncLink GT serial adapters.
4 * written by Paul Fulghum for Microgate Corporation
7 * Microgate and SyncLink are trademarks of Microgate Corporation
9 * This code is released under the GNU General Public License (GPL)
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
25 * DEBUG OUTPUT DEFINITIONS
27 * uncomment lines below to enable specific types of debug output
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
79 #include <asm/types.h>
80 #include <asm/uaccess.h>
82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83 #define SYNCLINK_GENERIC_HDLC 1
85 #define SYNCLINK_GENERIC_HDLC 0
89 * module identification
91 static char *driver_name = "SyncLink GT";
92 static char *slgt_driver_name = "synclink_gt";
93 static char *tty_dev_prefix = "ttySLG";
94 MODULE_LICENSE("GPL");
95 #define MGSL_MAGIC 0x5401
96 #define MAX_DEVICES 32
98 static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
105 MODULE_DEVICE_TABLE(pci, pci_table);
107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
113 .remove = remove_one,
116 static bool pci_registered;
119 * module configuration and status
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
137 * tty support and callbacks
139 static struct tty_driver *serial_driver;
141 static int open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
163 * generic HDLC support and callbacks
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
175 * device specific structures, macros and functions
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE 256
182 * conditional wait facility
185 struct cond_wait *next;
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
196 * DMA buffer descriptor and access macros
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
225 struct _input_signal_events {
237 * device instance data structure
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
243 struct slgt_info *next_device; /* device list link */
247 char device_name[25];
248 struct pci_dev *pdev;
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
257 int line; /* tty line instance number */
259 struct mgsl_icount icount;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
276 struct work_struct task;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
285 /* device configuration */
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
293 bool reg_addr_requested;
295 MGSL_PARAMS params; /* communications parameters */
297 u32 max_frame_size; /* as set by device config */
299 unsigned int rbuf_fill_level;
301 unsigned int if_mode;
302 unsigned int base_clock;
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
317 unsigned char *tx_buf;
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
347 /* SPPP/Cisco HDLC device parts */
351 #if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
357 static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
370 .parity = ASYNC_PARITY_NONE
375 #define BH_TRANSMIT 2
377 #define IO_PIN_SHUTDOWN_LIMIT 100
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
382 #define MASK_PARITY BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK BIT14
385 #define MASK_OVERRUN BIT4
387 #define GSR 0x00 /* global status */
388 #define JCR 0x04 /* JTAG control */
389 #define IODR 0x08 /* GPIO direction */
390 #define IOER 0x0c /* GPIO interrupt enable */
391 #define IOVR 0x10 /* GPIO value */
392 #define IOSR 0x14 /* GPIO interrupt status */
393 #define TDR 0x80 /* tx data */
394 #define RDR 0x80 /* rx data */
395 #define TCR 0x82 /* tx control */
396 #define TIR 0x84 /* tx idle */
397 #define TPR 0x85 /* tx preamble */
398 #define RCR 0x86 /* rx control */
399 #define VCR 0x88 /* V.24 control */
400 #define CCR 0x89 /* clock control */
401 #define BDR 0x8a /* baud divisor */
402 #define SCR 0x8c /* serial control */
403 #define SSR 0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408 #define XSR 0x40 /* extended sync pattern */
409 #define XCR 0x44 /* extended control */
412 #define RXBREAK BIT14
413 #define IRQ_TXDATA BIT13
414 #define IRQ_TXIDLE BIT12
415 #define IRQ_TXUNDER BIT11 /* HDLC */
416 #define IRQ_RXDATA BIT10
417 #define IRQ_RXIDLE BIT9 /* HDLC */
418 #define IRQ_RXBREAK BIT9 /* async */
419 #define IRQ_RXOVER BIT8
424 #define IRQ_ALL 0x3ff0
425 #define IRQ_MASTER BIT0
427 #define slgt_irq_on(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 #define slgt_irq_off(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
432 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
433 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
439 static void msc_set_vcr(struct slgt_info *info);
441 static int startup(struct slgt_info *info);
442 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443 static void shutdown(struct slgt_info *info);
444 static void program_hw(struct slgt_info *info);
445 static void change_params(struct slgt_info *info);
447 static int register_test(struct slgt_info *info);
448 static int irq_test(struct slgt_info *info);
449 static int loopback_test(struct slgt_info *info);
450 static int adapter_test(struct slgt_info *info);
452 static void reset_adapter(struct slgt_info *info);
453 static void reset_port(struct slgt_info *info);
454 static void async_mode(struct slgt_info *info);
455 static void sync_mode(struct slgt_info *info);
457 static void rx_stop(struct slgt_info *info);
458 static void rx_start(struct slgt_info *info);
459 static void reset_rbufs(struct slgt_info *info);
460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461 static void rdma_reset(struct slgt_info *info);
462 static bool rx_get_frame(struct slgt_info *info);
463 static bool rx_get_buf(struct slgt_info *info);
465 static void tx_start(struct slgt_info *info);
466 static void tx_stop(struct slgt_info *info);
467 static void tx_set_idle(struct slgt_info *info);
468 static unsigned int free_tbuf_count(struct slgt_info *info);
469 static unsigned int tbuf_bytes(struct slgt_info *info);
470 static void reset_tbufs(struct slgt_info *info);
471 static void tdma_reset(struct slgt_info *info);
472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
474 static void get_signals(struct slgt_info *info);
475 static void set_signals(struct slgt_info *info);
476 static void enable_loopback(struct slgt_info *info);
477 static void set_rate(struct slgt_info *info, u32 data_rate);
479 static int bh_action(struct slgt_info *info);
480 static void bh_handler(struct work_struct *work);
481 static void bh_transmit(struct slgt_info *info);
482 static void isr_serial(struct slgt_info *info);
483 static void isr_rdma(struct slgt_info *info);
484 static void isr_txeom(struct slgt_info *info, unsigned short status);
485 static void isr_tdma(struct slgt_info *info);
487 static int alloc_dma_bufs(struct slgt_info *info);
488 static void free_dma_bufs(struct slgt_info *info);
489 static int alloc_desc(struct slgt_info *info);
490 static void free_desc(struct slgt_info *info);
491 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
494 static int alloc_tmp_rbuf(struct slgt_info *info);
495 static void free_tmp_rbuf(struct slgt_info *info);
497 static void tx_timeout(unsigned long context);
498 static void rx_timeout(unsigned long context);
503 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
507 static int set_txidle(struct slgt_info *info, int idle_mode);
508 static int tx_enable(struct slgt_info *info, int enable);
509 static int tx_abort(struct slgt_info *info);
510 static int rx_enable(struct slgt_info *info, int enable);
511 static int modem_input_wait(struct slgt_info *info,int arg);
512 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513 static int tiocmget(struct tty_struct *tty);
514 static int tiocmset(struct tty_struct *tty,
515 unsigned int set, unsigned int clear);
516 static int set_break(struct tty_struct *tty, int break_state);
517 static int get_interface(struct slgt_info *info, int __user *if_mode);
518 static int set_interface(struct slgt_info *info, int if_mode);
519 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int get_xsync(struct slgt_info *info, int __user *if_mode);
523 static int set_xsync(struct slgt_info *info, int if_mode);
524 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
525 static int set_xctrl(struct slgt_info *info, int if_mode);
530 static void add_device(struct slgt_info *info);
531 static void device_init(int adapter_num, struct pci_dev *pdev);
532 static int claim_resources(struct slgt_info *info);
533 static void release_resources(struct slgt_info *info);
552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
556 printk("%s %s data:\n",info->device_name, label);
558 linecount = (count > 16) ? 16 : count;
559 for(i=0; i < linecount; i++)
560 printk("%02X ",(unsigned char)data[i]);
563 for(i=0;i<linecount;i++) {
564 if (data[i]>=040 && data[i]<=0176)
565 printk("%c",data[i]);
575 #define DBGDATA(info, buf, size, label)
579 static void dump_tbufs(struct slgt_info *info)
582 printk("tbuf_current=%d\n", info->tbuf_current);
583 for (i=0 ; i < info->tbuf_count ; i++) {
584 printk("%d: count=%04X status=%04X\n",
585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
589 #define DBGTBUF(info)
593 static void dump_rbufs(struct slgt_info *info)
596 printk("rbuf_current=%d\n", info->rbuf_current);
597 for (i=0 ; i < info->rbuf_count ; i++) {
598 printk("%d: count=%04X status=%04X\n",
599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
603 #define DBGRBUF(info)
606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
610 printk("null struct slgt_info for (%s) in %s\n", devname, name);
613 if (info->magic != MGSL_MAGIC) {
614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
625 * line discipline callback wrappers
627 * The wrappers maintain line discipline references
628 * while calling into the line discipline.
630 * ldisc_receive_buf - pass receive data to line discipline
632 static void ldisc_receive_buf(struct tty_struct *tty,
633 const __u8 *data, char *flags, int count)
635 struct tty_ldisc *ld;
638 ld = tty_ldisc_ref(tty);
640 if (ld->ops->receive_buf)
641 ld->ops->receive_buf(tty, data, flags, count);
648 static int open(struct tty_struct *tty, struct file *filp)
650 struct slgt_info *info;
655 if (line >= slgt_device_count) {
656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
660 info = slgt_device_list;
661 while(info && info->line != line)
662 info = info->next_device;
663 if (sanity_check(info, tty->name, "open"))
665 if (info->init_error) {
666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
670 tty->driver_data = info;
671 info->port.tty = tty;
673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
675 mutex_lock(&info->port.mutex);
676 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
678 spin_lock_irqsave(&info->netlock, flags);
679 if (info->netcount) {
681 spin_unlock_irqrestore(&info->netlock, flags);
682 mutex_unlock(&info->port.mutex);
686 spin_unlock_irqrestore(&info->netlock, flags);
688 if (info->port.count == 1) {
689 /* 1st open on this device, init hardware */
690 retval = startup(info);
692 mutex_unlock(&info->port.mutex);
696 mutex_unlock(&info->port.mutex);
697 retval = block_til_ready(tty, filp, info);
699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
708 info->port.tty = NULL; /* tty layer will release tty struct */
713 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
717 static void close(struct tty_struct *tty, struct file *filp)
719 struct slgt_info *info = tty->driver_data;
721 if (sanity_check(info, tty->name, "close"))
723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
725 if (tty_port_close_start(&info->port, tty, filp) == 0)
728 mutex_lock(&info->port.mutex);
729 if (tty_port_initialized(&info->port))
730 wait_until_sent(tty, info->timeout);
732 tty_ldisc_flush(tty);
735 mutex_unlock(&info->port.mutex);
737 tty_port_close_end(&info->port, tty);
738 info->port.tty = NULL;
740 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
743 static void hangup(struct tty_struct *tty)
745 struct slgt_info *info = tty->driver_data;
748 if (sanity_check(info, tty->name, "hangup"))
750 DBGINFO(("%s hangup\n", info->device_name));
754 mutex_lock(&info->port.mutex);
757 spin_lock_irqsave(&info->port.lock, flags);
758 info->port.count = 0;
759 info->port.tty = NULL;
760 spin_unlock_irqrestore(&info->port.lock, flags);
761 tty_port_set_active(&info->port, 0);
762 mutex_unlock(&info->port.mutex);
764 wake_up_interruptible(&info->port.open_wait);
767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
769 struct slgt_info *info = tty->driver_data;
772 DBGINFO(("%s set_termios\n", tty->driver->name));
776 /* Handle transition to B0 status */
777 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
778 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
779 spin_lock_irqsave(&info->lock,flags);
781 spin_unlock_irqrestore(&info->lock,flags);
784 /* Handle transition away from B0 status */
785 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
786 info->signals |= SerialSignal_DTR;
787 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
788 info->signals |= SerialSignal_RTS;
789 spin_lock_irqsave(&info->lock,flags);
791 spin_unlock_irqrestore(&info->lock,flags);
794 /* Handle turning off CRTSCTS */
795 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
801 static void update_tx_timer(struct slgt_info *info)
804 * use worst case speed of 1200bps to calculate transmit timeout
805 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
807 if (info->params.mode == MGSL_MODE_HDLC) {
808 int timeout = (tbuf_bytes(info) * 7) + 1000;
809 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
813 static int write(struct tty_struct *tty,
814 const unsigned char *buf, int count)
817 struct slgt_info *info = tty->driver_data;
820 if (sanity_check(info, tty->name, "write"))
823 DBGINFO(("%s write count=%d\n", info->device_name, count));
825 if (!info->tx_buf || (count > info->max_frame_size))
828 if (!count || tty->stopped || tty->hw_stopped)
831 spin_lock_irqsave(&info->lock, flags);
833 if (info->tx_count) {
834 /* send accumulated data from send_char() */
835 if (!tx_load(info, info->tx_buf, info->tx_count))
840 if (tx_load(info, buf, count))
844 spin_unlock_irqrestore(&info->lock, flags);
845 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
849 static int put_char(struct tty_struct *tty, unsigned char ch)
851 struct slgt_info *info = tty->driver_data;
855 if (sanity_check(info, tty->name, "put_char"))
857 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
860 spin_lock_irqsave(&info->lock,flags);
861 if (info->tx_count < info->max_frame_size) {
862 info->tx_buf[info->tx_count++] = ch;
865 spin_unlock_irqrestore(&info->lock,flags);
869 static void send_xchar(struct tty_struct *tty, char ch)
871 struct slgt_info *info = tty->driver_data;
874 if (sanity_check(info, tty->name, "send_xchar"))
876 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
879 spin_lock_irqsave(&info->lock,flags);
880 if (!info->tx_enabled)
882 spin_unlock_irqrestore(&info->lock,flags);
886 static void wait_until_sent(struct tty_struct *tty, int timeout)
888 struct slgt_info *info = tty->driver_data;
889 unsigned long orig_jiffies, char_time;
893 if (sanity_check(info, tty->name, "wait_until_sent"))
895 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
896 if (!tty_port_initialized(&info->port))
899 orig_jiffies = jiffies;
901 /* Set check interval to 1/5 of estimated time to
902 * send a character, and make it at least 1. The check
903 * interval should also be less than the timeout.
904 * Note: use tight timings here to satisfy the NIST-PCTS.
907 if (info->params.data_rate) {
908 char_time = info->timeout/(32 * 5);
915 char_time = min_t(unsigned long, char_time, timeout);
917 while (info->tx_active) {
918 msleep_interruptible(jiffies_to_msecs(char_time));
919 if (signal_pending(current))
921 if (timeout && time_after(jiffies, orig_jiffies + timeout))
925 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
928 static int write_room(struct tty_struct *tty)
930 struct slgt_info *info = tty->driver_data;
933 if (sanity_check(info, tty->name, "write_room"))
935 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
936 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
940 static void flush_chars(struct tty_struct *tty)
942 struct slgt_info *info = tty->driver_data;
945 if (sanity_check(info, tty->name, "flush_chars"))
947 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
949 if (info->tx_count <= 0 || tty->stopped ||
950 tty->hw_stopped || !info->tx_buf)
953 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
955 spin_lock_irqsave(&info->lock,flags);
956 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
958 spin_unlock_irqrestore(&info->lock,flags);
961 static void flush_buffer(struct tty_struct *tty)
963 struct slgt_info *info = tty->driver_data;
966 if (sanity_check(info, tty->name, "flush_buffer"))
968 DBGINFO(("%s flush_buffer\n", info->device_name));
970 spin_lock_irqsave(&info->lock, flags);
972 spin_unlock_irqrestore(&info->lock, flags);
978 * throttle (stop) transmitter
980 static void tx_hold(struct tty_struct *tty)
982 struct slgt_info *info = tty->driver_data;
985 if (sanity_check(info, tty->name, "tx_hold"))
987 DBGINFO(("%s tx_hold\n", info->device_name));
988 spin_lock_irqsave(&info->lock,flags);
989 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
991 spin_unlock_irqrestore(&info->lock,flags);
995 * release (start) transmitter
997 static void tx_release(struct tty_struct *tty)
999 struct slgt_info *info = tty->driver_data;
1000 unsigned long flags;
1002 if (sanity_check(info, tty->name, "tx_release"))
1004 DBGINFO(("%s tx_release\n", info->device_name));
1005 spin_lock_irqsave(&info->lock, flags);
1006 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1008 spin_unlock_irqrestore(&info->lock, flags);
1012 * Service an IOCTL request
1016 * tty pointer to tty instance data
1017 * cmd IOCTL command code
1018 * arg command argument/context
1020 * Return 0 if success, otherwise error code
1022 static int ioctl(struct tty_struct *tty,
1023 unsigned int cmd, unsigned long arg)
1025 struct slgt_info *info = tty->driver_data;
1026 void __user *argp = (void __user *)arg;
1029 if (sanity_check(info, tty->name, "ioctl"))
1031 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1033 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1034 (cmd != TIOCMIWAIT)) {
1035 if (tty_io_error(tty))
1040 case MGSL_IOCWAITEVENT:
1041 return wait_mgsl_event(info, argp);
1043 return modem_input_wait(info,(int)arg);
1045 return set_gpio(info, argp);
1047 return get_gpio(info, argp);
1048 case MGSL_IOCWAITGPIO:
1049 return wait_gpio(info, argp);
1050 case MGSL_IOCGXSYNC:
1051 return get_xsync(info, argp);
1052 case MGSL_IOCSXSYNC:
1053 return set_xsync(info, (int)arg);
1054 case MGSL_IOCGXCTRL:
1055 return get_xctrl(info, argp);
1056 case MGSL_IOCSXCTRL:
1057 return set_xctrl(info, (int)arg);
1059 mutex_lock(&info->port.mutex);
1061 case MGSL_IOCGPARAMS:
1062 ret = get_params(info, argp);
1064 case MGSL_IOCSPARAMS:
1065 ret = set_params(info, argp);
1067 case MGSL_IOCGTXIDLE:
1068 ret = get_txidle(info, argp);
1070 case MGSL_IOCSTXIDLE:
1071 ret = set_txidle(info, (int)arg);
1073 case MGSL_IOCTXENABLE:
1074 ret = tx_enable(info, (int)arg);
1076 case MGSL_IOCRXENABLE:
1077 ret = rx_enable(info, (int)arg);
1079 case MGSL_IOCTXABORT:
1080 ret = tx_abort(info);
1082 case MGSL_IOCGSTATS:
1083 ret = get_stats(info, argp);
1086 ret = get_interface(info, argp);
1089 ret = set_interface(info,(int)arg);
1094 mutex_unlock(&info->port.mutex);
1098 static int get_icount(struct tty_struct *tty,
1099 struct serial_icounter_struct *icount)
1102 struct slgt_info *info = tty->driver_data;
1103 struct mgsl_icount cnow; /* kernel counter temps */
1104 unsigned long flags;
1106 spin_lock_irqsave(&info->lock,flags);
1107 cnow = info->icount;
1108 spin_unlock_irqrestore(&info->lock,flags);
1110 icount->cts = cnow.cts;
1111 icount->dsr = cnow.dsr;
1112 icount->rng = cnow.rng;
1113 icount->dcd = cnow.dcd;
1114 icount->rx = cnow.rx;
1115 icount->tx = cnow.tx;
1116 icount->frame = cnow.frame;
1117 icount->overrun = cnow.overrun;
1118 icount->parity = cnow.parity;
1119 icount->brk = cnow.brk;
1120 icount->buf_overrun = cnow.buf_overrun;
1126 * support for 32 bit ioctl calls on 64 bit systems
1128 #ifdef CONFIG_COMPAT
1129 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1131 struct MGSL_PARAMS32 tmp_params;
1133 DBGINFO(("%s get_params32\n", info->device_name));
1134 memset(&tmp_params, 0, sizeof(tmp_params));
1135 tmp_params.mode = (compat_ulong_t)info->params.mode;
1136 tmp_params.loopback = info->params.loopback;
1137 tmp_params.flags = info->params.flags;
1138 tmp_params.encoding = info->params.encoding;
1139 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1140 tmp_params.addr_filter = info->params.addr_filter;
1141 tmp_params.crc_type = info->params.crc_type;
1142 tmp_params.preamble_length = info->params.preamble_length;
1143 tmp_params.preamble = info->params.preamble;
1144 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1145 tmp_params.data_bits = info->params.data_bits;
1146 tmp_params.stop_bits = info->params.stop_bits;
1147 tmp_params.parity = info->params.parity;
1148 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1155 struct MGSL_PARAMS32 tmp_params;
1157 DBGINFO(("%s set_params32\n", info->device_name));
1158 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1161 spin_lock(&info->lock);
1162 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163 info->base_clock = tmp_params.clock_speed;
1165 info->params.mode = tmp_params.mode;
1166 info->params.loopback = tmp_params.loopback;
1167 info->params.flags = tmp_params.flags;
1168 info->params.encoding = tmp_params.encoding;
1169 info->params.clock_speed = tmp_params.clock_speed;
1170 info->params.addr_filter = tmp_params.addr_filter;
1171 info->params.crc_type = tmp_params.crc_type;
1172 info->params.preamble_length = tmp_params.preamble_length;
1173 info->params.preamble = tmp_params.preamble;
1174 info->params.data_rate = tmp_params.data_rate;
1175 info->params.data_bits = tmp_params.data_bits;
1176 info->params.stop_bits = tmp_params.stop_bits;
1177 info->params.parity = tmp_params.parity;
1179 spin_unlock(&info->lock);
1186 static long slgt_compat_ioctl(struct tty_struct *tty,
1187 unsigned int cmd, unsigned long arg)
1189 struct slgt_info *info = tty->driver_data;
1192 if (sanity_check(info, tty->name, "compat_ioctl"))
1194 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1197 case MGSL_IOCSPARAMS32:
1198 rc = set_params32(info, compat_ptr(arg));
1201 case MGSL_IOCGPARAMS32:
1202 rc = get_params32(info, compat_ptr(arg));
1205 case MGSL_IOCGPARAMS:
1206 case MGSL_IOCSPARAMS:
1207 case MGSL_IOCGTXIDLE:
1208 case MGSL_IOCGSTATS:
1209 case MGSL_IOCWAITEVENT:
1213 case MGSL_IOCWAITGPIO:
1214 case MGSL_IOCGXSYNC:
1215 case MGSL_IOCGXCTRL:
1216 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1219 rc = ioctl(tty, cmd, arg);
1221 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1225 #define slgt_compat_ioctl NULL
1226 #endif /* ifdef CONFIG_COMPAT */
1231 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1234 unsigned long flags;
1236 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1237 info->device_name, info->phys_reg_addr,
1238 info->irq_level, info->max_frame_size);
1240 /* output current serial signal states */
1241 spin_lock_irqsave(&info->lock,flags);
1243 spin_unlock_irqrestore(&info->lock,flags);
1247 if (info->signals & SerialSignal_RTS)
1248 strcat(stat_buf, "|RTS");
1249 if (info->signals & SerialSignal_CTS)
1250 strcat(stat_buf, "|CTS");
1251 if (info->signals & SerialSignal_DTR)
1252 strcat(stat_buf, "|DTR");
1253 if (info->signals & SerialSignal_DSR)
1254 strcat(stat_buf, "|DSR");
1255 if (info->signals & SerialSignal_DCD)
1256 strcat(stat_buf, "|CD");
1257 if (info->signals & SerialSignal_RI)
1258 strcat(stat_buf, "|RI");
1260 if (info->params.mode != MGSL_MODE_ASYNC) {
1261 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1262 info->icount.txok, info->icount.rxok);
1263 if (info->icount.txunder)
1264 seq_printf(m, " txunder:%d", info->icount.txunder);
1265 if (info->icount.txabort)
1266 seq_printf(m, " txabort:%d", info->icount.txabort);
1267 if (info->icount.rxshort)
1268 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1269 if (info->icount.rxlong)
1270 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1271 if (info->icount.rxover)
1272 seq_printf(m, " rxover:%d", info->icount.rxover);
1273 if (info->icount.rxcrc)
1274 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1276 seq_printf(m, "\tASYNC tx:%d rx:%d",
1277 info->icount.tx, info->icount.rx);
1278 if (info->icount.frame)
1279 seq_printf(m, " fe:%d", info->icount.frame);
1280 if (info->icount.parity)
1281 seq_printf(m, " pe:%d", info->icount.parity);
1282 if (info->icount.brk)
1283 seq_printf(m, " brk:%d", info->icount.brk);
1284 if (info->icount.overrun)
1285 seq_printf(m, " oe:%d", info->icount.overrun);
1288 /* Append serial signal status to end */
1289 seq_printf(m, " %s\n", stat_buf+1);
1291 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1292 info->tx_active,info->bh_requested,info->bh_running,
1296 /* Called to print information about devices
1298 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1300 struct slgt_info *info;
1302 seq_puts(m, "synclink_gt driver\n");
1304 info = slgt_device_list;
1307 info = info->next_device;
1312 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1314 return single_open(file, synclink_gt_proc_show, NULL);
1317 static const struct file_operations synclink_gt_proc_fops = {
1318 .owner = THIS_MODULE,
1319 .open = synclink_gt_proc_open,
1321 .llseek = seq_lseek,
1322 .release = single_release,
1326 * return count of bytes in transmit buffer
1328 static int chars_in_buffer(struct tty_struct *tty)
1330 struct slgt_info *info = tty->driver_data;
1332 if (sanity_check(info, tty->name, "chars_in_buffer"))
1334 count = tbuf_bytes(info);
1335 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1340 * signal remote device to throttle send data (our receive data)
1342 static void throttle(struct tty_struct * tty)
1344 struct slgt_info *info = tty->driver_data;
1345 unsigned long flags;
1347 if (sanity_check(info, tty->name, "throttle"))
1349 DBGINFO(("%s throttle\n", info->device_name));
1351 send_xchar(tty, STOP_CHAR(tty));
1352 if (C_CRTSCTS(tty)) {
1353 spin_lock_irqsave(&info->lock,flags);
1354 info->signals &= ~SerialSignal_RTS;
1356 spin_unlock_irqrestore(&info->lock,flags);
1361 * signal remote device to stop throttling send data (our receive data)
1363 static void unthrottle(struct tty_struct * tty)
1365 struct slgt_info *info = tty->driver_data;
1366 unsigned long flags;
1368 if (sanity_check(info, tty->name, "unthrottle"))
1370 DBGINFO(("%s unthrottle\n", info->device_name));
1375 send_xchar(tty, START_CHAR(tty));
1377 if (C_CRTSCTS(tty)) {
1378 spin_lock_irqsave(&info->lock,flags);
1379 info->signals |= SerialSignal_RTS;
1381 spin_unlock_irqrestore(&info->lock,flags);
1386 * set or clear transmit break condition
1387 * break_state -1=set break condition, 0=clear
1389 static int set_break(struct tty_struct *tty, int break_state)
1391 struct slgt_info *info = tty->driver_data;
1392 unsigned short value;
1393 unsigned long flags;
1395 if (sanity_check(info, tty->name, "set_break"))
1397 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1399 spin_lock_irqsave(&info->lock,flags);
1400 value = rd_reg16(info, TCR);
1401 if (break_state == -1)
1405 wr_reg16(info, TCR, value);
1406 spin_unlock_irqrestore(&info->lock,flags);
1410 #if SYNCLINK_GENERIC_HDLC
1413 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1414 * set encoding and frame check sequence (FCS) options
1416 * dev pointer to network device structure
1417 * encoding serial encoding setting
1418 * parity FCS setting
1420 * returns 0 if success, otherwise error code
1422 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1423 unsigned short parity)
1425 struct slgt_info *info = dev_to_port(dev);
1426 unsigned char new_encoding;
1427 unsigned short new_crctype;
1429 /* return error if TTY interface open */
1430 if (info->port.count)
1433 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1437 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1438 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1439 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1440 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1441 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1442 default: return -EINVAL;
1447 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1448 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1449 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1450 default: return -EINVAL;
1453 info->params.encoding = new_encoding;
1454 info->params.crc_type = new_crctype;
1456 /* if network interface up, reprogram hardware */
1464 * called by generic HDLC layer to send frame
1466 * skb socket buffer containing HDLC frame
1467 * dev pointer to network device structure
1469 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1470 struct net_device *dev)
1472 struct slgt_info *info = dev_to_port(dev);
1473 unsigned long flags;
1475 DBGINFO(("%s hdlc_xmit\n", dev->name));
1478 return NETDEV_TX_OK;
1480 /* stop sending until this frame completes */
1481 netif_stop_queue(dev);
1483 /* update network statistics */
1484 dev->stats.tx_packets++;
1485 dev->stats.tx_bytes += skb->len;
1487 /* save start time for transmit timeout detection */
1488 netif_trans_update(dev);
1490 spin_lock_irqsave(&info->lock, flags);
1491 tx_load(info, skb->data, skb->len);
1492 spin_unlock_irqrestore(&info->lock, flags);
1494 /* done with socket buffer, so free it */
1497 return NETDEV_TX_OK;
1501 * called by network layer when interface enabled
1502 * claim resources and initialize hardware
1504 * dev pointer to network device structure
1506 * returns 0 if success, otherwise error code
1508 static int hdlcdev_open(struct net_device *dev)
1510 struct slgt_info *info = dev_to_port(dev);
1512 unsigned long flags;
1514 if (!try_module_get(THIS_MODULE))
1517 DBGINFO(("%s hdlcdev_open\n", dev->name));
1519 /* generic HDLC layer open processing */
1520 rc = hdlc_open(dev);
1524 /* arbitrate between network and tty opens */
1525 spin_lock_irqsave(&info->netlock, flags);
1526 if (info->port.count != 0 || info->netcount != 0) {
1527 DBGINFO(("%s hdlc_open busy\n", dev->name));
1528 spin_unlock_irqrestore(&info->netlock, flags);
1532 spin_unlock_irqrestore(&info->netlock, flags);
1534 /* claim resources and init adapter */
1535 if ((rc = startup(info)) != 0) {
1536 spin_lock_irqsave(&info->netlock, flags);
1538 spin_unlock_irqrestore(&info->netlock, flags);
1542 /* assert RTS and DTR, apply hardware settings */
1543 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1546 /* enable network layer transmit */
1547 netif_trans_update(dev);
1548 netif_start_queue(dev);
1550 /* inform generic HDLC layer of current DCD status */
1551 spin_lock_irqsave(&info->lock, flags);
1553 spin_unlock_irqrestore(&info->lock, flags);
1554 if (info->signals & SerialSignal_DCD)
1555 netif_carrier_on(dev);
1557 netif_carrier_off(dev);
1562 * called by network layer when interface is disabled
1563 * shutdown hardware and release resources
1565 * dev pointer to network device structure
1567 * returns 0 if success, otherwise error code
1569 static int hdlcdev_close(struct net_device *dev)
1571 struct slgt_info *info = dev_to_port(dev);
1572 unsigned long flags;
1574 DBGINFO(("%s hdlcdev_close\n", dev->name));
1576 netif_stop_queue(dev);
1578 /* shutdown adapter and release resources */
1583 spin_lock_irqsave(&info->netlock, flags);
1585 spin_unlock_irqrestore(&info->netlock, flags);
1587 module_put(THIS_MODULE);
1592 * called by network layer to process IOCTL call to network device
1594 * dev pointer to network device structure
1595 * ifr pointer to network interface request structure
1596 * cmd IOCTL command code
1598 * returns 0 if success, otherwise error code
1600 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1602 const size_t size = sizeof(sync_serial_settings);
1603 sync_serial_settings new_line;
1604 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1605 struct slgt_info *info = dev_to_port(dev);
1608 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1610 /* return error if TTY interface open */
1611 if (info->port.count)
1614 if (cmd != SIOCWANDEV)
1615 return hdlc_ioctl(dev, ifr, cmd);
1617 memset(&new_line, 0, sizeof(new_line));
1619 switch(ifr->ifr_settings.type) {
1620 case IF_GET_IFACE: /* return current sync_serial_settings */
1622 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1623 if (ifr->ifr_settings.size < size) {
1624 ifr->ifr_settings.size = size; /* data size wanted */
1628 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1629 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1630 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1631 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1634 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1635 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1636 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1637 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1638 default: new_line.clock_type = CLOCK_DEFAULT;
1641 new_line.clock_rate = info->params.clock_speed;
1642 new_line.loopback = info->params.loopback ? 1:0;
1644 if (copy_to_user(line, &new_line, size))
1648 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1650 if(!capable(CAP_NET_ADMIN))
1652 if (copy_from_user(&new_line, line, size))
1655 switch (new_line.clock_type)
1657 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1658 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1659 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1660 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1661 case CLOCK_DEFAULT: flags = info->params.flags &
1662 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1663 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1664 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1665 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1666 default: return -EINVAL;
1669 if (new_line.loopback != 0 && new_line.loopback != 1)
1672 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1673 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1674 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1675 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1676 info->params.flags |= flags;
1678 info->params.loopback = new_line.loopback;
1680 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1681 info->params.clock_speed = new_line.clock_rate;
1683 info->params.clock_speed = 0;
1685 /* if network interface up, reprogram hardware */
1691 return hdlc_ioctl(dev, ifr, cmd);
1696 * called by network layer when transmit timeout is detected
1698 * dev pointer to network device structure
1700 static void hdlcdev_tx_timeout(struct net_device *dev)
1702 struct slgt_info *info = dev_to_port(dev);
1703 unsigned long flags;
1705 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1707 dev->stats.tx_errors++;
1708 dev->stats.tx_aborted_errors++;
1710 spin_lock_irqsave(&info->lock,flags);
1712 spin_unlock_irqrestore(&info->lock,flags);
1714 netif_wake_queue(dev);
1718 * called by device driver when transmit completes
1719 * reenable network layer transmit if stopped
1721 * info pointer to device instance information
1723 static void hdlcdev_tx_done(struct slgt_info *info)
1725 if (netif_queue_stopped(info->netdev))
1726 netif_wake_queue(info->netdev);
1730 * called by device driver when frame received
1731 * pass frame to network layer
1733 * info pointer to device instance information
1734 * buf pointer to buffer contianing frame data
1735 * size count of data bytes in buf
1737 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1739 struct sk_buff *skb = dev_alloc_skb(size);
1740 struct net_device *dev = info->netdev;
1742 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1745 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1746 dev->stats.rx_dropped++;
1750 memcpy(skb_put(skb, size), buf, size);
1752 skb->protocol = hdlc_type_trans(skb, dev);
1754 dev->stats.rx_packets++;
1755 dev->stats.rx_bytes += size;
1760 static const struct net_device_ops hdlcdev_ops = {
1761 .ndo_open = hdlcdev_open,
1762 .ndo_stop = hdlcdev_close,
1763 .ndo_change_mtu = hdlc_change_mtu,
1764 .ndo_start_xmit = hdlc_start_xmit,
1765 .ndo_do_ioctl = hdlcdev_ioctl,
1766 .ndo_tx_timeout = hdlcdev_tx_timeout,
1770 * called by device driver when adding device instance
1771 * do generic HDLC initialization
1773 * info pointer to device instance information
1775 * returns 0 if success, otherwise error code
1777 static int hdlcdev_init(struct slgt_info *info)
1780 struct net_device *dev;
1783 /* allocate and initialize network and HDLC layer objects */
1785 dev = alloc_hdlcdev(info);
1787 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1791 /* for network layer reporting purposes only */
1792 dev->mem_start = info->phys_reg_addr;
1793 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1794 dev->irq = info->irq_level;
1796 /* network layer callbacks and settings */
1797 dev->netdev_ops = &hdlcdev_ops;
1798 dev->watchdog_timeo = 10 * HZ;
1799 dev->tx_queue_len = 50;
1801 /* generic HDLC layer callbacks and settings */
1802 hdlc = dev_to_hdlc(dev);
1803 hdlc->attach = hdlcdev_attach;
1804 hdlc->xmit = hdlcdev_xmit;
1806 /* register objects with HDLC layer */
1807 rc = register_hdlc_device(dev);
1809 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1819 * called by device driver when removing device instance
1820 * do generic HDLC cleanup
1822 * info pointer to device instance information
1824 static void hdlcdev_exit(struct slgt_info *info)
1828 unregister_hdlc_device(info->netdev);
1829 free_netdev(info->netdev);
1830 info->netdev = NULL;
1833 #endif /* ifdef CONFIG_HDLC */
1836 * get async data from rx DMA buffers
1838 static void rx_async(struct slgt_info *info)
1840 struct mgsl_icount *icount = &info->icount;
1841 unsigned int start, end;
1843 unsigned char status;
1844 struct slgt_desc *bufs = info->rbufs;
1850 start = end = info->rbuf_current;
1852 while(desc_complete(bufs[end])) {
1853 count = desc_count(bufs[end]) - info->rbuf_index;
1854 p = bufs[end].buf + info->rbuf_index;
1856 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1857 DBGDATA(info, p, count, "rx");
1859 for(i=0 ; i < count; i+=2, p+=2) {
1865 status = *(p + 1) & (BIT1 + BIT0);
1869 else if (status & BIT0)
1871 /* discard char if tty control flags say so */
1872 if (status & info->ignore_status_mask)
1876 else if (status & BIT0)
1879 tty_insert_flip_char(&info->port, ch, stat);
1884 /* receive buffer not completed */
1885 info->rbuf_index += i;
1886 mod_timer(&info->rx_timer, jiffies + 1);
1890 info->rbuf_index = 0;
1891 free_rbufs(info, end, end);
1893 if (++end == info->rbuf_count)
1896 /* if entire list searched then no frame available */
1902 tty_flip_buffer_push(&info->port);
1906 * return next bottom half action to perform
1908 static int bh_action(struct slgt_info *info)
1910 unsigned long flags;
1913 spin_lock_irqsave(&info->lock,flags);
1915 if (info->pending_bh & BH_RECEIVE) {
1916 info->pending_bh &= ~BH_RECEIVE;
1918 } else if (info->pending_bh & BH_TRANSMIT) {
1919 info->pending_bh &= ~BH_TRANSMIT;
1921 } else if (info->pending_bh & BH_STATUS) {
1922 info->pending_bh &= ~BH_STATUS;
1925 /* Mark BH routine as complete */
1926 info->bh_running = false;
1927 info->bh_requested = false;
1931 spin_unlock_irqrestore(&info->lock,flags);
1937 * perform bottom half processing
1939 static void bh_handler(struct work_struct *work)
1941 struct slgt_info *info = container_of(work, struct slgt_info, task);
1944 info->bh_running = true;
1946 while((action = bh_action(info))) {
1949 DBGBH(("%s bh receive\n", info->device_name));
1950 switch(info->params.mode) {
1951 case MGSL_MODE_ASYNC:
1954 case MGSL_MODE_HDLC:
1955 while(rx_get_frame(info));
1958 case MGSL_MODE_MONOSYNC:
1959 case MGSL_MODE_BISYNC:
1960 case MGSL_MODE_XSYNC:
1961 while(rx_get_buf(info));
1964 /* restart receiver if rx DMA buffers exhausted */
1965 if (info->rx_restart)
1972 DBGBH(("%s bh status\n", info->device_name));
1973 info->ri_chkcount = 0;
1974 info->dsr_chkcount = 0;
1975 info->dcd_chkcount = 0;
1976 info->cts_chkcount = 0;
1979 DBGBH(("%s unknown action\n", info->device_name));
1983 DBGBH(("%s bh_handler exit\n", info->device_name));
1986 static void bh_transmit(struct slgt_info *info)
1988 struct tty_struct *tty = info->port.tty;
1990 DBGBH(("%s bh_transmit\n", info->device_name));
1995 static void dsr_change(struct slgt_info *info, unsigned short status)
1997 if (status & BIT3) {
1998 info->signals |= SerialSignal_DSR;
1999 info->input_signal_events.dsr_up++;
2001 info->signals &= ~SerialSignal_DSR;
2002 info->input_signal_events.dsr_down++;
2004 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2005 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2006 slgt_irq_off(info, IRQ_DSR);
2010 wake_up_interruptible(&info->status_event_wait_q);
2011 wake_up_interruptible(&info->event_wait_q);
2012 info->pending_bh |= BH_STATUS;
2015 static void cts_change(struct slgt_info *info, unsigned short status)
2017 if (status & BIT2) {
2018 info->signals |= SerialSignal_CTS;
2019 info->input_signal_events.cts_up++;
2021 info->signals &= ~SerialSignal_CTS;
2022 info->input_signal_events.cts_down++;
2024 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2025 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2026 slgt_irq_off(info, IRQ_CTS);
2030 wake_up_interruptible(&info->status_event_wait_q);
2031 wake_up_interruptible(&info->event_wait_q);
2032 info->pending_bh |= BH_STATUS;
2034 if (tty_port_cts_enabled(&info->port)) {
2035 if (info->port.tty) {
2036 if (info->port.tty->hw_stopped) {
2037 if (info->signals & SerialSignal_CTS) {
2038 info->port.tty->hw_stopped = 0;
2039 info->pending_bh |= BH_TRANSMIT;
2043 if (!(info->signals & SerialSignal_CTS))
2044 info->port.tty->hw_stopped = 1;
2050 static void dcd_change(struct slgt_info *info, unsigned short status)
2052 if (status & BIT1) {
2053 info->signals |= SerialSignal_DCD;
2054 info->input_signal_events.dcd_up++;
2056 info->signals &= ~SerialSignal_DCD;
2057 info->input_signal_events.dcd_down++;
2059 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2060 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2061 slgt_irq_off(info, IRQ_DCD);
2065 #if SYNCLINK_GENERIC_HDLC
2066 if (info->netcount) {
2067 if (info->signals & SerialSignal_DCD)
2068 netif_carrier_on(info->netdev);
2070 netif_carrier_off(info->netdev);
2073 wake_up_interruptible(&info->status_event_wait_q);
2074 wake_up_interruptible(&info->event_wait_q);
2075 info->pending_bh |= BH_STATUS;
2077 if (tty_port_check_carrier(&info->port)) {
2078 if (info->signals & SerialSignal_DCD)
2079 wake_up_interruptible(&info->port.open_wait);
2082 tty_hangup(info->port.tty);
2087 static void ri_change(struct slgt_info *info, unsigned short status)
2089 if (status & BIT0) {
2090 info->signals |= SerialSignal_RI;
2091 info->input_signal_events.ri_up++;
2093 info->signals &= ~SerialSignal_RI;
2094 info->input_signal_events.ri_down++;
2096 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2097 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2098 slgt_irq_off(info, IRQ_RI);
2102 wake_up_interruptible(&info->status_event_wait_q);
2103 wake_up_interruptible(&info->event_wait_q);
2104 info->pending_bh |= BH_STATUS;
2107 static void isr_rxdata(struct slgt_info *info)
2109 unsigned int count = info->rbuf_fill_count;
2110 unsigned int i = info->rbuf_fill_index;
2113 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2114 reg = rd_reg16(info, RDR);
2115 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2116 if (desc_complete(info->rbufs[i])) {
2117 /* all buffers full */
2119 info->rx_restart = 1;
2122 info->rbufs[i].buf[count++] = (unsigned char)reg;
2123 /* async mode saves status byte to buffer for each data byte */
2124 if (info->params.mode == MGSL_MODE_ASYNC)
2125 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2126 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2127 /* buffer full or end of frame */
2128 set_desc_count(info->rbufs[i], count);
2129 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2130 info->rbuf_fill_count = count = 0;
2131 if (++i == info->rbuf_count)
2133 info->pending_bh |= BH_RECEIVE;
2137 info->rbuf_fill_index = i;
2138 info->rbuf_fill_count = count;
2141 static void isr_serial(struct slgt_info *info)
2143 unsigned short status = rd_reg16(info, SSR);
2145 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2147 wr_reg16(info, SSR, status); /* clear pending */
2149 info->irq_occurred = true;
2151 if (info->params.mode == MGSL_MODE_ASYNC) {
2152 if (status & IRQ_TXIDLE) {
2153 if (info->tx_active)
2154 isr_txeom(info, status);
2156 if (info->rx_pio && (status & IRQ_RXDATA))
2158 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2160 /* process break detection if tty control allows */
2161 if (info->port.tty) {
2162 if (!(status & info->ignore_status_mask)) {
2163 if (info->read_status_mask & MASK_BREAK) {
2164 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2165 if (info->port.flags & ASYNC_SAK)
2166 do_SAK(info->port.tty);
2172 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2173 isr_txeom(info, status);
2174 if (info->rx_pio && (status & IRQ_RXDATA))
2176 if (status & IRQ_RXIDLE) {
2177 if (status & RXIDLE)
2178 info->icount.rxidle++;
2180 info->icount.exithunt++;
2181 wake_up_interruptible(&info->event_wait_q);
2184 if (status & IRQ_RXOVER)
2188 if (status & IRQ_DSR)
2189 dsr_change(info, status);
2190 if (status & IRQ_CTS)
2191 cts_change(info, status);
2192 if (status & IRQ_DCD)
2193 dcd_change(info, status);
2194 if (status & IRQ_RI)
2195 ri_change(info, status);
2198 static void isr_rdma(struct slgt_info *info)
2200 unsigned int status = rd_reg32(info, RDCSR);
2202 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2204 /* RDCSR (rx DMA control/status)
2207 * 06 save status byte to DMA buffer
2209 * 04 eol (end of list)
2210 * 03 eob (end of buffer)
2215 wr_reg32(info, RDCSR, status); /* clear pending */
2217 if (status & (BIT5 + BIT4)) {
2218 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2219 info->rx_restart = true;
2221 info->pending_bh |= BH_RECEIVE;
2224 static void isr_tdma(struct slgt_info *info)
2226 unsigned int status = rd_reg32(info, TDCSR);
2228 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2230 /* TDCSR (tx DMA control/status)
2234 * 04 eol (end of list)
2235 * 03 eob (end of buffer)
2240 wr_reg32(info, TDCSR, status); /* clear pending */
2242 if (status & (BIT5 + BIT4 + BIT3)) {
2243 // another transmit buffer has completed
2244 // run bottom half to get more send data from user
2245 info->pending_bh |= BH_TRANSMIT;
2250 * return true if there are unsent tx DMA buffers, otherwise false
2252 * if there are unsent buffers then info->tbuf_start
2253 * is set to index of first unsent buffer
2255 static bool unsent_tbufs(struct slgt_info *info)
2257 unsigned int i = info->tbuf_current;
2261 * search backwards from last loaded buffer (precedes tbuf_current)
2262 * for first unsent buffer (desc_count > 0)
2269 i = info->tbuf_count - 1;
2270 if (!desc_count(info->tbufs[i]))
2272 info->tbuf_start = i;
2274 } while (i != info->tbuf_current);
2279 static void isr_txeom(struct slgt_info *info, unsigned short status)
2281 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2283 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2285 if (status & IRQ_TXUNDER) {
2286 unsigned short val = rd_reg16(info, TCR);
2287 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2288 wr_reg16(info, TCR, val); /* clear reset bit */
2291 if (info->tx_active) {
2292 if (info->params.mode != MGSL_MODE_ASYNC) {
2293 if (status & IRQ_TXUNDER)
2294 info->icount.txunder++;
2295 else if (status & IRQ_TXIDLE)
2296 info->icount.txok++;
2299 if (unsent_tbufs(info)) {
2301 update_tx_timer(info);
2304 info->tx_active = false;
2306 del_timer(&info->tx_timer);
2308 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2309 info->signals &= ~SerialSignal_RTS;
2310 info->drop_rts_on_tx_done = false;
2314 #if SYNCLINK_GENERIC_HDLC
2316 hdlcdev_tx_done(info);
2320 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2324 info->pending_bh |= BH_TRANSMIT;
2329 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2331 struct cond_wait *w, *prev;
2333 /* wake processes waiting for specific transitions */
2334 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2335 if (w->data & changed) {
2337 wake_up_interruptible(&w->q);
2339 prev->next = w->next;
2341 info->gpio_wait_q = w->next;
2347 /* interrupt service routine
2349 * irq interrupt number
2350 * dev_id device ID supplied during interrupt registration
2352 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2354 struct slgt_info *info = dev_id;
2358 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2360 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2361 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2362 info->irq_occurred = true;
2363 for(i=0; i < info->port_count ; i++) {
2364 if (info->port_array[i] == NULL)
2366 spin_lock(&info->port_array[i]->lock);
2367 if (gsr & (BIT8 << i))
2368 isr_serial(info->port_array[i]);
2369 if (gsr & (BIT16 << (i*2)))
2370 isr_rdma(info->port_array[i]);
2371 if (gsr & (BIT17 << (i*2)))
2372 isr_tdma(info->port_array[i]);
2373 spin_unlock(&info->port_array[i]->lock);
2377 if (info->gpio_present) {
2379 unsigned int changed;
2380 spin_lock(&info->lock);
2381 while ((changed = rd_reg32(info, IOSR)) != 0) {
2382 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2383 /* read latched state of GPIO signals */
2384 state = rd_reg32(info, IOVR);
2385 /* clear pending GPIO interrupt bits */
2386 wr_reg32(info, IOSR, changed);
2387 for (i=0 ; i < info->port_count ; i++) {
2388 if (info->port_array[i] != NULL)
2389 isr_gpio(info->port_array[i], changed, state);
2392 spin_unlock(&info->lock);
2395 for(i=0; i < info->port_count ; i++) {
2396 struct slgt_info *port = info->port_array[i];
2399 spin_lock(&port->lock);
2400 if ((port->port.count || port->netcount) &&
2401 port->pending_bh && !port->bh_running &&
2402 !port->bh_requested) {
2403 DBGISR(("%s bh queued\n", port->device_name));
2404 schedule_work(&port->task);
2405 port->bh_requested = true;
2407 spin_unlock(&port->lock);
2410 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2414 static int startup(struct slgt_info *info)
2416 DBGINFO(("%s startup\n", info->device_name));
2418 if (tty_port_initialized(&info->port))
2421 if (!info->tx_buf) {
2422 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2423 if (!info->tx_buf) {
2424 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2429 info->pending_bh = 0;
2431 memset(&info->icount, 0, sizeof(info->icount));
2433 /* program hardware for current parameters */
2434 change_params(info);
2437 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2439 tty_port_set_initialized(&info->port, 1);
2445 * called by close() and hangup() to shutdown hardware
2447 static void shutdown(struct slgt_info *info)
2449 unsigned long flags;
2451 if (!tty_port_initialized(&info->port))
2454 DBGINFO(("%s shutdown\n", info->device_name));
2456 /* clear status wait queue because status changes */
2457 /* can't happen after shutting down the hardware */
2458 wake_up_interruptible(&info->status_event_wait_q);
2459 wake_up_interruptible(&info->event_wait_q);
2461 del_timer_sync(&info->tx_timer);
2462 del_timer_sync(&info->rx_timer);
2464 kfree(info->tx_buf);
2465 info->tx_buf = NULL;
2467 spin_lock_irqsave(&info->lock,flags);
2472 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2474 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2475 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2479 flush_cond_wait(&info->gpio_wait_q);
2481 spin_unlock_irqrestore(&info->lock,flags);
2484 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2486 tty_port_set_initialized(&info->port, 0);
2489 static void program_hw(struct slgt_info *info)
2491 unsigned long flags;
2493 spin_lock_irqsave(&info->lock,flags);
2498 if (info->params.mode != MGSL_MODE_ASYNC ||
2506 info->dcd_chkcount = 0;
2507 info->cts_chkcount = 0;
2508 info->ri_chkcount = 0;
2509 info->dsr_chkcount = 0;
2511 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2514 if (info->netcount ||
2515 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2518 spin_unlock_irqrestore(&info->lock,flags);
2522 * reconfigure adapter based on new parameters
2524 static void change_params(struct slgt_info *info)
2529 if (!info->port.tty)
2531 DBGINFO(("%s change_params\n", info->device_name));
2533 cflag = info->port.tty->termios.c_cflag;
2535 /* if B0 rate (hangup) specified then negate RTS and DTR */
2536 /* otherwise assert RTS and DTR */
2538 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2540 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2542 /* byte size and parity */
2544 switch (cflag & CSIZE) {
2545 case CS5: info->params.data_bits = 5; break;
2546 case CS6: info->params.data_bits = 6; break;
2547 case CS7: info->params.data_bits = 7; break;
2548 case CS8: info->params.data_bits = 8; break;
2549 default: info->params.data_bits = 7; break;
2552 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2555 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2557 info->params.parity = ASYNC_PARITY_NONE;
2559 /* calculate number of jiffies to transmit a full
2560 * FIFO (32 bytes) at specified data rate
2562 bits_per_char = info->params.data_bits +
2563 info->params.stop_bits + 1;
2565 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2567 if (info->params.data_rate) {
2568 info->timeout = (32*HZ*bits_per_char) /
2569 info->params.data_rate;
2571 info->timeout += HZ/50; /* Add .02 seconds of slop */
2573 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2574 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2576 /* process tty input control flags */
2578 info->read_status_mask = IRQ_RXOVER;
2579 if (I_INPCK(info->port.tty))
2580 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2581 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2582 info->read_status_mask |= MASK_BREAK;
2583 if (I_IGNPAR(info->port.tty))
2584 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2585 if (I_IGNBRK(info->port.tty)) {
2586 info->ignore_status_mask |= MASK_BREAK;
2587 /* If ignoring parity and break indicators, ignore
2588 * overruns too. (For real raw support).
2590 if (I_IGNPAR(info->port.tty))
2591 info->ignore_status_mask |= MASK_OVERRUN;
2597 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2599 DBGINFO(("%s get_stats\n", info->device_name));
2601 memset(&info->icount, 0, sizeof(info->icount));
2603 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2609 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2611 DBGINFO(("%s get_params\n", info->device_name));
2612 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2617 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2619 unsigned long flags;
2620 MGSL_PARAMS tmp_params;
2622 DBGINFO(("%s set_params\n", info->device_name));
2623 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2626 spin_lock_irqsave(&info->lock, flags);
2627 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2628 info->base_clock = tmp_params.clock_speed;
2630 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2631 spin_unlock_irqrestore(&info->lock, flags);
2638 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2640 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2641 if (put_user(info->idle_mode, idle_mode))
2646 static int set_txidle(struct slgt_info *info, int idle_mode)
2648 unsigned long flags;
2649 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2650 spin_lock_irqsave(&info->lock,flags);
2651 info->idle_mode = idle_mode;
2652 if (info->params.mode != MGSL_MODE_ASYNC)
2654 spin_unlock_irqrestore(&info->lock,flags);
2658 static int tx_enable(struct slgt_info *info, int enable)
2660 unsigned long flags;
2661 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2662 spin_lock_irqsave(&info->lock,flags);
2664 if (!info->tx_enabled)
2667 if (info->tx_enabled)
2670 spin_unlock_irqrestore(&info->lock,flags);
2675 * abort transmit HDLC frame
2677 static int tx_abort(struct slgt_info *info)
2679 unsigned long flags;
2680 DBGINFO(("%s tx_abort\n", info->device_name));
2681 spin_lock_irqsave(&info->lock,flags);
2683 spin_unlock_irqrestore(&info->lock,flags);
2687 static int rx_enable(struct slgt_info *info, int enable)
2689 unsigned long flags;
2690 unsigned int rbuf_fill_level;
2691 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2692 spin_lock_irqsave(&info->lock,flags);
2694 * enable[31..16] = receive DMA buffer fill level
2695 * 0 = noop (leave fill level unchanged)
2696 * fill level must be multiple of 4 and <= buffer size
2698 rbuf_fill_level = ((unsigned int)enable) >> 16;
2699 if (rbuf_fill_level) {
2700 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2701 spin_unlock_irqrestore(&info->lock, flags);
2704 info->rbuf_fill_level = rbuf_fill_level;
2705 if (rbuf_fill_level < 128)
2706 info->rx_pio = 1; /* PIO mode */
2708 info->rx_pio = 0; /* DMA mode */
2709 rx_stop(info); /* restart receiver to use new fill level */
2713 * enable[1..0] = receiver enable command
2716 * 2 = enable or force hunt mode if already enabled
2720 if (!info->rx_enabled)
2722 else if (enable == 2) {
2723 /* force hunt mode (write 1 to RCR[3]) */
2724 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2727 if (info->rx_enabled)
2730 spin_unlock_irqrestore(&info->lock,flags);
2735 * wait for specified event to occur
2737 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2739 unsigned long flags;
2742 struct mgsl_icount cprev, cnow;
2745 struct _input_signal_events oldsigs, newsigs;
2746 DECLARE_WAITQUEUE(wait, current);
2748 if (get_user(mask, mask_ptr))
2751 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2753 spin_lock_irqsave(&info->lock,flags);
2755 /* return immediately if state matches requested events */
2760 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2761 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2762 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2763 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2765 spin_unlock_irqrestore(&info->lock,flags);
2769 /* save current irq counts */
2770 cprev = info->icount;
2771 oldsigs = info->input_signal_events;
2773 /* enable hunt and idle irqs if needed */
2774 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2775 unsigned short val = rd_reg16(info, SCR);
2776 if (!(val & IRQ_RXIDLE))
2777 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2780 set_current_state(TASK_INTERRUPTIBLE);
2781 add_wait_queue(&info->event_wait_q, &wait);
2783 spin_unlock_irqrestore(&info->lock,flags);
2787 if (signal_pending(current)) {
2792 /* get current irq counts */
2793 spin_lock_irqsave(&info->lock,flags);
2794 cnow = info->icount;
2795 newsigs = info->input_signal_events;
2796 set_current_state(TASK_INTERRUPTIBLE);
2797 spin_unlock_irqrestore(&info->lock,flags);
2799 /* if no change, wait aborted for some reason */
2800 if (newsigs.dsr_up == oldsigs.dsr_up &&
2801 newsigs.dsr_down == oldsigs.dsr_down &&
2802 newsigs.dcd_up == oldsigs.dcd_up &&
2803 newsigs.dcd_down == oldsigs.dcd_down &&
2804 newsigs.cts_up == oldsigs.cts_up &&
2805 newsigs.cts_down == oldsigs.cts_down &&
2806 newsigs.ri_up == oldsigs.ri_up &&
2807 newsigs.ri_down == oldsigs.ri_down &&
2808 cnow.exithunt == cprev.exithunt &&
2809 cnow.rxidle == cprev.rxidle) {
2815 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2816 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2817 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2818 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2819 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2820 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2821 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2822 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2823 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2824 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2832 remove_wait_queue(&info->event_wait_q, &wait);
2833 set_current_state(TASK_RUNNING);
2836 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2837 spin_lock_irqsave(&info->lock,flags);
2838 if (!waitqueue_active(&info->event_wait_q)) {
2839 /* disable enable exit hunt mode/idle rcvd IRQs */
2841 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2843 spin_unlock_irqrestore(&info->lock,flags);
2847 rc = put_user(events, mask_ptr);
2851 static int get_interface(struct slgt_info *info, int __user *if_mode)
2853 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2854 if (put_user(info->if_mode, if_mode))
2859 static int set_interface(struct slgt_info *info, int if_mode)
2861 unsigned long flags;
2864 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2865 spin_lock_irqsave(&info->lock,flags);
2866 info->if_mode = if_mode;
2870 /* TCR (tx control) 07 1=RTS driver control */
2871 val = rd_reg16(info, TCR);
2872 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2876 wr_reg16(info, TCR, val);
2878 spin_unlock_irqrestore(&info->lock,flags);
2882 static int get_xsync(struct slgt_info *info, int __user *xsync)
2884 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2885 if (put_user(info->xsync, xsync))
2891 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2893 * sync pattern is contained in least significant bytes of value
2894 * most significant byte of sync pattern is oldest (1st sent/detected)
2896 static int set_xsync(struct slgt_info *info, int xsync)
2898 unsigned long flags;
2900 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2901 spin_lock_irqsave(&info->lock, flags);
2902 info->xsync = xsync;
2903 wr_reg32(info, XSR, xsync);
2904 spin_unlock_irqrestore(&info->lock, flags);
2908 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2910 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2911 if (put_user(info->xctrl, xctrl))
2917 * set extended control options
2919 * xctrl[31:19] reserved, must be zero
2920 * xctrl[18:17] extended sync pattern length in bytes
2921 * 00 = 1 byte in xsr[7:0]
2922 * 01 = 2 bytes in xsr[15:0]
2923 * 10 = 3 bytes in xsr[23:0]
2924 * 11 = 4 bytes in xsr[31:0]
2925 * xctrl[16] 1 = enable terminal count, 0=disabled
2926 * xctrl[15:0] receive terminal count for fixed length packets
2927 * value is count minus one (0 = 1 byte packet)
2928 * when terminal count is reached, receiver
2929 * automatically returns to hunt mode and receive
2930 * FIFO contents are flushed to DMA buffers with
2931 * end of frame (EOF) status
2933 static int set_xctrl(struct slgt_info *info, int xctrl)
2935 unsigned long flags;
2937 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2938 spin_lock_irqsave(&info->lock, flags);
2939 info->xctrl = xctrl;
2940 wr_reg32(info, XCR, xctrl);
2941 spin_unlock_irqrestore(&info->lock, flags);
2946 * set general purpose IO pin state and direction
2949 * state each bit indicates a pin state
2950 * smask set bit indicates pin state to set
2951 * dir each bit indicates a pin direction (0=input, 1=output)
2952 * dmask set bit indicates pin direction to set
2954 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2956 unsigned long flags;
2957 struct gpio_desc gpio;
2960 if (!info->gpio_present)
2962 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2964 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2965 info->device_name, gpio.state, gpio.smask,
2966 gpio.dir, gpio.dmask));
2968 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2970 data = rd_reg32(info, IODR);
2971 data |= gpio.dmask & gpio.dir;
2972 data &= ~(gpio.dmask & ~gpio.dir);
2973 wr_reg32(info, IODR, data);
2976 data = rd_reg32(info, IOVR);
2977 data |= gpio.smask & gpio.state;
2978 data &= ~(gpio.smask & ~gpio.state);
2979 wr_reg32(info, IOVR, data);
2981 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2987 * get general purpose IO pin state and direction
2989 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2991 struct gpio_desc gpio;
2992 if (!info->gpio_present)
2994 gpio.state = rd_reg32(info, IOVR);
2995 gpio.smask = 0xffffffff;
2996 gpio.dir = rd_reg32(info, IODR);
2997 gpio.dmask = 0xffffffff;
2998 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3000 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3001 info->device_name, gpio.state, gpio.dir));
3006 * conditional wait facility
3008 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3010 init_waitqueue_head(&w->q);
3011 init_waitqueue_entry(&w->wait, current);
3015 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3017 set_current_state(TASK_INTERRUPTIBLE);
3018 add_wait_queue(&w->q, &w->wait);
3023 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3025 struct cond_wait *w, *prev;
3026 remove_wait_queue(&cw->q, &cw->wait);
3027 set_current_state(TASK_RUNNING);
3028 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3031 prev->next = w->next;
3039 static void flush_cond_wait(struct cond_wait **head)
3041 while (*head != NULL) {
3042 wake_up_interruptible(&(*head)->q);
3043 *head = (*head)->next;
3048 * wait for general purpose I/O pin(s) to enter specified state
3051 * state - bit indicates target pin state
3052 * smask - set bit indicates watched pin
3054 * The wait ends when at least one watched pin enters the specified
3055 * state. When 0 (no error) is returned, user_gpio->state is set to the
3056 * state of all GPIO pins when the wait ends.
3058 * Note: Each pin may be a dedicated input, dedicated output, or
3059 * configurable input/output. The number and configuration of pins
3060 * varies with the specific adapter model. Only input pins (dedicated
3061 * or configured) can be monitored with this function.
3063 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3065 unsigned long flags;
3067 struct gpio_desc gpio;
3068 struct cond_wait wait;
3071 if (!info->gpio_present)
3073 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3075 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3076 info->device_name, gpio.state, gpio.smask));
3077 /* ignore output pins identified by set IODR bit */
3078 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3080 init_cond_wait(&wait, gpio.smask);
3082 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3083 /* enable interrupts for watched pins */
3084 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3085 /* get current pin states */
3086 state = rd_reg32(info, IOVR);
3088 if (gpio.smask & ~(state ^ gpio.state)) {
3089 /* already in target state */
3092 /* wait for target state */
3093 add_cond_wait(&info->gpio_wait_q, &wait);
3094 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3096 if (signal_pending(current))
3099 gpio.state = wait.data;
3100 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3101 remove_cond_wait(&info->gpio_wait_q, &wait);
3104 /* disable all GPIO interrupts if no waiting processes */
3105 if (info->gpio_wait_q == NULL)
3106 wr_reg32(info, IOER, 0);
3107 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3109 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3114 static int modem_input_wait(struct slgt_info *info,int arg)
3116 unsigned long flags;
3118 struct mgsl_icount cprev, cnow;
3119 DECLARE_WAITQUEUE(wait, current);
3121 /* save current irq counts */
3122 spin_lock_irqsave(&info->lock,flags);
3123 cprev = info->icount;
3124 add_wait_queue(&info->status_event_wait_q, &wait);
3125 set_current_state(TASK_INTERRUPTIBLE);
3126 spin_unlock_irqrestore(&info->lock,flags);
3130 if (signal_pending(current)) {
3135 /* get new irq counts */
3136 spin_lock_irqsave(&info->lock,flags);
3137 cnow = info->icount;
3138 set_current_state(TASK_INTERRUPTIBLE);
3139 spin_unlock_irqrestore(&info->lock,flags);
3141 /* if no change, wait aborted for some reason */
3142 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3143 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3148 /* check for change in caller specified modem input */
3149 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3150 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3151 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3152 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3159 remove_wait_queue(&info->status_event_wait_q, &wait);
3160 set_current_state(TASK_RUNNING);
3165 * return state of serial control and status signals
3167 static int tiocmget(struct tty_struct *tty)
3169 struct slgt_info *info = tty->driver_data;
3170 unsigned int result;
3171 unsigned long flags;
3173 spin_lock_irqsave(&info->lock,flags);
3175 spin_unlock_irqrestore(&info->lock,flags);
3177 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3178 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3179 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3180 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3181 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3182 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3184 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3189 * set modem control signals (DTR/RTS)
3191 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3192 * TIOCMSET = set/clear signal values
3193 * value bit mask for command
3195 static int tiocmset(struct tty_struct *tty,
3196 unsigned int set, unsigned int clear)
3198 struct slgt_info *info = tty->driver_data;
3199 unsigned long flags;
3201 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3203 if (set & TIOCM_RTS)
3204 info->signals |= SerialSignal_RTS;
3205 if (set & TIOCM_DTR)
3206 info->signals |= SerialSignal_DTR;
3207 if (clear & TIOCM_RTS)
3208 info->signals &= ~SerialSignal_RTS;
3209 if (clear & TIOCM_DTR)
3210 info->signals &= ~SerialSignal_DTR;
3212 spin_lock_irqsave(&info->lock,flags);
3214 spin_unlock_irqrestore(&info->lock,flags);
3218 static int carrier_raised(struct tty_port *port)
3220 unsigned long flags;
3221 struct slgt_info *info = container_of(port, struct slgt_info, port);
3223 spin_lock_irqsave(&info->lock,flags);
3225 spin_unlock_irqrestore(&info->lock,flags);
3226 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3229 static void dtr_rts(struct tty_port *port, int on)
3231 unsigned long flags;
3232 struct slgt_info *info = container_of(port, struct slgt_info, port);
3234 spin_lock_irqsave(&info->lock,flags);
3236 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3238 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3240 spin_unlock_irqrestore(&info->lock,flags);
3245 * block current process until the device is ready to open
3247 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3248 struct slgt_info *info)
3250 DECLARE_WAITQUEUE(wait, current);
3252 bool do_clocal = false;
3253 unsigned long flags;
3255 struct tty_port *port = &info->port;
3257 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3259 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3260 /* nonblock mode is set or port is not enabled */
3261 tty_port_set_active(port, 1);
3268 /* Wait for carrier detect and the line to become
3269 * free (i.e., not in use by the callout). While we are in
3270 * this loop, port->count is dropped by one, so that
3271 * close() knows when to free things. We restore it upon
3272 * exit, either normal or abnormal.
3276 add_wait_queue(&port->open_wait, &wait);
3278 spin_lock_irqsave(&info->lock, flags);
3280 spin_unlock_irqrestore(&info->lock, flags);
3281 port->blocked_open++;
3284 if (C_BAUD(tty) && tty_port_initialized(port))
3285 tty_port_raise_dtr_rts(port);
3287 set_current_state(TASK_INTERRUPTIBLE);
3289 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3290 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3291 -EAGAIN : -ERESTARTSYS;
3295 cd = tty_port_carrier_raised(port);
3296 if (do_clocal || cd)
3299 if (signal_pending(current)) {
3300 retval = -ERESTARTSYS;
3304 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3310 set_current_state(TASK_RUNNING);
3311 remove_wait_queue(&port->open_wait, &wait);
3313 if (!tty_hung_up_p(filp))
3315 port->blocked_open--;
3318 tty_port_set_active(port, 1);
3320 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3325 * allocate buffers used for calling line discipline receive_buf
3326 * directly in synchronous mode
3327 * note: add 5 bytes to max frame size to allow appending
3328 * 32-bit CRC and status byte when configured to do so
3330 static int alloc_tmp_rbuf(struct slgt_info *info)
3332 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3333 if (info->tmp_rbuf == NULL)
3335 /* unused flag buffer to satisfy receive_buf calling interface */
3336 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3337 if (!info->flag_buf) {
3338 kfree(info->tmp_rbuf);
3339 info->tmp_rbuf = NULL;
3345 static void free_tmp_rbuf(struct slgt_info *info)
3347 kfree(info->tmp_rbuf);
3348 info->tmp_rbuf = NULL;
3349 kfree(info->flag_buf);
3350 info->flag_buf = NULL;
3354 * allocate DMA descriptor lists.
3356 static int alloc_desc(struct slgt_info *info)
3361 /* allocate memory to hold descriptor lists */
3362 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3363 &info->bufs_dma_addr);
3364 if (info->bufs == NULL)
3367 info->rbufs = (struct slgt_desc*)info->bufs;
3368 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3370 pbufs = (unsigned int)info->bufs_dma_addr;
3373 * Build circular lists of descriptors
3376 for (i=0; i < info->rbuf_count; i++) {
3377 /* physical address of this descriptor */
3378 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3380 /* physical address of next descriptor */
3381 if (i == info->rbuf_count - 1)
3382 info->rbufs[i].next = cpu_to_le32(pbufs);
3384 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3385 set_desc_count(info->rbufs[i], DMABUFSIZE);
3388 for (i=0; i < info->tbuf_count; i++) {
3389 /* physical address of this descriptor */
3390 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3392 /* physical address of next descriptor */
3393 if (i == info->tbuf_count - 1)
3394 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3396 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3402 static void free_desc(struct slgt_info *info)
3404 if (info->bufs != NULL) {
3405 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3412 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3415 for (i=0; i < count; i++) {
3416 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3418 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3423 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3426 for (i=0; i < count; i++) {
3427 if (bufs[i].buf == NULL)
3429 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3434 static int alloc_dma_bufs(struct slgt_info *info)
3436 info->rbuf_count = 32;
3437 info->tbuf_count = 32;
3439 if (alloc_desc(info) < 0 ||
3440 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3441 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3442 alloc_tmp_rbuf(info) < 0) {
3443 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3450 static void free_dma_bufs(struct slgt_info *info)
3453 free_bufs(info, info->rbufs, info->rbuf_count);
3454 free_bufs(info, info->tbufs, info->tbuf_count);
3457 free_tmp_rbuf(info);
3460 static int claim_resources(struct slgt_info *info)
3462 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3463 DBGERR(("%s reg addr conflict, addr=%08X\n",
3464 info->device_name, info->phys_reg_addr));
3465 info->init_error = DiagStatus_AddressConflict;
3469 info->reg_addr_requested = true;
3471 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3472 if (!info->reg_addr) {
3473 DBGERR(("%s can't map device registers, addr=%08X\n",
3474 info->device_name, info->phys_reg_addr));
3475 info->init_error = DiagStatus_CantAssignPciResources;
3481 release_resources(info);
3485 static void release_resources(struct slgt_info *info)
3487 if (info->irq_requested) {
3488 free_irq(info->irq_level, info);
3489 info->irq_requested = false;
3492 if (info->reg_addr_requested) {
3493 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3494 info->reg_addr_requested = false;
3497 if (info->reg_addr) {
3498 iounmap(info->reg_addr);
3499 info->reg_addr = NULL;
3503 /* Add the specified device instance data structure to the
3504 * global linked list of devices and increment the device count.
3506 static void add_device(struct slgt_info *info)
3510 info->next_device = NULL;
3511 info->line = slgt_device_count;
3512 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3514 if (info->line < MAX_DEVICES) {
3515 if (maxframe[info->line])
3516 info->max_frame_size = maxframe[info->line];
3519 slgt_device_count++;
3521 if (!slgt_device_list)
3522 slgt_device_list = info;
3524 struct slgt_info *current_dev = slgt_device_list;
3525 while(current_dev->next_device)
3526 current_dev = current_dev->next_device;
3527 current_dev->next_device = info;
3530 if (info->max_frame_size < 4096)
3531 info->max_frame_size = 4096;
3532 else if (info->max_frame_size > 65535)
3533 info->max_frame_size = 65535;
3535 switch(info->pdev->device) {
3536 case SYNCLINK_GT_DEVICE_ID:
3539 case SYNCLINK_GT2_DEVICE_ID:
3542 case SYNCLINK_GT4_DEVICE_ID:
3545 case SYNCLINK_AC_DEVICE_ID:
3547 info->params.mode = MGSL_MODE_ASYNC;
3550 devstr = "(unknown model)";
3552 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3553 devstr, info->device_name, info->phys_reg_addr,
3554 info->irq_level, info->max_frame_size);
3556 #if SYNCLINK_GENERIC_HDLC
3561 static const struct tty_port_operations slgt_port_ops = {
3562 .carrier_raised = carrier_raised,
3567 * allocate device instance structure, return NULL on failure
3569 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3571 struct slgt_info *info;
3573 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3576 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3577 driver_name, adapter_num, port_num));
3579 tty_port_init(&info->port);
3580 info->port.ops = &slgt_port_ops;
3581 info->magic = MGSL_MAGIC;
3582 INIT_WORK(&info->task, bh_handler);
3583 info->max_frame_size = 4096;
3584 info->base_clock = 14745600;
3585 info->rbuf_fill_level = DMABUFSIZE;
3586 info->port.close_delay = 5*HZ/10;
3587 info->port.closing_wait = 30*HZ;
3588 init_waitqueue_head(&info->status_event_wait_q);
3589 init_waitqueue_head(&info->event_wait_q);
3590 spin_lock_init(&info->netlock);
3591 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3592 info->idle_mode = HDLC_TXIDLE_FLAGS;
3593 info->adapter_num = adapter_num;
3594 info->port_num = port_num;
3596 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3597 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3599 /* Copy configuration info to device instance data */
3601 info->irq_level = pdev->irq;
3602 info->phys_reg_addr = pci_resource_start(pdev,0);
3604 info->bus_type = MGSL_BUS_TYPE_PCI;
3605 info->irq_flags = IRQF_SHARED;
3607 info->init_error = -1; /* assume error, set to 0 on successful init */
3613 static void device_init(int adapter_num, struct pci_dev *pdev)
3615 struct slgt_info *port_array[SLGT_MAX_PORTS];
3619 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3621 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3624 /* allocate device instances for all ports */
3625 for (i=0; i < port_count; ++i) {
3626 port_array[i] = alloc_dev(adapter_num, i, pdev);
3627 if (port_array[i] == NULL) {
3628 for (--i; i >= 0; --i) {
3629 tty_port_destroy(&port_array[i]->port);
3630 kfree(port_array[i]);
3636 /* give copy of port_array to all ports and add to device list */
3637 for (i=0; i < port_count; ++i) {
3638 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3639 add_device(port_array[i]);
3640 port_array[i]->port_count = port_count;
3641 spin_lock_init(&port_array[i]->lock);
3644 /* Allocate and claim adapter resources */
3645 if (!claim_resources(port_array[0])) {
3647 alloc_dma_bufs(port_array[0]);
3649 /* copy resource information from first port to others */
3650 for (i = 1; i < port_count; ++i) {
3651 port_array[i]->irq_level = port_array[0]->irq_level;
3652 port_array[i]->reg_addr = port_array[0]->reg_addr;
3653 alloc_dma_bufs(port_array[i]);
3656 if (request_irq(port_array[0]->irq_level,
3658 port_array[0]->irq_flags,
3659 port_array[0]->device_name,
3660 port_array[0]) < 0) {
3661 DBGERR(("%s request_irq failed IRQ=%d\n",
3662 port_array[0]->device_name,
3663 port_array[0]->irq_level));
3665 port_array[0]->irq_requested = true;
3666 adapter_test(port_array[0]);
3667 for (i=1 ; i < port_count ; i++) {
3668 port_array[i]->init_error = port_array[0]->init_error;
3669 port_array[i]->gpio_present = port_array[0]->gpio_present;
3674 for (i = 0; i < port_count; ++i) {
3675 struct slgt_info *info = port_array[i];
3676 tty_port_register_device(&info->port, serial_driver, info->line,
3681 static int init_one(struct pci_dev *dev,
3682 const struct pci_device_id *ent)
3684 if (pci_enable_device(dev)) {
3685 printk("error enabling pci device %p\n", dev);
3688 pci_set_master(dev);
3689 device_init(slgt_device_count, dev);
3693 static void remove_one(struct pci_dev *dev)
3697 static const struct tty_operations ops = {
3701 .put_char = put_char,
3702 .flush_chars = flush_chars,
3703 .write_room = write_room,
3704 .chars_in_buffer = chars_in_buffer,
3705 .flush_buffer = flush_buffer,
3707 .compat_ioctl = slgt_compat_ioctl,
3708 .throttle = throttle,
3709 .unthrottle = unthrottle,
3710 .send_xchar = send_xchar,
3711 .break_ctl = set_break,
3712 .wait_until_sent = wait_until_sent,
3713 .set_termios = set_termios,
3715 .start = tx_release,
3717 .tiocmget = tiocmget,
3718 .tiocmset = tiocmset,
3719 .get_icount = get_icount,
3720 .proc_fops = &synclink_gt_proc_fops,
3723 static void slgt_cleanup(void)
3726 struct slgt_info *info;
3727 struct slgt_info *tmp;
3729 printk(KERN_INFO "unload %s\n", driver_name);
3731 if (serial_driver) {
3732 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3733 tty_unregister_device(serial_driver, info->line);
3734 rc = tty_unregister_driver(serial_driver);
3736 DBGERR(("tty_unregister_driver error=%d\n", rc));
3737 put_tty_driver(serial_driver);
3741 info = slgt_device_list;
3744 info = info->next_device;
3747 /* release devices */
3748 info = slgt_device_list;
3750 #if SYNCLINK_GENERIC_HDLC
3753 free_dma_bufs(info);
3754 free_tmp_rbuf(info);
3755 if (info->port_num == 0)
3756 release_resources(info);
3758 info = info->next_device;
3759 tty_port_destroy(&tmp->port);
3764 pci_unregister_driver(&pci_driver);
3768 * Driver initialization entry point.
3770 static int __init slgt_init(void)
3774 printk(KERN_INFO "%s\n", driver_name);
3776 serial_driver = alloc_tty_driver(MAX_DEVICES);
3777 if (!serial_driver) {
3778 printk("%s can't allocate tty driver\n", driver_name);
3782 /* Initialize the tty_driver structure */
3784 serial_driver->driver_name = slgt_driver_name;
3785 serial_driver->name = tty_dev_prefix;
3786 serial_driver->major = ttymajor;
3787 serial_driver->minor_start = 64;
3788 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3789 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3790 serial_driver->init_termios = tty_std_termios;
3791 serial_driver->init_termios.c_cflag =
3792 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3793 serial_driver->init_termios.c_ispeed = 9600;
3794 serial_driver->init_termios.c_ospeed = 9600;
3795 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3796 tty_set_operations(serial_driver, &ops);
3797 if ((rc = tty_register_driver(serial_driver)) < 0) {
3798 DBGERR(("%s can't register serial driver\n", driver_name));
3799 put_tty_driver(serial_driver);
3800 serial_driver = NULL;
3804 printk(KERN_INFO "%s, tty major#%d\n",
3805 driver_name, serial_driver->major);
3807 slgt_device_count = 0;
3808 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3809 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3812 pci_registered = true;
3814 if (!slgt_device_list)
3815 printk("%s no devices found\n",driver_name);
3824 static void __exit slgt_exit(void)
3829 module_init(slgt_init);
3830 module_exit(slgt_exit);
3833 * register access routines
3836 #define CALC_REGADDR() \
3837 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3839 reg_addr += (info->port_num) * 32; \
3840 else if (addr >= 0x40) \
3841 reg_addr += (info->port_num) * 16;
3843 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3846 return readb((void __iomem *)reg_addr);
3849 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3852 writeb(value, (void __iomem *)reg_addr);
3855 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3858 return readw((void __iomem *)reg_addr);
3861 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3864 writew(value, (void __iomem *)reg_addr);
3867 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3870 return readl((void __iomem *)reg_addr);
3873 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3876 writel(value, (void __iomem *)reg_addr);
3879 static void rdma_reset(struct slgt_info *info)
3884 wr_reg32(info, RDCSR, BIT1);
3886 /* wait for enable bit cleared */
3887 for(i=0 ; i < 1000 ; i++)
3888 if (!(rd_reg32(info, RDCSR) & BIT0))
3892 static void tdma_reset(struct slgt_info *info)
3897 wr_reg32(info, TDCSR, BIT1);
3899 /* wait for enable bit cleared */
3900 for(i=0 ; i < 1000 ; i++)
3901 if (!(rd_reg32(info, TDCSR) & BIT0))
3906 * enable internal loopback
3907 * TxCLK and RxCLK are generated from BRG
3908 * and TxD is looped back to RxD internally.
3910 static void enable_loopback(struct slgt_info *info)
3912 /* SCR (serial control) BIT2=loopback enable */
3913 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3915 if (info->params.mode != MGSL_MODE_ASYNC) {
3916 /* CCR (clock control)
3917 * 07..05 tx clock source (010 = BRG)
3918 * 04..02 rx clock source (010 = BRG)
3919 * 01 auxclk enable (0 = disable)
3920 * 00 BRG enable (1 = enable)
3924 wr_reg8(info, CCR, 0x49);
3926 /* set speed if available, otherwise use default */
3927 if (info->params.clock_speed)
3928 set_rate(info, info->params.clock_speed);
3930 set_rate(info, 3686400);
3935 * set baud rate generator to specified rate
3937 static void set_rate(struct slgt_info *info, u32 rate)
3940 unsigned int osc = info->base_clock;
3942 /* div = osc/rate - 1
3944 * Round div up if osc/rate is not integer to
3945 * force to next slowest rate.
3950 if (!(osc % rate) && div)
3952 wr_reg16(info, BDR, (unsigned short)div);
3956 static void rx_stop(struct slgt_info *info)
3960 /* disable and reset receiver */
3961 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3962 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3963 wr_reg16(info, RCR, val); /* clear reset bit */
3965 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3967 /* clear pending rx interrupts */
3968 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3972 info->rx_enabled = false;
3973 info->rx_restart = false;
3976 static void rx_start(struct slgt_info *info)
3980 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3982 /* clear pending rx overrun IRQ */
3983 wr_reg16(info, SSR, IRQ_RXOVER);
3985 /* reset and disable receiver */
3986 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3987 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3988 wr_reg16(info, RCR, val); /* clear reset bit */
3994 /* rx request when rx FIFO not empty */
3995 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3996 slgt_irq_on(info, IRQ_RXDATA);
3997 if (info->params.mode == MGSL_MODE_ASYNC) {
3998 /* enable saving of rx status */
3999 wr_reg32(info, RDCSR, BIT6);
4002 /* rx request when rx FIFO half full */
4003 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4004 /* set 1st descriptor address */
4005 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4007 if (info->params.mode != MGSL_MODE_ASYNC) {
4008 /* enable rx DMA and DMA interrupt */
4009 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4011 /* enable saving of rx status, rx DMA and DMA interrupt */
4012 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4016 slgt_irq_on(info, IRQ_RXOVER);
4018 /* enable receiver */
4019 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4021 info->rx_restart = false;
4022 info->rx_enabled = true;
4025 static void tx_start(struct slgt_info *info)
4027 if (!info->tx_enabled) {
4029 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4030 info->tx_enabled = true;
4033 if (desc_count(info->tbufs[info->tbuf_start])) {
4034 info->drop_rts_on_tx_done = false;
4036 if (info->params.mode != MGSL_MODE_ASYNC) {
4037 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4039 if (!(info->signals & SerialSignal_RTS)) {
4040 info->signals |= SerialSignal_RTS;
4042 info->drop_rts_on_tx_done = true;
4046 slgt_irq_off(info, IRQ_TXDATA);
4047 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4048 /* clear tx idle and underrun status bits */
4049 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4051 slgt_irq_off(info, IRQ_TXDATA);
4052 slgt_irq_on(info, IRQ_TXIDLE);
4053 /* clear tx idle status bit */
4054 wr_reg16(info, SSR, IRQ_TXIDLE);
4056 /* set 1st descriptor address and start DMA */
4057 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4058 wr_reg32(info, TDCSR, BIT2 + BIT0);
4059 info->tx_active = true;
4063 static void tx_stop(struct slgt_info *info)
4067 del_timer(&info->tx_timer);
4071 /* reset and disable transmitter */
4072 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4073 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4075 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4077 /* clear tx idle and underrun status bit */
4078 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4082 info->tx_enabled = false;
4083 info->tx_active = false;
4086 static void reset_port(struct slgt_info *info)
4088 if (!info->reg_addr)
4094 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4097 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4100 static void reset_adapter(struct slgt_info *info)
4103 for (i=0; i < info->port_count; ++i) {
4104 if (info->port_array[i])
4105 reset_port(info->port_array[i]);
4109 static void async_mode(struct slgt_info *info)
4113 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4119 * 15..13 mode, 010=async
4120 * 12..10 encoding, 000=NRZ
4122 * 08 1=odd parity, 0=even parity
4123 * 07 1=RTS driver control
4125 * 05..04 character length
4130 * 03 0=1 stop bit, 1=2 stop bits
4133 * 00 auto-CTS enable
4137 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4140 if (info->params.parity != ASYNC_PARITY_NONE) {
4142 if (info->params.parity == ASYNC_PARITY_ODD)
4146 switch (info->params.data_bits)
4148 case 6: val |= BIT4; break;
4149 case 7: val |= BIT5; break;
4150 case 8: val |= BIT5 + BIT4; break;
4153 if (info->params.stop_bits != 1)
4156 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4159 wr_reg16(info, TCR, val);
4163 * 15..13 mode, 010=async
4164 * 12..10 encoding, 000=NRZ
4166 * 08 1=odd parity, 0=even parity
4167 * 07..06 reserved, must be 0
4168 * 05..04 character length
4173 * 03 reserved, must be zero
4176 * 00 auto-DCD enable
4180 if (info->params.parity != ASYNC_PARITY_NONE) {
4182 if (info->params.parity == ASYNC_PARITY_ODD)
4186 switch (info->params.data_bits)
4188 case 6: val |= BIT4; break;
4189 case 7: val |= BIT5; break;
4190 case 8: val |= BIT5 + BIT4; break;
4193 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4196 wr_reg16(info, RCR, val);
4198 /* CCR (clock control)
4200 * 07..05 011 = tx clock source is BRG/16
4201 * 04..02 010 = rx clock source is BRG
4202 * 01 0 = auxclk disabled
4203 * 00 1 = BRG enabled
4207 wr_reg8(info, CCR, 0x69);
4211 /* SCR (serial control)
4213 * 15 1=tx req on FIFO half empty
4214 * 14 1=rx req on FIFO half full
4215 * 13 tx data IRQ enable
4216 * 12 tx idle IRQ enable
4217 * 11 rx break on IRQ enable
4218 * 10 rx data IRQ enable
4219 * 09 rx break off IRQ enable
4220 * 08 overrun IRQ enable
4225 * 03 0=16x sampling, 1=8x sampling
4226 * 02 1=txd->rxd internal loopback enable
4227 * 01 reserved, must be zero
4228 * 00 1=master IRQ enable
4230 val = BIT15 + BIT14 + BIT0;
4231 /* JCR[8] : 1 = x8 async mode feature available */
4232 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4233 ((info->base_clock < (info->params.data_rate * 16)) ||
4234 (info->base_clock % (info->params.data_rate * 16)))) {
4235 /* use 8x sampling */
4237 set_rate(info, info->params.data_rate * 8);
4239 /* use 16x sampling */
4240 set_rate(info, info->params.data_rate * 16);
4242 wr_reg16(info, SCR, val);
4244 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4246 if (info->params.loopback)
4247 enable_loopback(info);
4250 static void sync_mode(struct slgt_info *info)
4254 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4262 * 001=raw bit synchronous
4263 * 010=asynchronous/isochronous
4264 * 011=monosync byte synchronous
4265 * 100=bisync byte synchronous
4266 * 101=xsync byte synchronous
4270 * 07 1=RTS driver control
4271 * 06 preamble enable
4272 * 05..04 preamble length
4273 * 03 share open/close flag
4276 * 00 auto-CTS enable
4280 switch(info->params.mode) {
4281 case MGSL_MODE_XSYNC:
4282 val |= BIT15 + BIT13;
4284 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4285 case MGSL_MODE_BISYNC: val |= BIT15; break;
4286 case MGSL_MODE_RAW: val |= BIT13; break;
4288 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4291 switch(info->params.encoding)
4293 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4294 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4295 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4296 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4297 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4298 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4299 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4302 switch (info->params.crc_type & HDLC_CRC_MASK)
4304 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4305 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4308 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4311 switch (info->params.preamble_length)
4313 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4314 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4315 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4318 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4321 wr_reg16(info, TCR, val);
4323 /* TPR (transmit preamble) */
4325 switch (info->params.preamble)
4327 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4328 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4329 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4330 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4331 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4332 default: val = 0x7e; break;
4334 wr_reg8(info, TPR, (unsigned char)val);
4340 * 001=raw bit synchronous
4341 * 010=asynchronous/isochronous
4342 * 011=monosync byte synchronous
4343 * 100=bisync byte synchronous
4344 * 101=xsync byte synchronous
4348 * 07..03 reserved, must be 0
4351 * 00 auto-DCD enable
4355 switch(info->params.mode) {
4356 case MGSL_MODE_XSYNC:
4357 val |= BIT15 + BIT13;
4359 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4360 case MGSL_MODE_BISYNC: val |= BIT15; break;
4361 case MGSL_MODE_RAW: val |= BIT13; break;
4364 switch(info->params.encoding)
4366 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4367 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4368 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4369 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4370 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4371 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4372 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4375 switch (info->params.crc_type & HDLC_CRC_MASK)
4377 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4378 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4381 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4384 wr_reg16(info, RCR, val);
4386 /* CCR (clock control)
4388 * 07..05 tx clock source
4389 * 04..02 rx clock source
4395 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4397 // when RxC source is DPLL, BRG generates 16X DPLL
4398 // reference clock, so take TxC from BRG/16 to get
4399 // transmit clock at actual data rate
4400 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4401 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4403 val |= BIT6; /* 010, txclk = BRG */
4405 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4406 val |= BIT7; /* 100, txclk = DPLL Input */
4407 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4408 val |= BIT5; /* 001, txclk = RXC Input */
4410 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4411 val |= BIT3; /* 010, rxclk = BRG */
4412 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4413 val |= BIT4; /* 100, rxclk = DPLL */
4414 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4415 val |= BIT2; /* 001, rxclk = TXC Input */
4417 if (info->params.clock_speed)
4420 wr_reg8(info, CCR, (unsigned char)val);
4422 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4424 // program DPLL mode
4425 switch(info->params.encoding)
4427 case HDLC_ENCODING_BIPHASE_MARK:
4428 case HDLC_ENCODING_BIPHASE_SPACE:
4430 case HDLC_ENCODING_BIPHASE_LEVEL:
4431 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4432 val = BIT7 + BIT6; break;
4433 default: val = BIT6; // NRZ encodings
4435 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4437 // DPLL requires a 16X reference clock from BRG
4438 set_rate(info, info->params.clock_speed * 16);
4441 set_rate(info, info->params.clock_speed);
4447 /* SCR (serial control)
4449 * 15 1=tx req on FIFO half empty
4450 * 14 1=rx req on FIFO half full
4451 * 13 tx data IRQ enable
4452 * 12 tx idle IRQ enable
4453 * 11 underrun IRQ enable
4454 * 10 rx data IRQ enable
4455 * 09 rx idle IRQ enable
4456 * 08 overrun IRQ enable
4461 * 03 reserved, must be zero
4462 * 02 1=txd->rxd internal loopback enable
4463 * 01 reserved, must be zero
4464 * 00 1=master IRQ enable
4466 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4468 if (info->params.loopback)
4469 enable_loopback(info);
4473 * set transmit idle mode
4475 static void tx_set_idle(struct slgt_info *info)
4480 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4481 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4483 tcr = rd_reg16(info, TCR);
4484 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4485 /* disable preamble, set idle size to 16 bits */
4486 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4487 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4488 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4489 } else if (!(tcr & BIT6)) {
4490 /* preamble is disabled, set idle size to 8 bits */
4491 tcr &= ~(BIT5 + BIT4);
4493 wr_reg16(info, TCR, tcr);
4495 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4496 /* LSB of custom tx idle specified in tx idle register */
4497 val = (unsigned char)(info->idle_mode & 0xff);
4499 /* standard 8 bit idle patterns */
4500 switch(info->idle_mode)
4502 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4503 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4504 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4505 case HDLC_TXIDLE_ZEROS:
4506 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4507 default: val = 0xff;
4511 wr_reg8(info, TIR, val);
4515 * get state of V24 status (input) signals
4517 static void get_signals(struct slgt_info *info)
4519 unsigned short status = rd_reg16(info, SSR);
4521 /* clear all serial signals except RTS and DTR */
4522 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4525 info->signals |= SerialSignal_DSR;
4527 info->signals |= SerialSignal_CTS;
4529 info->signals |= SerialSignal_DCD;
4531 info->signals |= SerialSignal_RI;
4535 * set V.24 Control Register based on current configuration
4537 static void msc_set_vcr(struct slgt_info *info)
4539 unsigned char val = 0;
4541 /* VCR (V.24 control)
4543 * 07..04 serial IF select
4550 switch(info->if_mode & MGSL_INTERFACE_MASK)
4552 case MGSL_INTERFACE_RS232:
4553 val |= BIT5; /* 0010 */
4555 case MGSL_INTERFACE_V35:
4556 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4558 case MGSL_INTERFACE_RS422:
4559 val |= BIT6; /* 0100 */
4563 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4565 if (info->signals & SerialSignal_DTR)
4567 if (info->signals & SerialSignal_RTS)
4569 if (info->if_mode & MGSL_INTERFACE_LL)
4571 if (info->if_mode & MGSL_INTERFACE_RL)
4573 wr_reg8(info, VCR, val);
4577 * set state of V24 control (output) signals
4579 static void set_signals(struct slgt_info *info)
4581 unsigned char val = rd_reg8(info, VCR);
4582 if (info->signals & SerialSignal_DTR)
4586 if (info->signals & SerialSignal_RTS)
4590 wr_reg8(info, VCR, val);
4594 * free range of receive DMA buffers (i to last)
4596 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4601 /* reset current buffer for reuse */
4602 info->rbufs[i].status = 0;
4603 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4606 if (++i == info->rbuf_count)
4609 info->rbuf_current = i;
4613 * mark all receive DMA buffers as free
4615 static void reset_rbufs(struct slgt_info *info)
4617 free_rbufs(info, 0, info->rbuf_count - 1);
4618 info->rbuf_fill_index = 0;
4619 info->rbuf_fill_count = 0;
4623 * pass receive HDLC frame to upper layer
4625 * return true if frame available, otherwise false
4627 static bool rx_get_frame(struct slgt_info *info)
4629 unsigned int start, end;
4630 unsigned short status;
4631 unsigned int framesize = 0;
4632 unsigned long flags;
4633 struct tty_struct *tty = info->port.tty;
4634 unsigned char addr_field = 0xff;
4635 unsigned int crc_size = 0;
4637 switch (info->params.crc_type & HDLC_CRC_MASK) {
4638 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4639 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4646 start = end = info->rbuf_current;
4649 if (!desc_complete(info->rbufs[end]))
4652 if (framesize == 0 && info->params.addr_filter != 0xff)
4653 addr_field = info->rbufs[end].buf[0];
4655 framesize += desc_count(info->rbufs[end]);
4657 if (desc_eof(info->rbufs[end]))
4660 if (++end == info->rbuf_count)
4663 if (end == info->rbuf_current) {
4664 if (info->rx_enabled){
4665 spin_lock_irqsave(&info->lock,flags);
4667 spin_unlock_irqrestore(&info->lock,flags);
4675 * 15 buffer complete
4678 * 02 eof (end of frame)
4682 status = desc_status(info->rbufs[end]);
4684 /* ignore CRC bit if not using CRC (bit is undefined) */
4685 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4688 if (framesize == 0 ||
4689 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4690 free_rbufs(info, start, end);
4694 if (framesize < (2 + crc_size) || status & BIT0) {
4695 info->icount.rxshort++;
4697 } else if (status & BIT1) {
4698 info->icount.rxcrc++;
4699 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4703 #if SYNCLINK_GENERIC_HDLC
4704 if (framesize == 0) {
4705 info->netdev->stats.rx_errors++;
4706 info->netdev->stats.rx_frame_errors++;
4710 DBGBH(("%s rx frame status=%04X size=%d\n",
4711 info->device_name, status, framesize));
4712 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4715 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4716 framesize -= crc_size;
4720 if (framesize > info->max_frame_size + crc_size)
4721 info->icount.rxlong++;
4723 /* copy dma buffer(s) to contiguous temp buffer */
4724 int copy_count = framesize;
4726 unsigned char *p = info->tmp_rbuf;
4727 info->tmp_rbuf_count = framesize;
4729 info->icount.rxok++;
4732 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4733 memcpy(p, info->rbufs[i].buf, partial_count);
4735 copy_count -= partial_count;
4736 if (++i == info->rbuf_count)
4740 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4741 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4745 #if SYNCLINK_GENERIC_HDLC
4747 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4750 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4753 free_rbufs(info, start, end);
4761 * pass receive buffer (RAW synchronous mode) to tty layer
4762 * return true if buffer available, otherwise false
4764 static bool rx_get_buf(struct slgt_info *info)
4766 unsigned int i = info->rbuf_current;
4769 if (!desc_complete(info->rbufs[i]))
4771 count = desc_count(info->rbufs[i]);
4772 switch(info->params.mode) {
4773 case MGSL_MODE_MONOSYNC:
4774 case MGSL_MODE_BISYNC:
4775 case MGSL_MODE_XSYNC:
4776 /* ignore residue in byte synchronous modes */
4777 if (desc_residue(info->rbufs[i]))
4781 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4782 DBGINFO(("rx_get_buf size=%d\n", count));
4784 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4785 info->flag_buf, count);
4786 free_rbufs(info, i, i);
4790 static void reset_tbufs(struct slgt_info *info)
4793 info->tbuf_current = 0;
4794 for (i=0 ; i < info->tbuf_count ; i++) {
4795 info->tbufs[i].status = 0;
4796 info->tbufs[i].count = 0;
4801 * return number of free transmit DMA buffers
4803 static unsigned int free_tbuf_count(struct slgt_info *info)
4805 unsigned int count = 0;
4806 unsigned int i = info->tbuf_current;
4810 if (desc_count(info->tbufs[i]))
4811 break; /* buffer in use */
4813 if (++i == info->tbuf_count)
4815 } while (i != info->tbuf_current);
4817 /* if tx DMA active, last zero count buffer is in use */
4818 if (count && (rd_reg32(info, TDCSR) & BIT0))
4825 * return number of bytes in unsent transmit DMA buffers
4826 * and the serial controller tx FIFO
4828 static unsigned int tbuf_bytes(struct slgt_info *info)
4830 unsigned int total_count = 0;
4831 unsigned int i = info->tbuf_current;
4832 unsigned int reg_value;
4834 unsigned int active_buf_count = 0;
4837 * Add descriptor counts for all tx DMA buffers.
4838 * If count is zero (cleared by DMA controller after read),
4839 * the buffer is complete or is actively being read from.
4841 * Record buf_count of last buffer with zero count starting
4842 * from current ring position. buf_count is mirror
4843 * copy of count and is not cleared by serial controller.
4844 * If DMA controller is active, that buffer is actively
4845 * being read so add to total.
4848 count = desc_count(info->tbufs[i]);
4850 total_count += count;
4851 else if (!total_count)
4852 active_buf_count = info->tbufs[i].buf_count;
4853 if (++i == info->tbuf_count)
4855 } while (i != info->tbuf_current);
4857 /* read tx DMA status register */
4858 reg_value = rd_reg32(info, TDCSR);
4860 /* if tx DMA active, last zero count buffer is in use */
4861 if (reg_value & BIT0)
4862 total_count += active_buf_count;
4864 /* add tx FIFO count = reg_value[15..8] */
4865 total_count += (reg_value >> 8) & 0xff;
4867 /* if transmitter active add one byte for shift register */
4868 if (info->tx_active)
4875 * load data into transmit DMA buffer ring and start transmitter if needed
4876 * return true if data accepted, otherwise false (buffers full)
4878 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4880 unsigned short count;
4882 struct slgt_desc *d;
4884 /* check required buffer space */
4885 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4888 DBGDATA(info, buf, size, "tx");
4891 * copy data to one or more DMA buffers in circular ring
4892 * tbuf_start = first buffer for this data
4893 * tbuf_current = next free buffer
4895 * Copy all data before making data visible to DMA controller by
4896 * setting descriptor count of the first buffer.
4897 * This prevents an active DMA controller from reading the first DMA
4898 * buffers of a frame and stopping before the final buffers are filled.
4901 info->tbuf_start = i = info->tbuf_current;
4904 d = &info->tbufs[i];
4906 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4907 memcpy(d->buf, buf, count);
4913 * set EOF bit for last buffer of HDLC frame or
4914 * for every buffer in raw mode
4916 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4917 info->params.mode == MGSL_MODE_RAW)
4918 set_desc_eof(*d, 1);
4920 set_desc_eof(*d, 0);
4922 /* set descriptor count for all but first buffer */
4923 if (i != info->tbuf_start)
4924 set_desc_count(*d, count);
4925 d->buf_count = count;
4927 if (++i == info->tbuf_count)
4931 info->tbuf_current = i;
4933 /* set first buffer count to make new data visible to DMA controller */
4934 d = &info->tbufs[info->tbuf_start];
4935 set_desc_count(*d, d->buf_count);
4937 /* start transmitter if needed and update transmit timeout */
4938 if (!info->tx_active)
4940 update_tx_timer(info);
4945 static int register_test(struct slgt_info *info)
4947 static unsigned short patterns[] =
4948 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4949 static unsigned int count = ARRAY_SIZE(patterns);
4953 for (i=0 ; i < count ; i++) {
4954 wr_reg16(info, TIR, patterns[i]);
4955 wr_reg16(info, BDR, patterns[(i+1)%count]);
4956 if ((rd_reg16(info, TIR) != patterns[i]) ||
4957 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4962 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4963 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4967 static int irq_test(struct slgt_info *info)
4969 unsigned long timeout;
4970 unsigned long flags;
4971 struct tty_struct *oldtty = info->port.tty;
4972 u32 speed = info->params.data_rate;
4974 info->params.data_rate = 921600;
4975 info->port.tty = NULL;
4977 spin_lock_irqsave(&info->lock, flags);
4979 slgt_irq_on(info, IRQ_TXIDLE);
4981 /* enable transmitter */
4983 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4985 /* write one byte and wait for tx idle */
4986 wr_reg16(info, TDR, 0);
4988 /* assume failure */
4989 info->init_error = DiagStatus_IrqFailure;
4990 info->irq_occurred = false;
4992 spin_unlock_irqrestore(&info->lock, flags);
4995 while(timeout-- && !info->irq_occurred)
4996 msleep_interruptible(10);
4998 spin_lock_irqsave(&info->lock,flags);
5000 spin_unlock_irqrestore(&info->lock,flags);
5002 info->params.data_rate = speed;
5003 info->port.tty = oldtty;
5005 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5006 return info->irq_occurred ? 0 : -ENODEV;
5009 static int loopback_test_rx(struct slgt_info *info)
5011 unsigned char *src, *dest;
5014 if (desc_complete(info->rbufs[0])) {
5015 count = desc_count(info->rbufs[0]);
5016 src = info->rbufs[0].buf;
5017 dest = info->tmp_rbuf;
5019 for( ; count ; count-=2, src+=2) {
5020 /* src=data byte (src+1)=status byte */
5021 if (!(*(src+1) & (BIT9 + BIT8))) {
5024 info->tmp_rbuf_count++;
5027 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5033 static int loopback_test(struct slgt_info *info)
5035 #define TESTFRAMESIZE 20
5037 unsigned long timeout;
5038 u16 count = TESTFRAMESIZE;
5039 unsigned char buf[TESTFRAMESIZE];
5041 unsigned long flags;
5043 struct tty_struct *oldtty = info->port.tty;
5046 memcpy(¶ms, &info->params, sizeof(params));
5048 info->params.mode = MGSL_MODE_ASYNC;
5049 info->params.data_rate = 921600;
5050 info->params.loopback = 1;
5051 info->port.tty = NULL;
5053 /* build and send transmit frame */
5054 for (count = 0; count < TESTFRAMESIZE; ++count)
5055 buf[count] = (unsigned char)count;
5057 info->tmp_rbuf_count = 0;
5058 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5060 /* program hardware for HDLC and enabled receiver */
5061 spin_lock_irqsave(&info->lock,flags);
5064 tx_load(info, buf, count);
5065 spin_unlock_irqrestore(&info->lock, flags);
5067 /* wait for receive complete */
5068 for (timeout = 100; timeout; --timeout) {
5069 msleep_interruptible(10);
5070 if (loopback_test_rx(info)) {
5076 /* verify received frame length and contents */
5077 if (!rc && (info->tmp_rbuf_count != count ||
5078 memcmp(buf, info->tmp_rbuf, count))) {
5082 spin_lock_irqsave(&info->lock,flags);
5083 reset_adapter(info);
5084 spin_unlock_irqrestore(&info->lock,flags);
5086 memcpy(&info->params, ¶ms, sizeof(info->params));
5087 info->port.tty = oldtty;
5089 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5093 static int adapter_test(struct slgt_info *info)
5095 DBGINFO(("testing %s\n", info->device_name));
5096 if (register_test(info) < 0) {
5097 printk("register test failure %s addr=%08X\n",
5098 info->device_name, info->phys_reg_addr);
5099 } else if (irq_test(info) < 0) {
5100 printk("IRQ test failure %s IRQ=%d\n",
5101 info->device_name, info->irq_level);
5102 } else if (loopback_test(info) < 0) {
5103 printk("loopback test failure %s\n", info->device_name);
5105 return info->init_error;
5109 * transmit timeout handler
5111 static void tx_timeout(unsigned long context)
5113 struct slgt_info *info = (struct slgt_info*)context;
5114 unsigned long flags;
5116 DBGINFO(("%s tx_timeout\n", info->device_name));
5117 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5118 info->icount.txtimeout++;
5120 spin_lock_irqsave(&info->lock,flags);
5122 spin_unlock_irqrestore(&info->lock,flags);
5124 #if SYNCLINK_GENERIC_HDLC
5126 hdlcdev_tx_done(info);
5133 * receive buffer polling timer
5135 static void rx_timeout(unsigned long context)
5137 struct slgt_info *info = (struct slgt_info*)context;
5138 unsigned long flags;
5140 DBGINFO(("%s rx_timeout\n", info->device_name));
5141 spin_lock_irqsave(&info->lock, flags);
5142 info->pending_bh |= BH_RECEIVE;
5143 spin_unlock_irqrestore(&info->lock, flags);
5144 bh_handler(&info->task);