2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Suspend support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqdomain.h>
24 #include <linux/of_address.h>
25 #include <linux/err.h>
26 #include <linux/regulator/machine.h>
28 #include <asm/cacheflush.h>
29 #include <asm/hardware/cache-l2x0.h>
30 #include <asm/firmware.h>
32 #include <asm/smp_scu.h>
33 #include <asm/suspend.h>
35 #include <plat/pm-common.h>
38 #include "exynos-pmu.h"
40 #include "regs-srom.h"
42 #define REG_TABLE_END (-1U)
44 #define EXYNOS5420_CPU_STATE 0x28
47 * struct exynos_wkup_irq - PMU IRQ to mask mapping
48 * @hwirq: Hardware IRQ signal of the PMU
49 * @mask: Mask in PMU wake-up mask register
51 struct exynos_wkup_irq {
56 static struct sleep_save exynos_core_save[] = {
58 SAVE_ITEM(S5P_SROM_BW),
59 SAVE_ITEM(S5P_SROM_BC0),
60 SAVE_ITEM(S5P_SROM_BC1),
61 SAVE_ITEM(S5P_SROM_BC2),
62 SAVE_ITEM(S5P_SROM_BC3),
65 struct exynos_pm_data {
66 const struct exynos_wkup_irq *wkup_irq;
67 unsigned int wake_disable_mask;
68 unsigned int *release_ret_regs;
70 void (*pm_prepare)(void);
71 void (*pm_resume_prepare)(void);
72 void (*pm_resume)(void);
73 int (*pm_suspend)(void);
74 int (*cpu_suspend)(unsigned long);
77 static const struct exynos_pm_data *pm_data;
79 static int exynos5420_cpu_state;
80 static unsigned int exynos_pmu_spare3;
86 static u32 exynos_irqwake_intmask = 0xffffffff;
88 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
89 { 73, BIT(1) }, /* RTC alarm */
90 { 74, BIT(2) }, /* RTC tick */
94 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
95 { 44, BIT(1) }, /* RTC alarm */
96 { 45, BIT(2) }, /* RTC tick */
100 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
101 { 43, BIT(1) }, /* RTC alarm */
102 { 44, BIT(2) }, /* RTC tick */
106 static unsigned int exynos_release_ret_regs[] = {
107 S5P_PAD_RET_MAUDIO_OPTION,
108 S5P_PAD_RET_GPIO_OPTION,
109 S5P_PAD_RET_UART_OPTION,
110 S5P_PAD_RET_MMCA_OPTION,
111 S5P_PAD_RET_MMCB_OPTION,
112 S5P_PAD_RET_EBIA_OPTION,
113 S5P_PAD_RET_EBIB_OPTION,
117 static unsigned int exynos3250_release_ret_regs[] = {
118 S5P_PAD_RET_MAUDIO_OPTION,
119 S5P_PAD_RET_GPIO_OPTION,
120 S5P_PAD_RET_UART_OPTION,
121 S5P_PAD_RET_MMCA_OPTION,
122 S5P_PAD_RET_MMCB_OPTION,
123 S5P_PAD_RET_EBIA_OPTION,
124 S5P_PAD_RET_EBIB_OPTION,
125 S5P_PAD_RET_MMC2_OPTION,
126 S5P_PAD_RET_SPI_OPTION,
130 static unsigned int exynos5420_release_ret_regs[] = {
131 EXYNOS_PAD_RET_DRAM_OPTION,
132 EXYNOS_PAD_RET_MAUDIO_OPTION,
133 EXYNOS_PAD_RET_JTAG_OPTION,
134 EXYNOS5420_PAD_RET_GPIO_OPTION,
135 EXYNOS5420_PAD_RET_UART_OPTION,
136 EXYNOS5420_PAD_RET_MMCA_OPTION,
137 EXYNOS5420_PAD_RET_MMCB_OPTION,
138 EXYNOS5420_PAD_RET_MMCC_OPTION,
139 EXYNOS5420_PAD_RET_HSI_OPTION,
140 EXYNOS_PAD_RET_EBIA_OPTION,
141 EXYNOS_PAD_RET_EBIB_OPTION,
142 EXYNOS5420_PAD_RET_SPI_OPTION,
143 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
147 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
149 const struct exynos_wkup_irq *wkup_irq;
151 if (!pm_data->wkup_irq)
153 wkup_irq = pm_data->wkup_irq;
155 while (wkup_irq->mask) {
156 if (wkup_irq->hwirq == data->hwirq) {
158 exynos_irqwake_intmask |= wkup_irq->mask;
160 exynos_irqwake_intmask &= ~wkup_irq->mask;
169 static struct irq_chip exynos_pmu_chip = {
171 .irq_eoi = irq_chip_eoi_parent,
172 .irq_mask = irq_chip_mask_parent,
173 .irq_unmask = irq_chip_unmask_parent,
174 .irq_retrigger = irq_chip_retrigger_hierarchy,
175 .irq_set_wake = exynos_irq_set_wake,
177 .irq_set_affinity = irq_chip_set_affinity_parent,
181 static int exynos_pmu_domain_translate(struct irq_domain *d,
182 struct irq_fwspec *fwspec,
183 unsigned long *hwirq,
186 if (is_of_node(fwspec->fwnode)) {
187 if (fwspec->param_count != 3)
190 /* No PPI should point to this domain */
191 if (fwspec->param[0] != 0)
194 *hwirq = fwspec->param[1];
195 *type = fwspec->param[2];
202 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
204 unsigned int nr_irqs, void *data)
206 struct irq_fwspec *fwspec = data;
207 struct irq_fwspec parent_fwspec;
208 irq_hw_number_t hwirq;
211 if (fwspec->param_count != 3)
212 return -EINVAL; /* Not GIC compliant */
213 if (fwspec->param[0] != 0)
214 return -EINVAL; /* No PPI should point to this domain */
216 hwirq = fwspec->param[1];
218 for (i = 0; i < nr_irqs; i++)
219 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
220 &exynos_pmu_chip, NULL);
222 parent_fwspec = *fwspec;
223 parent_fwspec.fwnode = domain->parent->fwnode;
224 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
228 static const struct irq_domain_ops exynos_pmu_domain_ops = {
229 .translate = exynos_pmu_domain_translate,
230 .alloc = exynos_pmu_domain_alloc,
231 .free = irq_domain_free_irqs_common,
234 static int __init exynos_pmu_irq_init(struct device_node *node,
235 struct device_node *parent)
237 struct irq_domain *parent_domain, *domain;
240 pr_err("%s: no parent, giving up\n", node->full_name);
244 parent_domain = irq_find_host(parent);
245 if (!parent_domain) {
246 pr_err("%s: unable to obtain parent domain\n", node->full_name);
250 pmu_base_addr = of_iomap(node, 0);
252 if (!pmu_base_addr) {
253 pr_err("%s: failed to find exynos pmu register\n",
258 domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
259 node, &exynos_pmu_domain_ops,
262 iounmap(pmu_base_addr);
263 pmu_base_addr = NULL;
270 #define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
272 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
273 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
274 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
275 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
276 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
277 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
278 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
280 static int exynos_cpu_do_idle(void)
282 /* issue the standby signal into the pm unit. */
285 pr_info("Failed to suspend the system\n");
286 return 1; /* Aborting suspend */
288 static void exynos_flush_cache_all(void)
294 static int exynos_cpu_suspend(unsigned long arg)
296 exynos_flush_cache_all();
297 return exynos_cpu_do_idle();
300 static int exynos3250_cpu_suspend(unsigned long arg)
303 return exynos_cpu_do_idle();
306 static int exynos5420_cpu_suspend(unsigned long arg)
308 /* MCPM works with HW CPU identifiers */
309 unsigned int mpidr = read_cpuid_mpidr();
310 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
311 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
313 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
315 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
316 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
320 pr_info("Failed to suspend the system\n");
322 /* return value != 0 means failure */
326 static void exynos_pm_set_wakeup_mask(void)
328 /* Set wake-up mask registers */
329 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
330 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
333 static void exynos_pm_enter_sleep_mode(void)
335 /* Set value of power down register for sleep mode */
336 exynos_sys_powerdown_conf(SYS_SLEEP);
337 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
340 static void exynos_pm_prepare(void)
342 exynos_set_delayed_reset_assertion(false);
344 /* Set wake-up mask registers */
345 exynos_pm_set_wakeup_mask();
347 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
349 exynos_pm_enter_sleep_mode();
351 /* ensure at least INFORM0 has the resume address */
352 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
355 static void exynos3250_pm_prepare(void)
359 /* Set wake-up mask registers */
360 exynos_pm_set_wakeup_mask();
362 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
363 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
364 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
366 exynos_pm_enter_sleep_mode();
368 /* ensure at least INFORM0 has the resume address */
369 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
372 static void exynos5420_pm_prepare(void)
376 /* Set wake-up mask registers */
377 exynos_pm_set_wakeup_mask();
379 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
381 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
383 * The cpu state needs to be saved and restored so that the
384 * secondary CPUs will enter low power start. Though the U-Boot
385 * is setting the cpu state with low power flag, the kernel
386 * needs to restore it back in case, the primary cpu fails to
387 * suspend for any reason.
389 exynos5420_cpu_state = __raw_readl(sysram_base_addr +
390 EXYNOS5420_CPU_STATE);
392 exynos_pm_enter_sleep_mode();
394 /* ensure at least INFORM0 has the resume address */
395 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
396 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
398 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
399 tmp &= ~EXYNOS5_USE_RETENTION;
400 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
402 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
403 tmp |= EXYNOS5420_UFS;
404 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
406 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
407 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
408 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
410 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
411 tmp |= EXYNOS5420_EMULATION;
412 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
414 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
415 tmp |= EXYNOS5420_EMULATION;
416 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
420 static int exynos_pm_suspend(void)
422 exynos_pm_central_suspend();
424 /* Setting SEQ_OPTION register */
425 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
426 S5P_CENTRAL_SEQ_OPTION);
428 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
429 exynos_cpu_save_register();
434 static int exynos5420_pm_suspend(void)
438 exynos_pm_central_suspend();
440 /* Setting SEQ_OPTION register */
442 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
444 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
445 S5P_CENTRAL_SEQ_OPTION);
447 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
448 S5P_CENTRAL_SEQ_OPTION);
452 static void exynos_pm_release_retention(void)
456 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
457 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
458 pm_data->release_ret_regs[i]);
461 static void exynos_pm_resume(void)
463 u32 cpuid = read_cpuid_part();
465 if (exynos_pm_central_resume())
468 /* For release retention */
469 exynos_pm_release_retention();
471 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
473 if (cpuid == ARM_CPU_PART_CORTEX_A9)
474 scu_enable(S5P_VA_SCU);
476 if (call_firmware_op(resume) == -ENOSYS
477 && cpuid == ARM_CPU_PART_CORTEX_A9)
478 exynos_cpu_restore_register();
482 /* Clear SLEEP mode set in INFORM1 */
483 pmu_raw_writel(0x0, S5P_INFORM1);
484 exynos_set_delayed_reset_assertion(true);
487 static void exynos3250_pm_resume(void)
489 u32 cpuid = read_cpuid_part();
491 if (exynos_pm_central_resume())
494 /* For release retention */
495 exynos_pm_release_retention();
497 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
499 if (call_firmware_op(resume) == -ENOSYS
500 && cpuid == ARM_CPU_PART_CORTEX_A9)
501 exynos_cpu_restore_register();
505 /* Clear SLEEP mode set in INFORM1 */
506 pmu_raw_writel(0x0, S5P_INFORM1);
509 static void exynos5420_prepare_pm_resume(void)
511 unsigned int mpidr, cluster;
513 mpidr = read_cpuid_mpidr();
514 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
516 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
517 WARN_ON(mcpm_cpu_powered_up());
519 if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
521 * When system is resumed on the LITTLE/KFC core (cluster 1),
522 * the DSCR is not properly updated until the power is turned
523 * on also for the cluster 0. Enable it for a while to
524 * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
525 * block and avoid undefined instruction issue on CP14 reset.
527 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
528 EXYNOS_COMMON_CONFIGURATION(0));
530 EXYNOS_COMMON_CONFIGURATION(0));
534 static void exynos5420_pm_resume(void)
538 /* Restore the CPU0 low power state register */
539 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
540 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
541 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
543 /* Restore the sysram cpu state register */
544 __raw_writel(exynos5420_cpu_state,
545 sysram_base_addr + EXYNOS5420_CPU_STATE);
547 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
548 S5P_CENTRAL_SEQ_OPTION);
550 if (exynos_pm_central_resume())
553 /* For release retention */
554 exynos_pm_release_retention();
556 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
558 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
562 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
563 tmp &= ~EXYNOS5420_UFS;
564 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
566 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
567 tmp &= ~EXYNOS5420_EMULATION;
568 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
570 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
571 tmp &= ~EXYNOS5420_EMULATION;
572 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
574 /* Clear SLEEP mode set in INFORM1 */
575 pmu_raw_writel(0x0, S5P_INFORM1);
582 static int exynos_suspend_enter(suspend_state_t state)
588 S3C_PMDBG("%s: suspending the system...\n", __func__);
590 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
591 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
593 if (exynos_irqwake_intmask == -1U
594 && exynos_get_eint_wake_mask() == -1U) {
595 pr_err("%s: No wake-up sources!\n", __func__);
596 pr_err("%s: Aborting sleep\n", __func__);
601 if (pm_data->pm_prepare)
602 pm_data->pm_prepare();
604 s3c_pm_check_store();
606 ret = call_firmware_op(suspend);
608 ret = cpu_suspend(0, pm_data->cpu_suspend);
612 if (pm_data->pm_resume_prepare)
613 pm_data->pm_resume_prepare();
614 s3c_pm_restore_uarts();
616 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
617 pmu_raw_readl(S5P_WAKEUP_STAT));
619 s3c_pm_check_restore();
621 S3C_PMDBG("%s: resuming the system...\n", __func__);
626 static int exynos_suspend_prepare(void)
631 * REVISIT: It would be better if struct platform_suspend_ops
632 * .prepare handler get the suspend_state_t as a parameter to
633 * avoid hard-coding the suspend to mem state. It's safe to do
634 * it now only because the suspend_valid_only_mem function is
635 * used as the .valid callback used to check if a given state
636 * is supported by the platform anyways.
638 ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
640 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
644 s3c_pm_check_prepare();
649 static void exynos_suspend_finish(void)
653 s3c_pm_check_cleanup();
655 ret = regulator_suspend_finish();
657 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
660 static const struct platform_suspend_ops exynos_suspend_ops = {
661 .enter = exynos_suspend_enter,
662 .prepare = exynos_suspend_prepare,
663 .finish = exynos_suspend_finish,
664 .valid = suspend_valid_only_mem,
667 static const struct exynos_pm_data exynos3250_pm_data = {
668 .wkup_irq = exynos3250_wkup_irq,
669 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
670 .release_ret_regs = exynos3250_release_ret_regs,
671 .pm_suspend = exynos_pm_suspend,
672 .pm_resume = exynos3250_pm_resume,
673 .pm_prepare = exynos3250_pm_prepare,
674 .cpu_suspend = exynos3250_cpu_suspend,
677 static const struct exynos_pm_data exynos4_pm_data = {
678 .wkup_irq = exynos4_wkup_irq,
679 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
680 .release_ret_regs = exynos_release_ret_regs,
681 .pm_suspend = exynos_pm_suspend,
682 .pm_resume = exynos_pm_resume,
683 .pm_prepare = exynos_pm_prepare,
684 .cpu_suspend = exynos_cpu_suspend,
687 static const struct exynos_pm_data exynos5250_pm_data = {
688 .wkup_irq = exynos5250_wkup_irq,
689 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
690 .release_ret_regs = exynos_release_ret_regs,
691 .pm_suspend = exynos_pm_suspend,
692 .pm_resume = exynos_pm_resume,
693 .pm_prepare = exynos_pm_prepare,
694 .cpu_suspend = exynos_cpu_suspend,
697 static const struct exynos_pm_data exynos5420_pm_data = {
698 .wkup_irq = exynos5250_wkup_irq,
699 .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
700 .release_ret_regs = exynos5420_release_ret_regs,
701 .pm_resume_prepare = exynos5420_prepare_pm_resume,
702 .pm_resume = exynos5420_pm_resume,
703 .pm_suspend = exynos5420_pm_suspend,
704 .pm_prepare = exynos5420_pm_prepare,
705 .cpu_suspend = exynos5420_cpu_suspend,
708 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
710 .compatible = "samsung,exynos3250-pmu",
711 .data = &exynos3250_pm_data,
713 .compatible = "samsung,exynos4210-pmu",
714 .data = &exynos4_pm_data,
716 .compatible = "samsung,exynos4212-pmu",
717 .data = &exynos4_pm_data,
719 .compatible = "samsung,exynos4412-pmu",
720 .data = &exynos4_pm_data,
722 .compatible = "samsung,exynos5250-pmu",
723 .data = &exynos5250_pm_data,
725 .compatible = "samsung,exynos5420-pmu",
726 .data = &exynos5420_pm_data,
731 static struct syscore_ops exynos_pm_syscore_ops;
733 void __init exynos_pm_init(void)
735 const struct of_device_id *match;
736 struct device_node *np;
739 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
741 pr_err("Failed to find PMU node\n");
745 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
746 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
752 pm_data = (const struct exynos_pm_data *) match->data;
754 /* All wakeup disable */
755 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
756 tmp |= pm_data->wake_disable_mask;
757 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
759 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
760 exynos_pm_syscore_ops.resume = pm_data->pm_resume;
762 register_syscore_ops(&exynos_pm_syscore_ops);
763 suspend_set_ops(&exynos_suspend_ops);