2 * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
6 * This file add support for MD5 and SHA1.
8 * You could find the datasheet in Documentation/arm/sunxi/README
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/scatterlist.h>
18 /* This is a totally arbitrary value */
19 #define SS_TIMEOUT 100
21 int sun4i_hash_crainit(struct crypto_tfm *tfm)
23 struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
24 struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
25 struct sun4i_ss_alg_template *algt;
27 memset(op, 0, sizeof(struct sun4i_tfm_ctx));
29 algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
32 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
33 sizeof(struct sun4i_req_ctx));
37 /* sun4i_hash_init: initialize request context */
38 int sun4i_hash_init(struct ahash_request *areq)
40 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
41 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
42 struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
43 struct sun4i_ss_alg_template *algt;
45 memset(op, 0, sizeof(struct sun4i_req_ctx));
47 algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
48 op->mode = algt->mode;
53 int sun4i_hash_export_md5(struct ahash_request *areq, void *out)
55 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
56 struct md5_state *octx = out;
59 octx->byte_count = op->byte_count + op->len;
61 memcpy(octx->block, op->buf, op->len);
63 if (op->byte_count > 0) {
64 for (i = 0; i < 4; i++)
65 octx->hash[i] = op->hash[i];
67 octx->hash[0] = SHA1_H0;
68 octx->hash[1] = SHA1_H1;
69 octx->hash[2] = SHA1_H2;
70 octx->hash[3] = SHA1_H3;
76 int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
78 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
79 const struct md5_state *ictx = in;
82 sun4i_hash_init(areq);
84 op->byte_count = ictx->byte_count & ~0x3F;
85 op->len = ictx->byte_count & 0x3F;
87 memcpy(op->buf, ictx->block, op->len);
89 for (i = 0; i < 4; i++)
90 op->hash[i] = ictx->hash[i];
95 int sun4i_hash_export_sha1(struct ahash_request *areq, void *out)
97 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
98 struct sha1_state *octx = out;
101 octx->count = op->byte_count + op->len;
103 memcpy(octx->buffer, op->buf, op->len);
105 if (op->byte_count > 0) {
106 for (i = 0; i < 5; i++)
107 octx->state[i] = op->hash[i];
109 octx->state[0] = SHA1_H0;
110 octx->state[1] = SHA1_H1;
111 octx->state[2] = SHA1_H2;
112 octx->state[3] = SHA1_H3;
113 octx->state[4] = SHA1_H4;
119 int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
121 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
122 const struct sha1_state *ictx = in;
125 sun4i_hash_init(areq);
127 op->byte_count = ictx->count & ~0x3F;
128 op->len = ictx->count & 0x3F;
130 memcpy(op->buf, ictx->buffer, op->len);
132 for (i = 0; i < 5; i++)
133 op->hash[i] = ictx->state[i];
138 #define SS_HASH_UPDATE 1
139 #define SS_HASH_FINAL 2
142 * sun4i_hash_update: update hash engine
144 * Could be used for both SHA1 and MD5
145 * Write data by step of 32bits and put then in the SS.
147 * Since we cannot leave partial data and hash state in the engine,
148 * we need to get the hash state at the end of this function.
149 * We can get the hash state every 64 bytes
151 * So the first work is to get the number of bytes to write to SS modulo 64
152 * The extra bytes will go to a temporary buffer op->buf storing op->len bytes
154 * So at the begin of update()
155 * if op->len + areq->nbytes < 64
156 * => all data will be written to wait buffer (op->buf) and end=0
157 * if not, write all data from op->buf to the device and position end to
158 * complete to 64bytes
161 * update1 60o => op->len=60
162 * update2 60o => need one more word to have 64 bytes
164 * so write all data from op->buf and one word of SGs
165 * write remaining data in op->buf
166 * final state op->len=56
168 static int sun4i_hash(struct ahash_request *areq)
173 * i is the total bytes read from SGs, to be compared to areq->nbytes
174 * i is important because we cannot rely on SG length since the sum of
175 * SG->length could be greater than areq->nbytes
178 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
179 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
180 struct sun4i_tfm_ctx *tfmctx = crypto_ahash_ctx(tfm);
181 struct sun4i_ss_ctx *ss = tfmctx->ss;
182 unsigned int in_i = 0; /* advancement in the current SG */
185 * end is the position when we need to stop writing to the device,
186 * to be compared to i
190 u32 spaces, rx_cnt = SS_RX_DEFAULT;
192 struct sg_mapping_iter mi;
195 unsigned int index, padlen;
199 unsigned int nwait, nbw = 0;
200 struct scatterlist *in_sg = areq->src;
202 dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
203 __func__, crypto_tfm_alg_name(areq->base.tfm),
204 op->byte_count, areq->nbytes, op->mode,
205 op->len, op->hash[0]);
207 if (unlikely(areq->nbytes == 0) && (op->flags & SS_HASH_FINAL) == 0)
210 /* protect against overflow */
211 if (unlikely(areq->nbytes > UINT_MAX - op->len)) {
212 dev_err(ss->dev, "Cannot process too large request\n");
216 if (op->len + areq->nbytes < 64 && (op->flags & SS_HASH_FINAL) == 0) {
217 /* linearize data to op->buf */
218 copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
219 op->buf + op->len, areq->nbytes, 0);
224 spin_lock_bh(&ss->slock);
227 * if some data have been processed before,
228 * we need to restore the partial hash state
230 if (op->byte_count > 0) {
231 ivmode = SS_IV_ARBITRARY;
232 for (i = 0; i < 5; i++)
233 writel(op->hash[i], ss->base + SS_IV0 + i * 4);
235 /* Enable the device */
236 writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
238 if ((op->flags & SS_HASH_UPDATE) == 0)
241 /* start of handling data */
242 if ((op->flags & SS_HASH_FINAL) == 0) {
243 end = ((areq->nbytes + op->len) / 64) * 64 - op->len;
245 if (end > areq->nbytes || areq->nbytes - end > 63) {
246 dev_err(ss->dev, "ERROR: Bound error %u %u\n",
252 /* Since we have the flag final, we can go up to modulo 4 */
253 if (areq->nbytes < 4)
256 end = ((areq->nbytes + op->len) / 4) * 4 - op->len;
259 /* TODO if SGlen % 4 and op->len == 0 then DMA */
261 while (in_sg && i == 1) {
262 if ((in_sg->length % 4) != 0)
264 in_sg = sg_next(in_sg);
266 if (i == 1 && op->len == 0)
267 dev_dbg(ss->dev, "We can DMA\n");
270 sg_miter_start(&mi, areq->src, sg_nents(areq->src),
271 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
277 * we need to linearize in two case:
278 * - the buffer is already used
279 * - the SG does not have enough byte remaining ( < 4)
281 if (op->len > 0 || (mi.length - in_i) < 4) {
283 * if we have entered here we have two reason to stop
284 * - the buffer is full
287 while (op->len < 64 && i < end) {
288 /* how many bytes we can read from current SG */
289 in_r = min(end - i, 64 - op->len);
290 in_r = min_t(size_t, mi.length - in_i, in_r);
291 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
295 if (in_i == mi.length) {
300 if (op->len > 3 && (op->len % 4) == 0) {
301 /* write buf to the device */
302 writesl(ss->base + SS_RXFIFO, op->buf,
304 op->byte_count += op->len;
308 if (mi.length - in_i > 3 && i < end) {
309 /* how many bytes we can read from current SG */
310 in_r = min_t(size_t, mi.length - in_i, areq->nbytes - i);
311 in_r = min_t(size_t, ((mi.length - in_i) / 4) * 4, in_r);
312 /* how many bytes we can write in the device*/
313 todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
314 writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
315 op->byte_count += todo * 4;
320 spaces = readl(ss->base + SS_FCSR);
321 rx_cnt = SS_RXFIFO_SPACES(spaces);
323 if (in_i == mi.length) {
331 * Now we have written to the device all that we can,
332 * store the remaining bytes in op->buf
334 if ((areq->nbytes - i) < 64) {
335 while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
336 /* how many bytes we can read from current SG */
337 in_r = min(areq->nbytes - i, 64 - op->len);
338 in_r = min_t(size_t, mi.length - in_i, in_r);
339 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
343 if (in_i == mi.length) {
353 * End of data process
354 * Now if we have the flag final go to finalize part
355 * If not, store the partial hash
357 if ((op->flags & SS_HASH_FINAL) > 0)
360 writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
363 v = readl(ss->base + SS_CTL);
365 } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
366 if (unlikely(i >= SS_TIMEOUT)) {
367 dev_err_ratelimited(ss->dev,
368 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
369 i, SS_TIMEOUT, v, areq->nbytes);
374 for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
375 op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
380 * hash_final: finalize hashing operation
382 * If we have some remaining bytes, we write them.
383 * Then ask the SS for finalizing the hashing operation
385 * I do not check RX FIFO size in this function since the size is 32
386 * after each enabling and this function neither write more than 32 words.
387 * If we come from the update part, we cannot have more than
388 * 3 remaining bytes to write and SS is fast enough to not care about it.
393 /* write the remaining words of the wait buffer */
397 writesl(ss->base + SS_RXFIFO, op->buf, nwait);
398 op->byte_count += 4 * nwait;
400 nbw = op->len - 4 * nwait;
401 wb = *(u32 *)(op->buf + nwait * 4);
402 wb &= (0xFFFFFFFF >> (4 - nbw) * 8);
405 /* write the remaining bytes of the nbw buffer */
407 wb |= ((1 << 7) << (nbw * 8));
414 * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
415 * I take the operations from other MD5/SHA1 implementations
418 /* we have already send 4 more byte of which nbw data */
419 if (op->mode == SS_OP_MD5) {
420 index = (op->byte_count + 4) & 0x3f;
421 op->byte_count += nbw;
423 zeros = (120 - index) / 4;
425 zeros = (56 - index) / 4;
427 op->byte_count += nbw;
428 index = op->byte_count & 0x3f;
429 padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
430 zeros = (padlen - 1) / 4;
433 memset(bf + j, 0, 4 * zeros);
436 /* write the length of data */
437 if (op->mode == SS_OP_SHA1) {
438 bits = cpu_to_be64(op->byte_count << 3);
439 bf[j++] = bits & 0xffffffff;
440 bf[j++] = (bits >> 32) & 0xffffffff;
442 bf[j++] = (op->byte_count << 3) & 0xffffffff;
443 bf[j++] = (op->byte_count >> 29) & 0xffffffff;
445 writesl(ss->base + SS_RXFIFO, bf, j);
447 /* Tell the SS to stop the hashing */
448 writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
451 * Wait for SS to finish the hash.
452 * The timeout could happen only in case of bad overclocking
457 v = readl(ss->base + SS_CTL);
459 } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
460 if (unlikely(i >= SS_TIMEOUT)) {
461 dev_err_ratelimited(ss->dev,
462 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
463 i, SS_TIMEOUT, v, areq->nbytes);
468 /* Get the hash from the device */
469 if (op->mode == SS_OP_SHA1) {
470 for (i = 0; i < 5; i++) {
471 v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
472 memcpy(areq->result + i * 4, &v, 4);
475 for (i = 0; i < 4; i++) {
476 v = readl(ss->base + SS_MD0 + i * 4);
477 memcpy(areq->result + i * 4, &v, 4);
482 writel(0, ss->base + SS_CTL);
483 spin_unlock_bh(&ss->slock);
487 int sun4i_hash_final(struct ahash_request *areq)
489 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
491 op->flags = SS_HASH_FINAL;
492 return sun4i_hash(areq);
495 int sun4i_hash_update(struct ahash_request *areq)
497 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
499 op->flags = SS_HASH_UPDATE;
500 return sun4i_hash(areq);
503 /* sun4i_hash_finup: finalize hashing operation after an update */
504 int sun4i_hash_finup(struct ahash_request *areq)
506 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
508 op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
509 return sun4i_hash(areq);
512 /* combo of init/update/final functions */
513 int sun4i_hash_digest(struct ahash_request *areq)
516 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
518 err = sun4i_hash_init(areq);
522 op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
523 return sun4i_hash(areq);