1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
7 * Core file which registers crypto algorithms supported by the SS.
9 * You could find a link for the datasheet in Documentation/arm/sunxi.rst
11 #include <linux/clk.h>
12 #include <linux/crypto.h>
13 #include <linux/debugfs.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <crypto/scatterwalk.h>
20 #include <linux/scatterlist.h>
21 #include <linux/interrupt.h>
22 #include <linux/delay.h>
23 #include <linux/reset.h>
27 static const struct ss_variant ss_a10_variant = {
31 static const struct ss_variant ss_a33_variant = {
35 static struct sun4i_ss_alg_template ss_algs[] = {
36 { .type = CRYPTO_ALG_TYPE_AHASH,
39 .init = sun4i_hash_init,
40 .update = sun4i_hash_update,
41 .final = sun4i_hash_final,
42 .finup = sun4i_hash_finup,
43 .digest = sun4i_hash_digest,
44 .export = sun4i_hash_export_md5,
45 .import = sun4i_hash_import_md5,
47 .digestsize = MD5_DIGEST_SIZE,
48 .statesize = sizeof(struct md5_state),
51 .cra_driver_name = "md5-sun4i-ss",
54 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
55 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
56 .cra_module = THIS_MODULE,
57 .cra_init = sun4i_hash_crainit,
58 .cra_exit = sun4i_hash_craexit,
63 { .type = CRYPTO_ALG_TYPE_AHASH,
66 .init = sun4i_hash_init,
67 .update = sun4i_hash_update,
68 .final = sun4i_hash_final,
69 .finup = sun4i_hash_finup,
70 .digest = sun4i_hash_digest,
71 .export = sun4i_hash_export_sha1,
72 .import = sun4i_hash_import_sha1,
74 .digestsize = SHA1_DIGEST_SIZE,
75 .statesize = sizeof(struct sha1_state),
78 .cra_driver_name = "sha1-sun4i-ss",
81 .cra_blocksize = SHA1_BLOCK_SIZE,
82 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
83 .cra_module = THIS_MODULE,
84 .cra_init = sun4i_hash_crainit,
85 .cra_exit = sun4i_hash_craexit,
90 { .type = CRYPTO_ALG_TYPE_SKCIPHER,
92 .setkey = sun4i_ss_aes_setkey,
93 .encrypt = sun4i_ss_cbc_aes_encrypt,
94 .decrypt = sun4i_ss_cbc_aes_decrypt,
95 .min_keysize = AES_MIN_KEY_SIZE,
96 .max_keysize = AES_MAX_KEY_SIZE,
97 .ivsize = AES_BLOCK_SIZE,
99 .cra_name = "cbc(aes)",
100 .cra_driver_name = "cbc-aes-sun4i-ss",
102 .cra_blocksize = AES_BLOCK_SIZE,
103 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
104 .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
105 .cra_module = THIS_MODULE,
107 .cra_init = sun4i_ss_cipher_init,
108 .cra_exit = sun4i_ss_cipher_exit,
112 { .type = CRYPTO_ALG_TYPE_SKCIPHER,
114 .setkey = sun4i_ss_aes_setkey,
115 .encrypt = sun4i_ss_ecb_aes_encrypt,
116 .decrypt = sun4i_ss_ecb_aes_decrypt,
117 .min_keysize = AES_MIN_KEY_SIZE,
118 .max_keysize = AES_MAX_KEY_SIZE,
120 .cra_name = "ecb(aes)",
121 .cra_driver_name = "ecb-aes-sun4i-ss",
123 .cra_blocksize = AES_BLOCK_SIZE,
124 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
125 .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
126 .cra_module = THIS_MODULE,
128 .cra_init = sun4i_ss_cipher_init,
129 .cra_exit = sun4i_ss_cipher_exit,
133 { .type = CRYPTO_ALG_TYPE_SKCIPHER,
135 .setkey = sun4i_ss_des_setkey,
136 .encrypt = sun4i_ss_cbc_des_encrypt,
137 .decrypt = sun4i_ss_cbc_des_decrypt,
138 .min_keysize = DES_KEY_SIZE,
139 .max_keysize = DES_KEY_SIZE,
140 .ivsize = DES_BLOCK_SIZE,
142 .cra_name = "cbc(des)",
143 .cra_driver_name = "cbc-des-sun4i-ss",
145 .cra_blocksize = DES_BLOCK_SIZE,
146 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
147 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
148 .cra_module = THIS_MODULE,
150 .cra_init = sun4i_ss_cipher_init,
151 .cra_exit = sun4i_ss_cipher_exit,
155 { .type = CRYPTO_ALG_TYPE_SKCIPHER,
157 .setkey = sun4i_ss_des_setkey,
158 .encrypt = sun4i_ss_ecb_des_encrypt,
159 .decrypt = sun4i_ss_ecb_des_decrypt,
160 .min_keysize = DES_KEY_SIZE,
161 .max_keysize = DES_KEY_SIZE,
163 .cra_name = "ecb(des)",
164 .cra_driver_name = "ecb-des-sun4i-ss",
166 .cra_blocksize = DES_BLOCK_SIZE,
167 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
168 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
169 .cra_module = THIS_MODULE,
171 .cra_init = sun4i_ss_cipher_init,
172 .cra_exit = sun4i_ss_cipher_exit,
176 { .type = CRYPTO_ALG_TYPE_SKCIPHER,
178 .setkey = sun4i_ss_des3_setkey,
179 .encrypt = sun4i_ss_cbc_des3_encrypt,
180 .decrypt = sun4i_ss_cbc_des3_decrypt,
181 .min_keysize = DES3_EDE_KEY_SIZE,
182 .max_keysize = DES3_EDE_KEY_SIZE,
183 .ivsize = DES3_EDE_BLOCK_SIZE,
185 .cra_name = "cbc(des3_ede)",
186 .cra_driver_name = "cbc-des3-sun4i-ss",
188 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
189 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
190 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
191 .cra_module = THIS_MODULE,
193 .cra_init = sun4i_ss_cipher_init,
194 .cra_exit = sun4i_ss_cipher_exit,
198 { .type = CRYPTO_ALG_TYPE_SKCIPHER,
200 .setkey = sun4i_ss_des3_setkey,
201 .encrypt = sun4i_ss_ecb_des3_encrypt,
202 .decrypt = sun4i_ss_ecb_des3_decrypt,
203 .min_keysize = DES3_EDE_KEY_SIZE,
204 .max_keysize = DES3_EDE_KEY_SIZE,
206 .cra_name = "ecb(des3_ede)",
207 .cra_driver_name = "ecb-des3-sun4i-ss",
209 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
210 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
211 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
212 .cra_module = THIS_MODULE,
214 .cra_init = sun4i_ss_cipher_init,
215 .cra_exit = sun4i_ss_cipher_exit,
219 #ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
221 .type = CRYPTO_ALG_TYPE_RNG,
224 .cra_name = "stdrng",
225 .cra_driver_name = "sun4i_ss_rng",
228 .cra_module = THIS_MODULE,
230 .generate = sun4i_ss_prng_generate,
231 .seed = sun4i_ss_prng_seed,
232 .seedsize = SS_SEED_LEN / BITS_PER_BYTE,
238 static int sun4i_ss_dbgfs_read(struct seq_file *seq, void *v)
242 for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
245 switch (ss_algs[i].type) {
246 case CRYPTO_ALG_TYPE_SKCIPHER:
247 seq_printf(seq, "%s %s reqs=%lu opti=%lu fallback=%lu tsize=%lu\n",
248 ss_algs[i].alg.crypto.base.cra_driver_name,
249 ss_algs[i].alg.crypto.base.cra_name,
250 ss_algs[i].stat_req, ss_algs[i].stat_opti, ss_algs[i].stat_fb,
251 ss_algs[i].stat_bytes);
253 case CRYPTO_ALG_TYPE_RNG:
254 seq_printf(seq, "%s %s reqs=%lu tsize=%lu\n",
255 ss_algs[i].alg.rng.base.cra_driver_name,
256 ss_algs[i].alg.rng.base.cra_name,
257 ss_algs[i].stat_req, ss_algs[i].stat_bytes);
259 case CRYPTO_ALG_TYPE_AHASH:
260 seq_printf(seq, "%s %s reqs=%lu\n",
261 ss_algs[i].alg.hash.halg.base.cra_driver_name,
262 ss_algs[i].alg.hash.halg.base.cra_name,
263 ss_algs[i].stat_req);
270 static int sun4i_ss_dbgfs_open(struct inode *inode, struct file *file)
272 return single_open(file, sun4i_ss_dbgfs_read, inode->i_private);
275 static const struct file_operations sun4i_ss_debugfs_fops = {
276 .owner = THIS_MODULE,
277 .open = sun4i_ss_dbgfs_open,
280 .release = single_release,
284 * Power management strategy: The device is suspended unless a TFM exists for
285 * one of the algorithms proposed by this driver.
287 static int sun4i_ss_pm_suspend(struct device *dev)
289 struct sun4i_ss_ctx *ss = dev_get_drvdata(dev);
291 reset_control_assert(ss->reset);
293 clk_disable_unprepare(ss->ssclk);
294 clk_disable_unprepare(ss->busclk);
298 static int sun4i_ss_pm_resume(struct device *dev)
300 struct sun4i_ss_ctx *ss = dev_get_drvdata(dev);
304 err = clk_prepare_enable(ss->busclk);
306 dev_err(ss->dev, "Cannot prepare_enable busclk\n");
310 err = clk_prepare_enable(ss->ssclk);
312 dev_err(ss->dev, "Cannot prepare_enable ssclk\n");
316 err = reset_control_deassert(ss->reset);
318 dev_err(ss->dev, "Cannot deassert reset control\n");
324 sun4i_ss_pm_suspend(dev);
328 static const struct dev_pm_ops sun4i_ss_pm_ops = {
329 SET_RUNTIME_PM_OPS(sun4i_ss_pm_suspend, sun4i_ss_pm_resume, NULL)
333 * When power management is enabled, this function enables the PM and set the
334 * device as suspended
335 * When power management is disabled, this function just enables the device
337 static int sun4i_ss_pm_init(struct sun4i_ss_ctx *ss)
341 pm_runtime_use_autosuspend(ss->dev);
342 pm_runtime_set_autosuspend_delay(ss->dev, 2000);
344 err = pm_runtime_set_suspended(ss->dev);
347 pm_runtime_enable(ss->dev);
351 static void sun4i_ss_pm_exit(struct sun4i_ss_ctx *ss)
353 pm_runtime_disable(ss->dev);
356 static int sun4i_ss_probe(struct platform_device *pdev)
361 const unsigned long cr_ahb = 24 * 1000 * 1000;
362 const unsigned long cr_mod = 150 * 1000 * 1000;
363 struct sun4i_ss_ctx *ss;
365 if (!pdev->dev.of_node)
368 ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
372 ss->base = devm_platform_ioremap_resource(pdev, 0);
373 if (IS_ERR(ss->base)) {
374 dev_err(&pdev->dev, "Cannot request MMIO\n");
375 return PTR_ERR(ss->base);
378 ss->variant = of_device_get_match_data(&pdev->dev);
380 dev_err(&pdev->dev, "Missing Security System variant\n");
384 ss->ssclk = devm_clk_get(&pdev->dev, "mod");
385 if (IS_ERR(ss->ssclk)) {
386 err = PTR_ERR(ss->ssclk);
387 dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
390 dev_dbg(&pdev->dev, "clock ss acquired\n");
392 ss->busclk = devm_clk_get(&pdev->dev, "ahb");
393 if (IS_ERR(ss->busclk)) {
394 err = PTR_ERR(ss->busclk);
395 dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
398 dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
400 ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
401 if (IS_ERR(ss->reset))
402 return PTR_ERR(ss->reset);
404 dev_info(&pdev->dev, "no reset control found\n");
407 * Check that clock have the correct rates given in the datasheet
408 * Try to set the clock to the maximum allowed
410 err = clk_set_rate(ss->ssclk, cr_mod);
412 dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
417 * The only impact on clocks below requirement are bad performance,
418 * so do not print "errors"
419 * warn on Overclocked clocks
421 cr = clk_get_rate(ss->busclk);
423 dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
424 cr, cr / 1000000, cr_ahb);
426 dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
427 cr, cr / 1000000, cr_ahb);
429 cr = clk_get_rate(ss->ssclk);
432 dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
433 cr, cr / 1000000, cr_mod);
435 dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
436 cr, cr / 1000000, cr_mod);
438 dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
439 cr, cr / 1000000, cr_mod);
441 ss->dev = &pdev->dev;
442 platform_set_drvdata(pdev, ss);
444 spin_lock_init(&ss->slock);
446 err = sun4i_ss_pm_init(ss);
451 * Datasheet named it "Die Bonding ID"
452 * I expect to be a sort of Security System Revision number.
453 * Since the A80 seems to have an other version of SS
454 * this info could be useful
457 err = pm_runtime_resume_and_get(ss->dev);
461 writel(SS_ENABLED, ss->base + SS_CTL);
462 v = readl(ss->base + SS_CTL);
465 dev_info(&pdev->dev, "Die ID %d\n", v);
466 writel(0, ss->base + SS_CTL);
468 pm_runtime_put_sync(ss->dev);
470 for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
472 switch (ss_algs[i].type) {
473 case CRYPTO_ALG_TYPE_SKCIPHER:
474 err = crypto_register_skcipher(&ss_algs[i].alg.crypto);
476 dev_err(ss->dev, "Fail to register %s\n",
477 ss_algs[i].alg.crypto.base.cra_name);
481 case CRYPTO_ALG_TYPE_AHASH:
482 err = crypto_register_ahash(&ss_algs[i].alg.hash);
484 dev_err(ss->dev, "Fail to register %s\n",
485 ss_algs[i].alg.hash.halg.base.cra_name);
489 case CRYPTO_ALG_TYPE_RNG:
490 err = crypto_register_rng(&ss_algs[i].alg.rng);
492 dev_err(ss->dev, "Fail to register %s\n",
493 ss_algs[i].alg.rng.base.cra_name);
499 /* Ignore error of debugfs */
500 ss->dbgfs_dir = debugfs_create_dir("sun4i-ss", NULL);
501 ss->dbgfs_stats = debugfs_create_file("stats", 0444, ss->dbgfs_dir, ss,
502 &sun4i_ss_debugfs_fops);
507 for (; i >= 0; i--) {
508 switch (ss_algs[i].type) {
509 case CRYPTO_ALG_TYPE_SKCIPHER:
510 crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
512 case CRYPTO_ALG_TYPE_AHASH:
513 crypto_unregister_ahash(&ss_algs[i].alg.hash);
515 case CRYPTO_ALG_TYPE_RNG:
516 crypto_unregister_rng(&ss_algs[i].alg.rng);
521 sun4i_ss_pm_exit(ss);
525 static int sun4i_ss_remove(struct platform_device *pdev)
528 struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
530 for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
531 switch (ss_algs[i].type) {
532 case CRYPTO_ALG_TYPE_SKCIPHER:
533 crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
535 case CRYPTO_ALG_TYPE_AHASH:
536 crypto_unregister_ahash(&ss_algs[i].alg.hash);
538 case CRYPTO_ALG_TYPE_RNG:
539 crypto_unregister_rng(&ss_algs[i].alg.rng);
544 sun4i_ss_pm_exit(ss);
548 static const struct of_device_id a20ss_crypto_of_match_table[] = {
549 { .compatible = "allwinner,sun4i-a10-crypto",
550 .data = &ss_a10_variant
552 { .compatible = "allwinner,sun8i-a33-crypto",
553 .data = &ss_a33_variant
557 MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
559 static struct platform_driver sun4i_ss_driver = {
560 .probe = sun4i_ss_probe,
561 .remove = sun4i_ss_remove,
564 .pm = &sun4i_ss_pm_ops,
565 .of_match_table = a20ss_crypto_of_match_table,
569 module_platform_driver(sun4i_ss_driver);
571 MODULE_ALIAS("platform:sun4i-ss");
572 MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
573 MODULE_LICENSE("GPL");
574 MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");