1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
8 #include "odm_precomp.h"
14 static u32 array_agc_tab_1t_8188e[] = {
145 static bool set_baseband_agc_config(struct adapter *adapt)
148 const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
149 u32 *array = array_agc_tab_1t_8188e;
151 for (i = 0; i < arraylen; i += 2) {
153 u32 v2 = array[i + 1];
155 if (v1 < 0xCDCDCDCD) {
156 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
165 static u32 array_phy_reg_1t_8188e[] = {
359 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
363 } else if (addr == 0xfd) {
365 } else if (addr == 0xfc) {
367 } else if (addr == 0xfb) {
369 } else if (addr == 0xfa) {
371 } else if (addr == 0xf9) {
374 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
375 /* Add 1us delay between BB/RF register setting. */
380 static bool set_baseband_phy_config(struct adapter *adapt)
383 const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
384 u32 *array = array_phy_reg_1t_8188e;
386 for (i = 0; i < arraylen; i += 2) {
388 u32 v2 = array[i + 1];
391 rtl_bb_delay(adapt, v1, v2);
398 static u32 array_phy_reg_pg_8188e[] = {
399 0xE00, 0xFFFFFFFF, 0x06070809,
400 0xE04, 0xFFFFFFFF, 0x02020405,
401 0xE08, 0x0000FF00, 0x00000006,
402 0x86C, 0xFFFFFF00, 0x00020400,
403 0xE10, 0xFFFFFFFF, 0x08090A0B,
404 0xE14, 0xFFFFFFFF, 0x01030607,
405 0xE18, 0xFFFFFFFF, 0x08090A0B,
406 0xE1C, 0xFFFFFFFF, 0x01030607,
407 0xE00, 0xFFFFFFFF, 0x00000000,
408 0xE04, 0xFFFFFFFF, 0x00000000,
409 0xE08, 0x0000FF00, 0x00000000,
410 0x86C, 0xFFFFFF00, 0x00000000,
411 0xE10, 0xFFFFFFFF, 0x00000000,
412 0xE14, 0xFFFFFFFF, 0x00000000,
413 0xE18, 0xFFFFFFFF, 0x00000000,
414 0xE1C, 0xFFFFFFFF, 0x00000000,
415 0xE00, 0xFFFFFFFF, 0x02020202,
416 0xE04, 0xFFFFFFFF, 0x00020202,
417 0xE08, 0x0000FF00, 0x00000000,
418 0x86C, 0xFFFFFF00, 0x00000000,
419 0xE10, 0xFFFFFFFF, 0x04040404,
420 0xE14, 0xFFFFFFFF, 0x00020404,
421 0xE18, 0xFFFFFFFF, 0x00000000,
422 0xE1C, 0xFFFFFFFF, 0x00000000,
423 0xE00, 0xFFFFFFFF, 0x02020202,
424 0xE04, 0xFFFFFFFF, 0x00020202,
425 0xE08, 0x0000FF00, 0x00000000,
426 0x86C, 0xFFFFFF00, 0x00000000,
427 0xE10, 0xFFFFFFFF, 0x04040404,
428 0xE14, 0xFFFFFFFF, 0x00020404,
429 0xE18, 0xFFFFFFFF, 0x00000000,
430 0xE1C, 0xFFFFFFFF, 0x00000000,
431 0xE00, 0xFFFFFFFF, 0x00000000,
432 0xE04, 0xFFFFFFFF, 0x00000000,
433 0xE08, 0x0000FF00, 0x00000000,
434 0x86C, 0xFFFFFF00, 0x00000000,
435 0xE10, 0xFFFFFFFF, 0x00000000,
436 0xE14, 0xFFFFFFFF, 0x00000000,
437 0xE18, 0xFFFFFFFF, 0x00000000,
438 0xE1C, 0xFFFFFFFF, 0x00000000,
439 0xE00, 0xFFFFFFFF, 0x02020202,
440 0xE04, 0xFFFFFFFF, 0x00020202,
441 0xE08, 0x0000FF00, 0x00000000,
442 0x86C, 0xFFFFFF00, 0x00000000,
443 0xE10, 0xFFFFFFFF, 0x04040404,
444 0xE14, 0xFFFFFFFF, 0x00020404,
445 0xE18, 0xFFFFFFFF, 0x00000000,
446 0xE1C, 0xFFFFFFFF, 0x00000000,
447 0xE00, 0xFFFFFFFF, 0x00000000,
448 0xE04, 0xFFFFFFFF, 0x00000000,
449 0xE08, 0x0000FF00, 0x00000000,
450 0x86C, 0xFFFFFF00, 0x00000000,
451 0xE10, 0xFFFFFFFF, 0x00000000,
452 0xE14, 0xFFFFFFFF, 0x00000000,
453 0xE18, 0xFFFFFFFF, 0x00000000,
454 0xE1C, 0xFFFFFFFF, 0x00000000,
455 0xE00, 0xFFFFFFFF, 0x00000000,
456 0xE04, 0xFFFFFFFF, 0x00000000,
457 0xE08, 0x0000FF00, 0x00000000,
458 0x86C, 0xFFFFFF00, 0x00000000,
459 0xE10, 0xFFFFFFFF, 0x00000000,
460 0xE14, 0xFFFFFFFF, 0x00000000,
461 0xE18, 0xFFFFFFFF, 0x00000000,
462 0xE1C, 0xFFFFFFFF, 0x00000000,
463 0xE00, 0xFFFFFFFF, 0x00000000,
464 0xE04, 0xFFFFFFFF, 0x00000000,
465 0xE08, 0x0000FF00, 0x00000000,
466 0x86C, 0xFFFFFF00, 0x00000000,
467 0xE10, 0xFFFFFFFF, 0x00000000,
468 0xE14, 0xFFFFFFFF, 0x00000000,
469 0xE18, 0xFFFFFFFF, 0x00000000,
470 0xE1C, 0xFFFFFFFF, 0x00000000,
471 0xE00, 0xFFFFFFFF, 0x00000000,
472 0xE04, 0xFFFFFFFF, 0x00000000,
473 0xE08, 0x0000FF00, 0x00000000,
474 0x86C, 0xFFFFFF00, 0x00000000,
475 0xE10, 0xFFFFFFFF, 0x00000000,
476 0xE14, 0xFFFFFFFF, 0x00000000,
477 0xE18, 0xFFFFFFFF, 0x00000000,
478 0xE1C, 0xFFFFFFFF, 0x00000000,
479 0xE00, 0xFFFFFFFF, 0x00000000,
480 0xE04, 0xFFFFFFFF, 0x00000000,
481 0xE08, 0x0000FF00, 0x00000000,
482 0x86C, 0xFFFFFF00, 0x00000000,
483 0xE10, 0xFFFFFFFF, 0x00000000,
484 0xE14, 0xFFFFFFFF, 0x00000000,
485 0xE18, 0xFFFFFFFF, 0x00000000,
486 0xE1C, 0xFFFFFFFF, 0x00000000,
490 static void store_pwrindex_offset(struct adapter *adapter,
491 u32 regaddr, u32 bitmask, u32 data)
493 struct hal_data_8188e *hal_data = adapter->HalData;
494 u32 * const power_level_offset =
495 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
497 if (regaddr == rTxAGC_A_Rate18_06)
498 power_level_offset[0] = data;
499 if (regaddr == rTxAGC_A_Rate54_24)
500 power_level_offset[1] = data;
501 if (regaddr == rTxAGC_A_CCK1_Mcs32)
502 power_level_offset[6] = data;
503 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
504 power_level_offset[7] = data;
505 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
506 power_level_offset[2] = data;
507 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
508 power_level_offset[3] = data;
509 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
510 power_level_offset[4] = data;
511 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
512 power_level_offset[5] = data;
513 hal_data->pwrGroupCnt++;
515 if (regaddr == rTxAGC_B_Rate18_06)
516 power_level_offset[8] = data;
517 if (regaddr == rTxAGC_B_Rate54_24)
518 power_level_offset[9] = data;
519 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
520 power_level_offset[14] = data;
521 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
522 power_level_offset[15] = data;
523 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
524 power_level_offset[10] = data;
525 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
526 power_level_offset[11] = data;
527 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
528 power_level_offset[12] = data;
529 if (regaddr == rTxAGC_B_Mcs15_Mcs12)
530 power_level_offset[13] = data;
533 static void rtl_addr_delay(struct adapter *adapt,
534 u32 addr, u32 bit_mask, u32 data)
556 store_pwrindex_offset(adapt, addr, bit_mask, data);
560 static bool config_bb_with_pgheader(struct adapter *adapt)
563 const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
564 u32 *array = array_phy_reg_pg_8188e;
566 for (i = 0; i < arraylen; i += 3) {
568 u32 v2 = array[i + 1];
569 u32 v3 = array[i + 2];
572 rtl_addr_delay(adapt, v1, v2, v3);
577 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
579 struct bb_reg_def *reg[4];
581 reg[RF_PATH_A] = &adapter->HalData->PHYRegDef[RF_PATH_A];
582 reg[RF_PATH_B] = &adapter->HalData->PHYRegDef[RF_PATH_B];
584 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
585 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
587 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
588 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
590 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
591 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
593 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
594 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
596 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
597 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
599 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
600 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
602 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
603 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
605 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
606 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
608 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
609 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
611 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
612 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
614 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
615 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
617 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
618 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
620 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
621 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
623 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
624 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
626 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
627 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
629 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
630 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
632 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
633 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
635 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
636 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
639 static bool config_parafile(struct adapter *adapt)
641 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
643 set_baseband_phy_config(adapt);
645 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
646 if (!eeprom->bautoload_fail_flag) {
647 adapt->HalData->pwrGroupCnt = 0;
648 config_bb_with_pgheader(adapt);
650 set_baseband_agc_config(adapt);
654 bool rtl88eu_phy_bb_config(struct adapter *adapt)
660 rtl88e_phy_init_bb_rf_register_definition(adapt);
662 /* Enable BB and RF */
663 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
664 usb_write16(adapt, REG_SYS_FUNC_EN,
665 (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
667 usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
669 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
670 FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
672 /* Config BB and AGC */
673 rtstatus = config_parafile(adapt);
675 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
676 crystal_cap = adapt->HalData->CrystalCap & 0x3F;
677 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
678 (crystal_cap | (crystal_cap << 6)));