1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016-2017 NXP
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/etherdevice.h>
9 #include <linux/of_net.h>
10 #include <linux/interrupt.h>
11 #include <linux/msi.h>
12 #include <linux/kthread.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/fsl/mc.h>
19 #include "dpaa2-eth.h"
21 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
22 * using trace events only need to #include <trace/events/sched.h>
24 #define CREATE_TRACE_POINTS
25 #include "dpaa2-eth-trace.h"
27 MODULE_LICENSE("Dual BSD/GPL");
28 MODULE_AUTHOR("Freescale Semiconductor, Inc");
29 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
31 static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
34 phys_addr_t phys_addr;
36 phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
38 return phys_to_virt(phys_addr);
41 static void validate_rx_csum(struct dpaa2_eth_priv *priv,
45 skb_checksum_none_assert(skb);
47 /* HW checksum validation is disabled, nothing to do here */
48 if (!(priv->net_dev->features & NETIF_F_RXCSUM))
51 /* Read checksum validation bits */
52 if (!((fd_status & DPAA2_FAS_L3CV) &&
53 (fd_status & DPAA2_FAS_L4CV)))
56 /* Inform the stack there's no need to compute L3/L4 csum anymore */
57 skb->ip_summed = CHECKSUM_UNNECESSARY;
60 /* Free a received FD.
61 * Not to be used for Tx conf FDs or on any other paths.
63 static void free_rx_fd(struct dpaa2_eth_priv *priv,
64 const struct dpaa2_fd *fd,
67 struct device *dev = priv->net_dev->dev.parent;
68 dma_addr_t addr = dpaa2_fd_get_addr(fd);
69 u8 fd_format = dpaa2_fd_get_format(fd);
70 struct dpaa2_sg_entry *sgt;
74 /* If single buffer frame, just free the data buffer */
75 if (fd_format == dpaa2_fd_single)
77 else if (fd_format != dpaa2_fd_sg)
78 /* We don't support any other format */
81 /* For S/G frames, we first need to free all SG entries
82 * except the first one, which was taken care of already
84 sgt = vaddr + dpaa2_fd_get_offset(fd);
85 for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
86 addr = dpaa2_sg_get_addr(&sgt[i]);
87 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
88 dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
91 skb_free_frag(sg_vaddr);
92 if (dpaa2_sg_is_final(&sgt[i]))
100 /* Build a linear skb based on a single-buffer frame descriptor */
101 static struct sk_buff *build_linear_skb(struct dpaa2_eth_priv *priv,
102 struct dpaa2_eth_channel *ch,
103 const struct dpaa2_fd *fd,
106 struct sk_buff *skb = NULL;
107 u16 fd_offset = dpaa2_fd_get_offset(fd);
108 u32 fd_length = dpaa2_fd_get_len(fd);
112 skb = build_skb(fd_vaddr, DPAA2_ETH_SKB_SIZE);
116 skb_reserve(skb, fd_offset);
117 skb_put(skb, fd_length);
122 /* Build a non linear (fragmented) skb based on a S/G table */
123 static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv,
124 struct dpaa2_eth_channel *ch,
125 struct dpaa2_sg_entry *sgt)
127 struct sk_buff *skb = NULL;
128 struct device *dev = priv->net_dev->dev.parent;
133 struct page *page, *head_page;
137 for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
138 struct dpaa2_sg_entry *sge = &sgt[i];
140 /* NOTE: We only support SG entries in dpaa2_sg_single format,
141 * but this is the only format we may receive from HW anyway
144 /* Get the address and length from the S/G entry */
145 sg_addr = dpaa2_sg_get_addr(sge);
146 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
147 dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUF_SIZE,
150 sg_length = dpaa2_sg_get_len(sge);
153 /* We build the skb around the first data buffer */
154 skb = build_skb(sg_vaddr, DPAA2_ETH_SKB_SIZE);
155 if (unlikely(!skb)) {
156 /* Free the first SG entry now, since we already
157 * unmapped it and obtained the virtual address
159 skb_free_frag(sg_vaddr);
161 /* We still need to subtract the buffers used
162 * by this FD from our software counter
164 while (!dpaa2_sg_is_final(&sgt[i]) &&
165 i < DPAA2_ETH_MAX_SG_ENTRIES)
170 sg_offset = dpaa2_sg_get_offset(sge);
171 skb_reserve(skb, sg_offset);
172 skb_put(skb, sg_length);
174 /* Rest of the data buffers are stored as skb frags */
175 page = virt_to_page(sg_vaddr);
176 head_page = virt_to_head_page(sg_vaddr);
178 /* Offset in page (which may be compound).
179 * Data in subsequent SG entries is stored from the
180 * beginning of the buffer, so we don't need to add the
183 page_offset = ((unsigned long)sg_vaddr &
185 (page_address(page) - page_address(head_page));
187 skb_add_rx_frag(skb, i - 1, head_page, page_offset,
188 sg_length, DPAA2_ETH_RX_BUF_SIZE);
191 if (dpaa2_sg_is_final(sge))
195 WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
197 /* Count all data buffers + SG table buffer */
198 ch->buf_count -= i + 2;
203 /* Main Rx frame processing routine */
204 static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
205 struct dpaa2_eth_channel *ch,
206 const struct dpaa2_fd *fd,
207 struct napi_struct *napi,
210 dma_addr_t addr = dpaa2_fd_get_addr(fd);
211 u8 fd_format = dpaa2_fd_get_format(fd);
214 struct rtnl_link_stats64 *percpu_stats;
215 struct dpaa2_eth_drv_stats *percpu_extras;
216 struct device *dev = priv->net_dev->dev.parent;
217 struct dpaa2_fas *fas;
222 trace_dpaa2_rx_fd(priv->net_dev, fd);
224 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
225 dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE);
227 fas = dpaa2_get_fas(vaddr, false);
229 buf_data = vaddr + dpaa2_fd_get_offset(fd);
232 percpu_stats = this_cpu_ptr(priv->percpu_stats);
233 percpu_extras = this_cpu_ptr(priv->percpu_extras);
235 if (fd_format == dpaa2_fd_single) {
236 skb = build_linear_skb(priv, ch, fd, vaddr);
237 } else if (fd_format == dpaa2_fd_sg) {
238 skb = build_frag_skb(priv, ch, buf_data);
239 skb_free_frag(vaddr);
240 percpu_extras->rx_sg_frames++;
241 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
243 /* We don't support any other format */
244 goto err_frame_format;
252 /* Get the timestamp value */
253 if (priv->rx_tstamp) {
254 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
255 __le64 *ts = dpaa2_get_ts(vaddr, false);
258 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
260 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
261 shhwtstamps->hwtstamp = ns_to_ktime(ns);
264 /* Check if we need to validate the L4 csum */
265 if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
266 status = le32_to_cpu(fas->status);
267 validate_rx_csum(priv, status, skb);
270 skb->protocol = eth_type_trans(skb, priv->net_dev);
271 skb_record_rx_queue(skb, queue_id);
273 percpu_stats->rx_packets++;
274 percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
276 napi_gro_receive(napi, skb);
281 free_rx_fd(priv, fd, vaddr);
283 percpu_stats->rx_dropped++;
286 /* Consume all frames pull-dequeued into the store. This is the simplest way to
287 * make sure we don't accidentally issue another volatile dequeue which would
288 * overwrite (leak) frames already in the store.
290 * Observance of NAPI budget is not our concern, leaving that to the caller.
292 static int consume_frames(struct dpaa2_eth_channel *ch)
294 struct dpaa2_eth_priv *priv = ch->priv;
295 struct dpaa2_eth_fq *fq;
297 const struct dpaa2_fd *fd;
302 dq = dpaa2_io_store_next(ch->store, &is_last);
304 /* If we're here, we *must* have placed a
305 * volatile dequeue comnmand, so keep reading through
306 * the store until we get some sort of valid response
307 * token (either a valid frame or an "empty dequeue")
312 fd = dpaa2_dq_fd(dq);
313 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
316 fq->consume(priv, ch, fd, &ch->napi, fq->flowid);
323 /* Configure the egress frame annotation for timestamp update */
324 static void enable_tx_tstamp(struct dpaa2_fd *fd, void *buf_start)
326 struct dpaa2_faead *faead;
329 /* Mark the egress frame annotation area as valid */
330 frc = dpaa2_fd_get_frc(fd);
331 dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
333 /* Set hardware annotation size */
334 ctrl = dpaa2_fd_get_ctrl(fd);
335 dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
337 /* enable UPD (update prepanded data) bit in FAEAD field of
338 * hardware frame annotation area
340 ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
341 faead = dpaa2_get_faead(buf_start, true);
342 faead->ctrl = cpu_to_le32(ctrl);
345 /* Create a frame descriptor based on a fragmented skb */
346 static int build_sg_fd(struct dpaa2_eth_priv *priv,
350 struct device *dev = priv->net_dev->dev.parent;
351 void *sgt_buf = NULL;
353 int nr_frags = skb_shinfo(skb)->nr_frags;
354 struct dpaa2_sg_entry *sgt;
357 struct scatterlist *scl, *crt_scl;
360 struct dpaa2_eth_swa *swa;
362 /* Create and map scatterlist.
363 * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
364 * to go beyond nr_frags+1.
365 * Note: We don't support chained scatterlists
367 if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
370 scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
374 sg_init_table(scl, nr_frags + 1);
375 num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
376 num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
377 if (unlikely(!num_dma_bufs)) {
379 goto dma_map_sg_failed;
382 /* Prepare the HW SGT structure */
383 sgt_buf_size = priv->tx_data_offset +
384 sizeof(struct dpaa2_sg_entry) * num_dma_bufs;
385 sgt_buf = netdev_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
386 if (unlikely(!sgt_buf)) {
388 goto sgt_buf_alloc_failed;
390 sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
391 memset(sgt_buf, 0, sgt_buf_size);
393 sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
395 /* Fill in the HW SGT structure.
397 * sgt_buf is zeroed out, so the following fields are implicit
398 * in all sgt entries:
400 * - format is 'dpaa2_sg_single'
402 for_each_sg(scl, crt_scl, num_dma_bufs, i) {
403 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
404 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
406 dpaa2_sg_set_final(&sgt[i - 1], true);
408 /* Store the skb backpointer in the SGT buffer.
409 * Fit the scatterlist and the number of buffers alongside the
410 * skb backpointer in the software annotation area. We'll need
411 * all of them on Tx Conf.
413 swa = (struct dpaa2_eth_swa *)sgt_buf;
416 swa->num_sg = num_sg;
417 swa->sgt_size = sgt_buf_size;
419 /* Separately map the SGT buffer */
420 addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
421 if (unlikely(dma_mapping_error(dev, addr))) {
423 goto dma_map_single_failed;
425 dpaa2_fd_set_offset(fd, priv->tx_data_offset);
426 dpaa2_fd_set_format(fd, dpaa2_fd_sg);
427 dpaa2_fd_set_addr(fd, addr);
428 dpaa2_fd_set_len(fd, skb->len);
429 dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA | FD_CTRL_PTV1);
431 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
432 enable_tx_tstamp(fd, sgt_buf);
436 dma_map_single_failed:
437 skb_free_frag(sgt_buf);
438 sgt_buf_alloc_failed:
439 dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
445 /* Create a frame descriptor based on a linear skb */
446 static int build_single_fd(struct dpaa2_eth_priv *priv,
450 struct device *dev = priv->net_dev->dev.parent;
451 u8 *buffer_start, *aligned_start;
452 struct sk_buff **skbh;
455 buffer_start = skb->data - dpaa2_eth_needed_headroom(priv, skb);
457 /* If there's enough room to align the FD address, do it.
458 * It will help hardware optimize accesses.
460 aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
461 DPAA2_ETH_TX_BUF_ALIGN);
462 if (aligned_start >= skb->head)
463 buffer_start = aligned_start;
465 /* Store a backpointer to the skb at the beginning of the buffer
466 * (in the private data area) such that we can release it
469 skbh = (struct sk_buff **)buffer_start;
472 addr = dma_map_single(dev, buffer_start,
473 skb_tail_pointer(skb) - buffer_start,
475 if (unlikely(dma_mapping_error(dev, addr)))
478 dpaa2_fd_set_addr(fd, addr);
479 dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
480 dpaa2_fd_set_len(fd, skb->len);
481 dpaa2_fd_set_format(fd, dpaa2_fd_single);
482 dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA | FD_CTRL_PTV1);
484 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
485 enable_tx_tstamp(fd, buffer_start);
490 /* FD freeing routine on the Tx path
492 * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
493 * back-pointed to is also freed.
494 * This can be called either from dpaa2_eth_tx_conf() or on the error path of
497 static void free_tx_fd(const struct dpaa2_eth_priv *priv,
498 const struct dpaa2_fd *fd)
500 struct device *dev = priv->net_dev->dev.parent;
502 struct sk_buff **skbh, *skb;
503 unsigned char *buffer_start;
504 struct dpaa2_eth_swa *swa;
505 u8 fd_format = dpaa2_fd_get_format(fd);
507 fd_addr = dpaa2_fd_get_addr(fd);
508 skbh = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
510 if (fd_format == dpaa2_fd_single) {
512 buffer_start = (unsigned char *)skbh;
513 /* Accessing the skb buffer is safe before dma unmap, because
514 * we didn't map the actual skb shell.
516 dma_unmap_single(dev, fd_addr,
517 skb_tail_pointer(skb) - buffer_start,
519 } else if (fd_format == dpaa2_fd_sg) {
520 swa = (struct dpaa2_eth_swa *)skbh;
523 /* Unmap the scatterlist */
524 dma_unmap_sg(dev, swa->scl, swa->num_sg, DMA_BIDIRECTIONAL);
527 /* Unmap the SGT buffer */
528 dma_unmap_single(dev, fd_addr, swa->sgt_size,
531 netdev_dbg(priv->net_dev, "Invalid FD format\n");
535 /* Get the timestamp value */
536 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
537 struct skb_shared_hwtstamps shhwtstamps;
538 __le64 *ts = dpaa2_get_ts(skbh, true);
541 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
543 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
544 shhwtstamps.hwtstamp = ns_to_ktime(ns);
545 skb_tstamp_tx(skb, &shhwtstamps);
548 /* Free SGT buffer allocated on tx */
549 if (fd_format != dpaa2_fd_single)
552 /* Move on with skb release */
556 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
558 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
560 struct rtnl_link_stats64 *percpu_stats;
561 struct dpaa2_eth_drv_stats *percpu_extras;
562 struct dpaa2_eth_fq *fq;
564 unsigned int needed_headroom;
567 percpu_stats = this_cpu_ptr(priv->percpu_stats);
568 percpu_extras = this_cpu_ptr(priv->percpu_extras);
570 needed_headroom = dpaa2_eth_needed_headroom(priv, skb);
571 if (skb_headroom(skb) < needed_headroom) {
574 ns = skb_realloc_headroom(skb, needed_headroom);
576 percpu_stats->tx_dropped++;
577 goto err_alloc_headroom;
579 percpu_extras->tx_reallocs++;
582 skb_set_owner_w(ns, skb->sk);
588 /* We'll be holding a back-reference to the skb until Tx Confirmation;
589 * we don't want that overwritten by a concurrent Tx with a cloned skb.
591 skb = skb_unshare(skb, GFP_ATOMIC);
592 if (unlikely(!skb)) {
593 /* skb_unshare() has already freed the skb */
594 percpu_stats->tx_dropped++;
598 /* Setup the FD fields */
599 memset(&fd, 0, sizeof(fd));
601 if (skb_is_nonlinear(skb)) {
602 err = build_sg_fd(priv, skb, &fd);
603 percpu_extras->tx_sg_frames++;
604 percpu_extras->tx_sg_bytes += skb->len;
606 err = build_single_fd(priv, skb, &fd);
610 percpu_stats->tx_dropped++;
615 trace_dpaa2_tx_fd(net_dev, &fd);
617 /* TxConf FQ selection relies on queue id from the stack.
618 * In case of a forwarded frame from another DPNI interface, we choose
619 * a queue affined to the same core that processed the Rx frame
621 queue_mapping = skb_get_queue_mapping(skb);
622 fq = &priv->fq[queue_mapping];
623 for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
624 err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
630 percpu_extras->tx_portal_busy += i;
631 if (unlikely(err < 0)) {
632 percpu_stats->tx_errors++;
633 /* Clean up everything, including freeing the skb */
634 free_tx_fd(priv, &fd);
636 percpu_stats->tx_packets++;
637 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fd);
649 /* Tx confirmation frame processing routine */
650 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
651 struct dpaa2_eth_channel *ch,
652 const struct dpaa2_fd *fd,
653 struct napi_struct *napi __always_unused,
654 u16 queue_id __always_unused)
656 struct rtnl_link_stats64 *percpu_stats;
657 struct dpaa2_eth_drv_stats *percpu_extras;
661 trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
663 percpu_extras = this_cpu_ptr(priv->percpu_extras);
664 percpu_extras->tx_conf_frames++;
665 percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd);
667 /* Check frame errors in the FD field */
668 fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
669 free_tx_fd(priv, fd);
671 if (likely(!fd_errors))
675 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
678 percpu_stats = this_cpu_ptr(priv->percpu_stats);
679 /* Tx-conf logically pertains to the egress path. */
680 percpu_stats->tx_errors++;
683 static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
687 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
688 DPNI_OFF_RX_L3_CSUM, enable);
690 netdev_err(priv->net_dev,
691 "dpni_set_offload(RX_L3_CSUM) failed\n");
695 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
696 DPNI_OFF_RX_L4_CSUM, enable);
698 netdev_err(priv->net_dev,
699 "dpni_set_offload(RX_L4_CSUM) failed\n");
706 static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
710 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
711 DPNI_OFF_TX_L3_CSUM, enable);
713 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
717 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
718 DPNI_OFF_TX_L4_CSUM, enable);
720 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
727 /* Free buffers acquired from the buffer pool or which were meant to
728 * be released in the pool
730 static void free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, int count)
732 struct device *dev = priv->net_dev->dev.parent;
736 for (i = 0; i < count; i++) {
737 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
738 dma_unmap_single(dev, buf_array[i], DPAA2_ETH_RX_BUF_SIZE,
740 skb_free_frag(vaddr);
744 /* Perform a single release command to add buffers
745 * to the specified buffer pool
747 static int add_bufs(struct dpaa2_eth_priv *priv,
748 struct dpaa2_eth_channel *ch, u16 bpid)
750 struct device *dev = priv->net_dev->dev.parent;
751 u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
756 for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
757 /* Allocate buffer visible to WRIOP + skb shared info +
760 buf = napi_alloc_frag(dpaa2_eth_buf_raw_size(priv));
764 buf = PTR_ALIGN(buf, priv->rx_buf_align);
766 addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE,
768 if (unlikely(dma_mapping_error(dev, addr)))
774 trace_dpaa2_eth_buf_seed(priv->net_dev,
775 buf, dpaa2_eth_buf_raw_size(priv),
776 addr, DPAA2_ETH_RX_BUF_SIZE,
781 /* In case the portal is busy, retry until successful */
782 while ((err = dpaa2_io_service_release(ch->dpio, bpid,
783 buf_array, i)) == -EBUSY)
786 /* If release command failed, clean up and bail out;
787 * not much else we can do about it
790 free_bufs(priv, buf_array, i);
799 /* If we managed to allocate at least some buffers,
800 * release them to hardware
808 static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
813 /* This is the lazy seeding of Rx buffer pools.
814 * dpaa2_add_bufs() is also used on the Rx hotpath and calls
815 * napi_alloc_frag(). The trouble with that is that it in turn ends up
816 * calling this_cpu_ptr(), which mandates execution in atomic context.
817 * Rather than splitting up the code, do a one-off preempt disable.
820 for (j = 0; j < priv->num_channels; j++) {
821 for (i = 0; i < DPAA2_ETH_NUM_BUFS;
822 i += DPAA2_ETH_BUFS_PER_CMD) {
823 new_count = add_bufs(priv, priv->channel[j], bpid);
824 priv->channel[j]->buf_count += new_count;
826 if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
838 * Drain the specified number of buffers from the DPNI's private buffer pool.
839 * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
841 static void drain_bufs(struct dpaa2_eth_priv *priv, int count)
843 u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
847 ret = dpaa2_io_service_acquire(NULL, priv->bpid,
850 netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
853 free_bufs(priv, buf_array, ret);
857 static void drain_pool(struct dpaa2_eth_priv *priv)
861 drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
864 for (i = 0; i < priv->num_channels; i++)
865 priv->channel[i]->buf_count = 0;
868 /* Function is called from softirq context only, so we don't need to guard
869 * the access to percpu count
871 static int refill_pool(struct dpaa2_eth_priv *priv,
872 struct dpaa2_eth_channel *ch,
877 if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
881 new_count = add_bufs(priv, ch, bpid);
882 if (unlikely(!new_count)) {
883 /* Out of memory; abort for now, we'll try later on */
886 ch->buf_count += new_count;
887 } while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
889 if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
895 static int pull_channel(struct dpaa2_eth_channel *ch)
900 /* Retry while portal is busy */
902 err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
906 } while (err == -EBUSY);
908 ch->stats.dequeue_portal_busy += dequeues;
910 ch->stats.pull_err++;
917 * Frames are dequeued from the QMan channel associated with this NAPI context.
918 * Rx, Tx confirmation and (if configured) Rx error frames all count
919 * towards the NAPI budget.
921 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
923 struct dpaa2_eth_channel *ch;
924 int cleaned = 0, store_cleaned;
925 struct dpaa2_eth_priv *priv;
928 ch = container_of(napi, struct dpaa2_eth_channel, napi);
931 while (cleaned < budget) {
932 err = pull_channel(ch);
936 /* Refill pool if appropriate */
937 refill_pool(priv, ch, priv->bpid);
939 store_cleaned = consume_frames(ch);
940 cleaned += store_cleaned;
942 /* If we have enough budget left for a full store,
943 * try a new pull dequeue, otherwise we're done here
945 if (store_cleaned == 0 ||
946 cleaned > budget - DPAA2_ETH_STORE_SIZE)
950 if (cleaned < budget && napi_complete_done(napi, cleaned)) {
951 /* Re-enable data available notifications */
953 err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
955 } while (err == -EBUSY);
956 WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
957 ch->nctx.desired_cpu);
960 ch->stats.frames += cleaned;
965 static void enable_ch_napi(struct dpaa2_eth_priv *priv)
967 struct dpaa2_eth_channel *ch;
970 for (i = 0; i < priv->num_channels; i++) {
971 ch = priv->channel[i];
972 napi_enable(&ch->napi);
976 static void disable_ch_napi(struct dpaa2_eth_priv *priv)
978 struct dpaa2_eth_channel *ch;
981 for (i = 0; i < priv->num_channels; i++) {
982 ch = priv->channel[i];
983 napi_disable(&ch->napi);
987 static int link_state_update(struct dpaa2_eth_priv *priv)
989 struct dpni_link_state state;
992 err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
994 netdev_err(priv->net_dev,
995 "dpni_get_link_state() failed\n");
999 /* Chech link state; speed / duplex changes are not treated yet */
1000 if (priv->link_state.up == state.up)
1003 priv->link_state = state;
1005 netif_carrier_on(priv->net_dev);
1006 netif_tx_start_all_queues(priv->net_dev);
1008 netif_tx_stop_all_queues(priv->net_dev);
1009 netif_carrier_off(priv->net_dev);
1012 netdev_info(priv->net_dev, "Link Event: state %s\n",
1013 state.up ? "up" : "down");
1018 static int dpaa2_eth_open(struct net_device *net_dev)
1020 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1023 err = seed_pool(priv, priv->bpid);
1025 /* Not much to do; the buffer pool, though not filled up,
1026 * may still contain some buffers which would enable us
1029 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1030 priv->dpbp_dev->obj_desc.id, priv->bpid);
1033 /* We'll only start the txqs when the link is actually ready; make sure
1034 * we don't race against the link up notification, which may come
1035 * immediately after dpni_enable();
1037 netif_tx_stop_all_queues(net_dev);
1038 enable_ch_napi(priv);
1039 /* Also, explicitly set carrier off, otherwise netif_carrier_ok() will
1040 * return true and cause 'ip link show' to report the LOWER_UP flag,
1041 * even though the link notification wasn't even received.
1043 netif_carrier_off(net_dev);
1045 err = dpni_enable(priv->mc_io, 0, priv->mc_token);
1047 netdev_err(net_dev, "dpni_enable() failed\n");
1051 /* If the DPMAC object has already processed the link up interrupt,
1052 * we have to learn the link state ourselves.
1054 err = link_state_update(priv);
1056 netdev_err(net_dev, "Can't update link state\n");
1057 goto link_state_err;
1064 disable_ch_napi(priv);
1069 /* The DPIO store must be empty when we call this,
1070 * at the end of every NAPI cycle.
1072 static u32 drain_channel(struct dpaa2_eth_priv *priv,
1073 struct dpaa2_eth_channel *ch)
1075 u32 drained = 0, total = 0;
1079 drained = consume_frames(ch);
1086 static u32 drain_ingress_frames(struct dpaa2_eth_priv *priv)
1088 struct dpaa2_eth_channel *ch;
1092 for (i = 0; i < priv->num_channels; i++) {
1093 ch = priv->channel[i];
1094 drained += drain_channel(priv, ch);
1100 static int dpaa2_eth_stop(struct net_device *net_dev)
1102 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1107 netif_tx_stop_all_queues(net_dev);
1108 netif_carrier_off(net_dev);
1110 /* Loop while dpni_disable() attempts to drain the egress FQs
1111 * and confirm them back to us.
1114 dpni_disable(priv->mc_io, 0, priv->mc_token);
1115 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
1117 /* Allow the hardware some slack */
1119 } while (dpni_enabled && --retries);
1121 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
1122 /* Must go on and disable NAPI nonetheless, so we don't crash at
1123 * the next "ifconfig up"
1127 /* Wait for NAPI to complete on every core and disable it.
1128 * In particular, this will also prevent NAPI from being rescheduled if
1129 * a new CDAN is serviced, effectively discarding the CDAN. We therefore
1130 * don't even need to disarm the channels, except perhaps for the case
1131 * of a huge coalescing value.
1133 disable_ch_napi(priv);
1135 /* Manually drain the Rx and TxConf queues */
1136 drained = drain_ingress_frames(priv);
1138 netdev_dbg(net_dev, "Drained %d frames.\n", drained);
1140 /* Empty the buffer pool */
1146 static int dpaa2_eth_init(struct net_device *net_dev)
1149 u64 not_supported = 0;
1150 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1151 u32 options = priv->dpni_attrs.options;
1153 /* Capabilities listing */
1154 supported |= IFF_LIVE_ADDR_CHANGE;
1156 if (options & DPNI_OPT_NO_MAC_FILTER)
1157 not_supported |= IFF_UNICAST_FLT;
1159 supported |= IFF_UNICAST_FLT;
1161 net_dev->priv_flags |= supported;
1162 net_dev->priv_flags &= ~not_supported;
1165 net_dev->features = NETIF_F_RXCSUM |
1166 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1167 NETIF_F_SG | NETIF_F_HIGHDMA |
1169 net_dev->hw_features = net_dev->features;
1174 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
1176 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1177 struct device *dev = net_dev->dev.parent;
1180 err = eth_mac_addr(net_dev, addr);
1182 dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
1186 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
1189 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
1196 /** Fill in counters maintained by the GPP driver. These may be different from
1197 * the hardware counters obtained by ethtool.
1199 static void dpaa2_eth_get_stats(struct net_device *net_dev,
1200 struct rtnl_link_stats64 *stats)
1202 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1203 struct rtnl_link_stats64 *percpu_stats;
1205 u64 *netstats = (u64 *)stats;
1207 int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
1209 for_each_possible_cpu(i) {
1210 percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
1211 cpustats = (u64 *)percpu_stats;
1212 for (j = 0; j < num; j++)
1213 netstats[j] += cpustats[j];
1217 /* Copy mac unicast addresses from @net_dev to @priv.
1218 * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1220 static void add_uc_hw_addr(const struct net_device *net_dev,
1221 struct dpaa2_eth_priv *priv)
1223 struct netdev_hw_addr *ha;
1226 netdev_for_each_uc_addr(ha, net_dev) {
1227 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1230 netdev_warn(priv->net_dev,
1231 "Could not add ucast MAC %pM to the filtering table (err %d)\n",
1236 /* Copy mac multicast addresses from @net_dev to @priv
1237 * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1239 static void add_mc_hw_addr(const struct net_device *net_dev,
1240 struct dpaa2_eth_priv *priv)
1242 struct netdev_hw_addr *ha;
1245 netdev_for_each_mc_addr(ha, net_dev) {
1246 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1249 netdev_warn(priv->net_dev,
1250 "Could not add mcast MAC %pM to the filtering table (err %d)\n",
1255 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
1257 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1258 int uc_count = netdev_uc_count(net_dev);
1259 int mc_count = netdev_mc_count(net_dev);
1260 u8 max_mac = priv->dpni_attrs.mac_filter_entries;
1261 u32 options = priv->dpni_attrs.options;
1262 u16 mc_token = priv->mc_token;
1263 struct fsl_mc_io *mc_io = priv->mc_io;
1266 /* Basic sanity checks; these probably indicate a misconfiguration */
1267 if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
1268 netdev_info(net_dev,
1269 "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
1272 /* Force promiscuous if the uc or mc counts exceed our capabilities. */
1273 if (uc_count > max_mac) {
1274 netdev_info(net_dev,
1275 "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
1279 if (mc_count + uc_count > max_mac) {
1280 netdev_info(net_dev,
1281 "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
1282 uc_count + mc_count, max_mac);
1283 goto force_mc_promisc;
1286 /* Adjust promisc settings due to flag combinations */
1287 if (net_dev->flags & IFF_PROMISC)
1289 if (net_dev->flags & IFF_ALLMULTI) {
1290 /* First, rebuild unicast filtering table. This should be done
1291 * in promisc mode, in order to avoid frame loss while we
1292 * progressively add entries to the table.
1293 * We don't know whether we had been in promisc already, and
1294 * making an MC call to find out is expensive; so set uc promisc
1297 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1299 netdev_warn(net_dev, "Can't set uc promisc\n");
1301 /* Actual uc table reconstruction. */
1302 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
1304 netdev_warn(net_dev, "Can't clear uc filters\n");
1305 add_uc_hw_addr(net_dev, priv);
1307 /* Finally, clear uc promisc and set mc promisc as requested. */
1308 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1310 netdev_warn(net_dev, "Can't clear uc promisc\n");
1311 goto force_mc_promisc;
1314 /* Neither unicast, nor multicast promisc will be on... eventually.
1315 * For now, rebuild mac filtering tables while forcing both of them on.
1317 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1319 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
1320 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1322 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
1324 /* Actual mac filtering tables reconstruction */
1325 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
1327 netdev_warn(net_dev, "Can't clear mac filters\n");
1328 add_mc_hw_addr(net_dev, priv);
1329 add_uc_hw_addr(net_dev, priv);
1331 /* Now we can clear both ucast and mcast promisc, without risking
1332 * to drop legitimate frames anymore.
1334 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1336 netdev_warn(net_dev, "Can't clear ucast promisc\n");
1337 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
1339 netdev_warn(net_dev, "Can't clear mcast promisc\n");
1344 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1346 netdev_warn(net_dev, "Can't set ucast promisc\n");
1348 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1350 netdev_warn(net_dev, "Can't set mcast promisc\n");
1353 static int dpaa2_eth_set_features(struct net_device *net_dev,
1354 netdev_features_t features)
1356 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1357 netdev_features_t changed = features ^ net_dev->features;
1361 if (changed & NETIF_F_RXCSUM) {
1362 enable = !!(features & NETIF_F_RXCSUM);
1363 err = set_rx_csum(priv, enable);
1368 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
1369 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
1370 err = set_tx_csum(priv, enable);
1378 static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1380 struct dpaa2_eth_priv *priv = netdev_priv(dev);
1381 struct hwtstamp_config config;
1383 if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
1386 switch (config.tx_type) {
1387 case HWTSTAMP_TX_OFF:
1388 priv->tx_tstamp = false;
1390 case HWTSTAMP_TX_ON:
1391 priv->tx_tstamp = true;
1397 if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
1398 priv->rx_tstamp = false;
1400 priv->rx_tstamp = true;
1401 /* TS is set for all frame types, not only those requested */
1402 config.rx_filter = HWTSTAMP_FILTER_ALL;
1405 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
1409 static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1411 if (cmd == SIOCSHWTSTAMP)
1412 return dpaa2_eth_ts_ioctl(dev, rq, cmd);
1417 static const struct net_device_ops dpaa2_eth_ops = {
1418 .ndo_open = dpaa2_eth_open,
1419 .ndo_start_xmit = dpaa2_eth_tx,
1420 .ndo_stop = dpaa2_eth_stop,
1421 .ndo_init = dpaa2_eth_init,
1422 .ndo_set_mac_address = dpaa2_eth_set_addr,
1423 .ndo_get_stats64 = dpaa2_eth_get_stats,
1424 .ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
1425 .ndo_set_features = dpaa2_eth_set_features,
1426 .ndo_do_ioctl = dpaa2_eth_ioctl,
1429 static void cdan_cb(struct dpaa2_io_notification_ctx *ctx)
1431 struct dpaa2_eth_channel *ch;
1433 ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
1435 /* Update NAPI statistics */
1438 napi_schedule_irqoff(&ch->napi);
1441 /* Allocate and configure a DPCON object */
1442 static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv)
1444 struct fsl_mc_device *dpcon;
1445 struct device *dev = priv->net_dev->dev.parent;
1446 struct dpcon_attr attrs;
1449 err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
1450 FSL_MC_POOL_DPCON, &dpcon);
1452 dev_info(dev, "Not enough DPCONs, will go on as-is\n");
1456 err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
1458 dev_err(dev, "dpcon_open() failed\n");
1462 err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
1464 dev_err(dev, "dpcon_reset() failed\n");
1468 err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs);
1470 dev_err(dev, "dpcon_get_attributes() failed\n");
1474 err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
1476 dev_err(dev, "dpcon_enable() failed\n");
1483 dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
1485 fsl_mc_object_free(dpcon);
1490 static void free_dpcon(struct dpaa2_eth_priv *priv,
1491 struct fsl_mc_device *dpcon)
1493 dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
1494 dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
1495 fsl_mc_object_free(dpcon);
1498 static struct dpaa2_eth_channel *
1499 alloc_channel(struct dpaa2_eth_priv *priv)
1501 struct dpaa2_eth_channel *channel;
1502 struct dpcon_attr attr;
1503 struct device *dev = priv->net_dev->dev.parent;
1506 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
1510 channel->dpcon = setup_dpcon(priv);
1511 if (!channel->dpcon)
1514 err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
1517 dev_err(dev, "dpcon_get_attributes() failed\n");
1521 channel->dpcon_id = attr.id;
1522 channel->ch_id = attr.qbman_ch_id;
1523 channel->priv = priv;
1528 free_dpcon(priv, channel->dpcon);
1534 static void free_channel(struct dpaa2_eth_priv *priv,
1535 struct dpaa2_eth_channel *channel)
1537 free_dpcon(priv, channel->dpcon);
1541 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
1542 * and register data availability notifications
1544 static int setup_dpio(struct dpaa2_eth_priv *priv)
1546 struct dpaa2_io_notification_ctx *nctx;
1547 struct dpaa2_eth_channel *channel;
1548 struct dpcon_notification_cfg dpcon_notif_cfg;
1549 struct device *dev = priv->net_dev->dev.parent;
1552 /* We want the ability to spread ingress traffic (RX, TX conf) to as
1553 * many cores as possible, so we need one channel for each core
1554 * (unless there's fewer queues than cores, in which case the extra
1555 * channels would be wasted).
1556 * Allocate one channel per core and register it to the core's
1557 * affine DPIO. If not enough channels are available for all cores
1558 * or if some cores don't have an affine DPIO, there will be no
1559 * ingress frame processing on those cores.
1561 cpumask_clear(&priv->dpio_cpumask);
1562 for_each_online_cpu(i) {
1563 /* Try to allocate a channel */
1564 channel = alloc_channel(priv);
1567 "No affine channel for cpu %d and above\n", i);
1572 priv->channel[priv->num_channels] = channel;
1574 nctx = &channel->nctx;
1577 nctx->id = channel->ch_id;
1578 nctx->desired_cpu = i;
1580 /* Register the new context */
1581 channel->dpio = dpaa2_io_service_select(i);
1582 err = dpaa2_io_service_register(channel->dpio, nctx);
1584 dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
1585 /* If no affine DPIO for this core, there's probably
1586 * none available for next cores either. Signal we want
1587 * to retry later, in case the DPIO devices weren't
1590 err = -EPROBE_DEFER;
1591 goto err_service_reg;
1594 /* Register DPCON notification with MC */
1595 dpcon_notif_cfg.dpio_id = nctx->dpio_id;
1596 dpcon_notif_cfg.priority = 0;
1597 dpcon_notif_cfg.user_ctx = nctx->qman64;
1598 err = dpcon_set_notification(priv->mc_io, 0,
1599 channel->dpcon->mc_handle,
1602 dev_err(dev, "dpcon_set_notification failed()\n");
1606 /* If we managed to allocate a channel and also found an affine
1607 * DPIO for this core, add it to the final mask
1609 cpumask_set_cpu(i, &priv->dpio_cpumask);
1610 priv->num_channels++;
1612 /* Stop if we already have enough channels to accommodate all
1613 * RX and TX conf queues
1615 if (priv->num_channels == dpaa2_eth_queue_count(priv))
1622 dpaa2_io_service_deregister(channel->dpio, nctx);
1624 free_channel(priv, channel);
1626 if (cpumask_empty(&priv->dpio_cpumask)) {
1627 dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
1631 dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
1632 cpumask_pr_args(&priv->dpio_cpumask));
1637 static void free_dpio(struct dpaa2_eth_priv *priv)
1640 struct dpaa2_eth_channel *ch;
1642 /* deregister CDAN notifications and free channels */
1643 for (i = 0; i < priv->num_channels; i++) {
1644 ch = priv->channel[i];
1645 dpaa2_io_service_deregister(ch->dpio, &ch->nctx);
1646 free_channel(priv, ch);
1650 static struct dpaa2_eth_channel *get_affine_channel(struct dpaa2_eth_priv *priv,
1653 struct device *dev = priv->net_dev->dev.parent;
1656 for (i = 0; i < priv->num_channels; i++)
1657 if (priv->channel[i]->nctx.desired_cpu == cpu)
1658 return priv->channel[i];
1660 /* We should never get here. Issue a warning and return
1661 * the first channel, because it's still better than nothing
1663 dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
1665 return priv->channel[0];
1668 static void set_fq_affinity(struct dpaa2_eth_priv *priv)
1670 struct device *dev = priv->net_dev->dev.parent;
1671 struct cpumask xps_mask;
1672 struct dpaa2_eth_fq *fq;
1673 int rx_cpu, txc_cpu;
1676 /* For each FQ, pick one channel/CPU to deliver frames to.
1677 * This may well change at runtime, either through irqbalance or
1678 * through direct user intervention.
1680 rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
1682 for (i = 0; i < priv->num_fqs; i++) {
1686 fq->target_cpu = rx_cpu;
1687 rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
1688 if (rx_cpu >= nr_cpu_ids)
1689 rx_cpu = cpumask_first(&priv->dpio_cpumask);
1691 case DPAA2_TX_CONF_FQ:
1692 fq->target_cpu = txc_cpu;
1694 /* Tell the stack to affine to txc_cpu the Tx queue
1695 * associated with the confirmation one
1697 cpumask_clear(&xps_mask);
1698 cpumask_set_cpu(txc_cpu, &xps_mask);
1699 err = netif_set_xps_queue(priv->net_dev, &xps_mask,
1702 dev_err(dev, "Error setting XPS queue\n");
1704 txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
1705 if (txc_cpu >= nr_cpu_ids)
1706 txc_cpu = cpumask_first(&priv->dpio_cpumask);
1709 dev_err(dev, "Unknown FQ type: %d\n", fq->type);
1711 fq->channel = get_affine_channel(priv, fq->target_cpu);
1715 static void setup_fqs(struct dpaa2_eth_priv *priv)
1719 /* We have one TxConf FQ per Tx flow.
1720 * The number of Tx and Rx queues is the same.
1721 * Tx queues come first in the fq array.
1723 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
1724 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
1725 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
1726 priv->fq[priv->num_fqs++].flowid = (u16)i;
1729 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
1730 priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
1731 priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
1732 priv->fq[priv->num_fqs++].flowid = (u16)i;
1735 /* For each FQ, decide on which core to process incoming frames */
1736 set_fq_affinity(priv);
1739 /* Allocate and configure one buffer pool for each interface */
1740 static int setup_dpbp(struct dpaa2_eth_priv *priv)
1743 struct fsl_mc_device *dpbp_dev;
1744 struct device *dev = priv->net_dev->dev.parent;
1745 struct dpbp_attr dpbp_attrs;
1747 err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
1750 dev_err(dev, "DPBP device allocation failed\n");
1754 priv->dpbp_dev = dpbp_dev;
1756 err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
1757 &dpbp_dev->mc_handle);
1759 dev_err(dev, "dpbp_open() failed\n");
1763 err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
1765 dev_err(dev, "dpbp_reset() failed\n");
1769 err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
1771 dev_err(dev, "dpbp_enable() failed\n");
1775 err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
1778 dev_err(dev, "dpbp_get_attributes() failed\n");
1781 priv->bpid = dpbp_attrs.bpid;
1786 dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
1789 dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
1791 fsl_mc_object_free(dpbp_dev);
1796 static void free_dpbp(struct dpaa2_eth_priv *priv)
1799 dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
1800 dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
1801 fsl_mc_object_free(priv->dpbp_dev);
1804 static int set_buffer_layout(struct dpaa2_eth_priv *priv)
1806 struct device *dev = priv->net_dev->dev.parent;
1807 struct dpni_buffer_layout buf_layout = {0};
1810 /* We need to check for WRIOP version 1.0.0, but depending on the MC
1811 * version, this number is not always provided correctly on rev1.
1812 * We need to check for both alternatives in this situation.
1814 if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
1815 priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
1816 priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
1818 priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
1821 buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
1822 buf_layout.pass_timestamp = true;
1823 buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
1824 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
1825 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1826 DPNI_QUEUE_TX, &buf_layout);
1828 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
1832 /* tx-confirm buffer */
1833 buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
1834 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1835 DPNI_QUEUE_TX_CONFIRM, &buf_layout);
1837 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
1841 /* Now that we've set our tx buffer layout, retrieve the minimum
1842 * required tx data offset.
1844 err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
1845 &priv->tx_data_offset);
1847 dev_err(dev, "dpni_get_tx_data_offset() failed\n");
1851 if ((priv->tx_data_offset % 64) != 0)
1852 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
1853 priv->tx_data_offset);
1856 buf_layout.pass_frame_status = true;
1857 buf_layout.pass_parser_result = true;
1858 buf_layout.data_align = priv->rx_buf_align;
1859 buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv);
1860 buf_layout.private_data_size = 0;
1861 buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
1862 DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
1863 DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
1864 DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
1865 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
1866 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1867 DPNI_QUEUE_RX, &buf_layout);
1869 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
1876 /* Configure the DPNI object this interface is associated with */
1877 static int setup_dpni(struct fsl_mc_device *ls_dev)
1879 struct device *dev = &ls_dev->dev;
1880 struct dpaa2_eth_priv *priv;
1881 struct net_device *net_dev;
1884 net_dev = dev_get_drvdata(dev);
1885 priv = netdev_priv(net_dev);
1887 /* get a handle for the DPNI object */
1888 err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
1890 dev_err(dev, "dpni_open() failed\n");
1894 /* Check if we can work with this DPNI object */
1895 err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
1896 &priv->dpni_ver_minor);
1898 dev_err(dev, "dpni_get_api_version() failed\n");
1901 if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
1902 dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
1903 priv->dpni_ver_major, priv->dpni_ver_minor,
1904 DPNI_VER_MAJOR, DPNI_VER_MINOR);
1909 ls_dev->mc_io = priv->mc_io;
1910 ls_dev->mc_handle = priv->mc_token;
1912 err = dpni_reset(priv->mc_io, 0, priv->mc_token);
1914 dev_err(dev, "dpni_reset() failed\n");
1918 err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
1921 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
1925 err = set_buffer_layout(priv);
1932 dpni_close(priv->mc_io, 0, priv->mc_token);
1937 static void free_dpni(struct dpaa2_eth_priv *priv)
1941 err = dpni_reset(priv->mc_io, 0, priv->mc_token);
1943 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
1946 dpni_close(priv->mc_io, 0, priv->mc_token);
1949 static int setup_rx_flow(struct dpaa2_eth_priv *priv,
1950 struct dpaa2_eth_fq *fq)
1952 struct device *dev = priv->net_dev->dev.parent;
1953 struct dpni_queue queue;
1954 struct dpni_queue_id qid;
1955 struct dpni_taildrop td;
1958 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
1959 DPNI_QUEUE_RX, 0, fq->flowid, &queue, &qid);
1961 dev_err(dev, "dpni_get_queue(RX) failed\n");
1965 fq->fqid = qid.fqid;
1967 queue.destination.id = fq->channel->dpcon_id;
1968 queue.destination.type = DPNI_DEST_DPCON;
1969 queue.destination.priority = 1;
1970 queue.user_context = (u64)(uintptr_t)fq;
1971 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
1972 DPNI_QUEUE_RX, 0, fq->flowid,
1973 DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
1976 dev_err(dev, "dpni_set_queue(RX) failed\n");
1981 td.threshold = DPAA2_ETH_TAILDROP_THRESH;
1982 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token, DPNI_CP_QUEUE,
1983 DPNI_QUEUE_RX, 0, fq->flowid, &td);
1985 dev_err(dev, "dpni_set_threshold() failed\n");
1992 static int setup_tx_flow(struct dpaa2_eth_priv *priv,
1993 struct dpaa2_eth_fq *fq)
1995 struct device *dev = priv->net_dev->dev.parent;
1996 struct dpni_queue queue;
1997 struct dpni_queue_id qid;
2000 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2001 DPNI_QUEUE_TX, 0, fq->flowid, &queue, &qid);
2003 dev_err(dev, "dpni_get_queue(TX) failed\n");
2007 fq->tx_qdbin = qid.qdbin;
2009 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2010 DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
2013 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
2017 fq->fqid = qid.fqid;
2019 queue.destination.id = fq->channel->dpcon_id;
2020 queue.destination.type = DPNI_DEST_DPCON;
2021 queue.destination.priority = 0;
2022 queue.user_context = (u64)(uintptr_t)fq;
2023 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
2024 DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
2025 DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
2028 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
2035 /* Hash key is a 5-tuple: IPsrc, IPdst, IPnextproto, L4src, L4dst */
2036 static const struct dpaa2_eth_hash_fields hash_fields[] = {
2039 .rxnfc_field = RXH_IP_SRC,
2040 .cls_prot = NET_PROT_IP,
2041 .cls_field = NH_FLD_IP_SRC,
2044 .rxnfc_field = RXH_IP_DST,
2045 .cls_prot = NET_PROT_IP,
2046 .cls_field = NH_FLD_IP_DST,
2049 .rxnfc_field = RXH_L3_PROTO,
2050 .cls_prot = NET_PROT_IP,
2051 .cls_field = NH_FLD_IP_PROTO,
2054 /* Using UDP ports, this is functionally equivalent to raw
2055 * byte pairs from L4 header.
2057 .rxnfc_field = RXH_L4_B_0_1,
2058 .cls_prot = NET_PROT_UDP,
2059 .cls_field = NH_FLD_UDP_PORT_SRC,
2062 .rxnfc_field = RXH_L4_B_2_3,
2063 .cls_prot = NET_PROT_UDP,
2064 .cls_field = NH_FLD_UDP_PORT_DST,
2069 /* Set RX hash options
2070 * flags is a combination of RXH_ bits
2072 static int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
2074 struct device *dev = net_dev->dev.parent;
2075 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2076 struct dpkg_profile_cfg cls_cfg;
2077 struct dpni_rx_tc_dist_cfg dist_cfg;
2082 if (!dpaa2_eth_hash_enabled(priv)) {
2083 dev_dbg(dev, "Hashing support is not enabled\n");
2087 memset(&cls_cfg, 0, sizeof(cls_cfg));
2089 for (i = 0; i < ARRAY_SIZE(hash_fields); i++) {
2090 struct dpkg_extract *key =
2091 &cls_cfg.extracts[cls_cfg.num_extracts];
2093 if (!(flags & hash_fields[i].rxnfc_field))
2096 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
2097 dev_err(dev, "error adding key extraction rule, too many rules?\n");
2101 key->type = DPKG_EXTRACT_FROM_HDR;
2102 key->extract.from_hdr.prot = hash_fields[i].cls_prot;
2103 key->extract.from_hdr.type = DPKG_FULL_FIELD;
2104 key->extract.from_hdr.field = hash_fields[i].cls_field;
2105 cls_cfg.num_extracts++;
2107 priv->rx_hash_fields |= hash_fields[i].rxnfc_field;
2110 dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
2114 err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
2116 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
2120 memset(&dist_cfg, 0, sizeof(dist_cfg));
2122 /* Prepare for setting the rx dist */
2123 dist_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
2124 DPAA2_CLASSIFIER_DMA_SIZE,
2126 if (dma_mapping_error(dev, dist_cfg.key_cfg_iova)) {
2127 dev_err(dev, "DMA mapping failed\n");
2132 dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
2133 dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
2135 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, 0, &dist_cfg);
2136 dma_unmap_single(dev, dist_cfg.key_cfg_iova,
2137 DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE);
2139 dev_err(dev, "dpni_set_rx_tc_dist() error %d\n", err);
2147 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
2148 * frame queues and channels
2150 static int bind_dpni(struct dpaa2_eth_priv *priv)
2152 struct net_device *net_dev = priv->net_dev;
2153 struct device *dev = net_dev->dev.parent;
2154 struct dpni_pools_cfg pools_params;
2155 struct dpni_error_cfg err_cfg;
2159 pools_params.num_dpbp = 1;
2160 pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
2161 pools_params.pools[0].backup_pool = 0;
2162 pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUF_SIZE;
2163 err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
2165 dev_err(dev, "dpni_set_pools() failed\n");
2169 /* have the interface implicitly distribute traffic based on
2170 * the default hash key
2172 err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT);
2174 dev_err(dev, "Failed to configure hashing\n");
2176 /* Configure handling of error frames */
2177 err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
2178 err_cfg.set_frame_annotation = 1;
2179 err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
2180 err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
2183 dev_err(dev, "dpni_set_errors_behavior failed\n");
2187 /* Configure Rx and Tx conf queues to generate CDANs */
2188 for (i = 0; i < priv->num_fqs; i++) {
2189 switch (priv->fq[i].type) {
2191 err = setup_rx_flow(priv, &priv->fq[i]);
2193 case DPAA2_TX_CONF_FQ:
2194 err = setup_tx_flow(priv, &priv->fq[i]);
2197 dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
2204 err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
2205 DPNI_QUEUE_TX, &priv->tx_qdid);
2207 dev_err(dev, "dpni_get_qdid() failed\n");
2214 /* Allocate rings for storing incoming frame descriptors */
2215 static int alloc_rings(struct dpaa2_eth_priv *priv)
2217 struct net_device *net_dev = priv->net_dev;
2218 struct device *dev = net_dev->dev.parent;
2221 for (i = 0; i < priv->num_channels; i++) {
2222 priv->channel[i]->store =
2223 dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
2224 if (!priv->channel[i]->store) {
2225 netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
2233 for (i = 0; i < priv->num_channels; i++) {
2234 if (!priv->channel[i]->store)
2236 dpaa2_io_store_destroy(priv->channel[i]->store);
2242 static void free_rings(struct dpaa2_eth_priv *priv)
2246 for (i = 0; i < priv->num_channels; i++)
2247 dpaa2_io_store_destroy(priv->channel[i]->store);
2250 static int set_mac_addr(struct dpaa2_eth_priv *priv)
2252 struct net_device *net_dev = priv->net_dev;
2253 struct device *dev = net_dev->dev.parent;
2254 u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
2257 /* Get firmware address, if any */
2258 err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
2260 dev_err(dev, "dpni_get_port_mac_addr() failed\n");
2264 /* Get DPNI attributes address, if any */
2265 err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
2268 dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
2272 /* First check if firmware has any address configured by bootloader */
2273 if (!is_zero_ether_addr(mac_addr)) {
2274 /* If the DPMAC addr != DPNI addr, update it */
2275 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
2276 err = dpni_set_primary_mac_addr(priv->mc_io, 0,
2280 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
2284 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
2285 } else if (is_zero_ether_addr(dpni_mac_addr)) {
2286 /* No MAC address configured, fill in net_dev->dev_addr
2289 eth_hw_addr_random(net_dev);
2290 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
2292 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
2295 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
2299 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
2300 * practical purposes, this will be our "permanent" mac address,
2301 * at least until the next reboot. This move will also permit
2302 * register_netdevice() to properly fill up net_dev->perm_addr.
2304 net_dev->addr_assign_type = NET_ADDR_PERM;
2306 /* NET_ADDR_PERM is default, all we have to do is
2307 * fill in the device addr.
2309 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
2315 static int netdev_init(struct net_device *net_dev)
2317 struct device *dev = net_dev->dev.parent;
2318 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2319 u8 bcast_addr[ETH_ALEN];
2323 net_dev->netdev_ops = &dpaa2_eth_ops;
2325 err = set_mac_addr(priv);
2329 /* Explicitly add the broadcast address to the MAC filtering table */
2330 eth_broadcast_addr(bcast_addr);
2331 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
2333 dev_err(dev, "dpni_add_mac_addr() failed\n");
2337 /* Set MTU upper limit; lower limit is 68B (default value) */
2338 net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
2339 err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
2342 dev_err(dev, "dpni_set_max_frame_length() failed\n");
2346 /* Set actual number of queues in the net device */
2347 num_queues = dpaa2_eth_queue_count(priv);
2348 err = netif_set_real_num_tx_queues(net_dev, num_queues);
2350 dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
2353 err = netif_set_real_num_rx_queues(net_dev, num_queues);
2355 dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
2359 /* Our .ndo_init will be called herein */
2360 err = register_netdev(net_dev);
2362 dev_err(dev, "register_netdev() failed\n");
2369 static int poll_link_state(void *arg)
2371 struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
2374 while (!kthread_should_stop()) {
2375 err = link_state_update(priv);
2379 msleep(DPAA2_ETH_LINK_STATE_REFRESH);
2385 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
2388 struct device *dev = (struct device *)arg;
2389 struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
2390 struct net_device *net_dev = dev_get_drvdata(dev);
2393 err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
2394 DPNI_IRQ_INDEX, &status);
2395 if (unlikely(err)) {
2396 netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
2400 if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
2401 link_state_update(netdev_priv(net_dev));
2406 static int setup_irqs(struct fsl_mc_device *ls_dev)
2409 struct fsl_mc_device_irq *irq;
2411 err = fsl_mc_allocate_irqs(ls_dev);
2413 dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
2417 irq = ls_dev->irqs[0];
2418 err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
2419 NULL, dpni_irq0_handler_thread,
2420 IRQF_NO_SUSPEND | IRQF_ONESHOT,
2421 dev_name(&ls_dev->dev), &ls_dev->dev);
2423 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
2427 err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
2428 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED);
2430 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
2434 err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
2437 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
2444 devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
2446 fsl_mc_free_irqs(ls_dev);
2451 static void add_ch_napi(struct dpaa2_eth_priv *priv)
2454 struct dpaa2_eth_channel *ch;
2456 for (i = 0; i < priv->num_channels; i++) {
2457 ch = priv->channel[i];
2458 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
2459 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
2464 static void del_ch_napi(struct dpaa2_eth_priv *priv)
2467 struct dpaa2_eth_channel *ch;
2469 for (i = 0; i < priv->num_channels; i++) {
2470 ch = priv->channel[i];
2471 netif_napi_del(&ch->napi);
2475 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
2478 struct net_device *net_dev = NULL;
2479 struct dpaa2_eth_priv *priv = NULL;
2482 dev = &dpni_dev->dev;
2485 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_TX_QUEUES);
2487 dev_err(dev, "alloc_etherdev_mq() failed\n");
2491 SET_NETDEV_DEV(net_dev, dev);
2492 dev_set_drvdata(dev, net_dev);
2494 priv = netdev_priv(net_dev);
2495 priv->net_dev = net_dev;
2497 priv->iommu_domain = iommu_get_domain_for_dev(dev);
2499 /* Obtain a MC portal */
2500 err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
2504 err = -EPROBE_DEFER;
2506 dev_err(dev, "MC portal allocation failed\n");
2507 goto err_portal_alloc;
2510 /* MC objects initialization and configuration */
2511 err = setup_dpni(dpni_dev);
2513 goto err_dpni_setup;
2515 err = setup_dpio(priv);
2517 goto err_dpio_setup;
2521 err = setup_dpbp(priv);
2523 goto err_dpbp_setup;
2525 err = bind_dpni(priv);
2529 /* Add a NAPI context for each channel */
2532 /* Percpu statistics */
2533 priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
2534 if (!priv->percpu_stats) {
2535 dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
2537 goto err_alloc_percpu_stats;
2539 priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
2540 if (!priv->percpu_extras) {
2541 dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
2543 goto err_alloc_percpu_extras;
2546 err = netdev_init(net_dev);
2548 goto err_netdev_init;
2550 /* Configure checksum offload based on current interface flags */
2551 err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
2555 err = set_tx_csum(priv, !!(net_dev->features &
2556 (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
2560 err = alloc_rings(priv);
2562 goto err_alloc_rings;
2564 net_dev->ethtool_ops = &dpaa2_ethtool_ops;
2566 err = setup_irqs(dpni_dev);
2568 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
2569 priv->poll_thread = kthread_run(poll_link_state, priv,
2570 "%s_poll_link", net_dev->name);
2571 if (IS_ERR(priv->poll_thread)) {
2572 netdev_err(net_dev, "Error starting polling thread\n");
2573 goto err_poll_thread;
2575 priv->do_link_poll = true;
2578 dev_info(dev, "Probed interface %s\n", net_dev->name);
2585 unregister_netdev(net_dev);
2587 free_percpu(priv->percpu_extras);
2588 err_alloc_percpu_extras:
2589 free_percpu(priv->percpu_stats);
2590 err_alloc_percpu_stats:
2599 fsl_mc_portal_free(priv->mc_io);
2601 dev_set_drvdata(dev, NULL);
2602 free_netdev(net_dev);
2607 static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
2610 struct net_device *net_dev;
2611 struct dpaa2_eth_priv *priv;
2614 net_dev = dev_get_drvdata(dev);
2615 priv = netdev_priv(net_dev);
2617 unregister_netdev(net_dev);
2619 if (priv->do_link_poll)
2620 kthread_stop(priv->poll_thread);
2622 fsl_mc_free_irqs(ls_dev);
2625 free_percpu(priv->percpu_stats);
2626 free_percpu(priv->percpu_extras);
2633 fsl_mc_portal_free(priv->mc_io);
2635 free_netdev(net_dev);
2637 dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
2642 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
2644 .vendor = FSL_MC_VENDOR_FREESCALE,
2649 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
2651 static struct fsl_mc_driver dpaa2_eth_driver = {
2653 .name = KBUILD_MODNAME,
2654 .owner = THIS_MODULE,
2656 .probe = dpaa2_eth_probe,
2657 .remove = dpaa2_eth_remove,
2658 .match_id_table = dpaa2_eth_match_id_table
2661 module_fsl_mc_driver(dpaa2_eth_driver);