2 * Copyright (C) 2014 STMicroelectronics
4 * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
6 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_address.h>
22 #include <linux/clk.h>
23 #include <linux/phy/phy.h>
24 #include <linux/delay.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
29 #include <dt-bindings/phy/phy.h>
32 #define MIPHY_CONF_RESET 0x00
33 #define RST_APPLI_SW BIT(0)
34 #define RST_CONF_SW BIT(1)
35 #define RST_MACRO_SW BIT(2)
37 #define MIPHY_RESET 0x01
38 #define RST_PLL_SW BIT(0)
39 #define RST_COMP_SW BIT(2)
41 #define MIPHY_STATUS_1 0x02
42 #define PHY_RDY BIT(0)
43 #define HFC_RDY BIT(1)
44 #define HFC_PLL BIT(2)
46 #define MIPHY_CONTROL 0x04
47 #define TERM_EN_SW BIT(2)
48 #define DIS_LINK_RST BIT(3)
49 #define AUTO_RST_RX BIT(4)
50 #define PX_RX_POL BIT(5)
52 #define MIPHY_BOUNDARY_SEL 0x0a
54 #define SSC_SEL BIT(4)
55 #define GENSEL_SEL BIT(0)
57 #define MIPHY_BOUNDARY_1 0x0b
58 #define MIPHY_BOUNDARY_2 0x0c
59 #define SSC_EN_SW BIT(2)
61 #define MIPHY_PLL_CLKREF_FREQ 0x0d
62 #define MIPHY_SPEED 0x0e
63 #define TX_SPDSEL_80DEC 0
64 #define TX_SPDSEL_40DEC 1
65 #define TX_SPDSEL_20DEC 2
66 #define RX_SPDSEL_80DEC 0
67 #define RX_SPDSEL_40DEC (1 << 2)
68 #define RX_SPDSEL_20DEC (2 << 2)
70 #define MIPHY_CONF 0x0f
71 #define MIPHY_CTRL_TEST_SEL 0x20
72 #define MIPHY_CTRL_TEST_1 0x21
73 #define MIPHY_CTRL_TEST_2 0x22
74 #define MIPHY_CTRL_TEST_3 0x23
75 #define MIPHY_CTRL_TEST_4 0x24
76 #define MIPHY_FEEDBACK_TEST 0x25
77 #define MIPHY_DEBUG_BUS 0x26
78 #define MIPHY_DEBUG_STATUS_MSB 0x27
79 #define MIPHY_DEBUG_STATUS_LSB 0x28
80 #define MIPHY_PWR_RAIL_1 0x29
81 #define MIPHY_PWR_RAIL_2 0x2a
82 #define MIPHY_SYNCHAR_CONTROL 0x30
84 #define MIPHY_COMP_FSM_1 0x3a
85 #define COMP_START BIT(6)
87 #define MIPHY_COMP_FSM_6 0x3f
88 #define COMP_DONE BIT(7)
90 #define MIPHY_COMP_POSTP 0x42
91 #define MIPHY_TX_CTRL_1 0x49
92 #define TX_REG_STEP_0V 0
93 #define TX_REG_STEP_P_25MV 1
94 #define TX_REG_STEP_P_50MV 2
95 #define TX_REG_STEP_N_25MV 7
96 #define TX_REG_STEP_N_50MV 6
97 #define TX_REG_STEP_N_75MV 5
99 #define MIPHY_TX_CTRL_2 0x4a
100 #define TX_SLEW_SW_40_PS 0
101 #define TX_SLEW_SW_80_PS 1
102 #define TX_SLEW_SW_120_PS 2
104 #define MIPHY_TX_CTRL_3 0x4b
105 #define MIPHY_TX_CAL_MAN 0x4e
106 #define TX_SLEW_CAL_MAN_EN BIT(0)
108 #define MIPHY_TST_BIAS_BOOST_2 0x62
109 #define MIPHY_BIAS_BOOST_1 0x63
110 #define MIPHY_BIAS_BOOST_2 0x64
111 #define MIPHY_RX_DESBUFF_FDB_2 0x67
112 #define MIPHY_RX_DESBUFF_FDB_3 0x68
113 #define MIPHY_SIGDET_COMPENS1 0x69
114 #define MIPHY_SIGDET_COMPENS2 0x6a
115 #define MIPHY_JITTER_PERIOD 0x6b
116 #define MIPHY_JITTER_AMPLITUDE_1 0x6c
117 #define MIPHY_JITTER_AMPLITUDE_2 0x6d
118 #define MIPHY_JITTER_AMPLITUDE_3 0x6e
119 #define MIPHY_RX_K_GAIN 0x78
120 #define MIPHY_RX_BUFFER_CTRL 0x7a
121 #define VGA_GAIN BIT(0)
122 #define EQ_DC_GAIN BIT(2)
123 #define EQ_BOOST_GAIN BIT(3)
125 #define MIPHY_RX_VGA_GAIN 0x7b
126 #define MIPHY_RX_EQU_GAIN_1 0x7f
127 #define MIPHY_RX_EQU_GAIN_2 0x80
128 #define MIPHY_RX_EQU_GAIN_3 0x81
129 #define MIPHY_RX_CAL_CTRL_1 0x97
130 #define MIPHY_RX_CAL_CTRL_2 0x98
132 #define MIPHY_RX_CAL_OFFSET_CTRL 0x99
133 #define CAL_OFFSET_VGA_64 (0x03 << 0)
134 #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2)
135 #define VGA_OFFSET_POLARITY BIT(4)
136 #define OFFSET_COMPENSATION_EN BIT(6)
138 #define MIPHY_RX_CAL_VGA_STEP 0x9a
139 #define MIPHY_RX_CAL_EYE_MIN 0x9d
140 #define MIPHY_RX_CAL_OPT_LENGTH 0x9f
141 #define MIPHY_RX_LOCK_CTRL_1 0xc1
142 #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
143 #define MIPHY_RX_LOCK_STEP 0xc4
145 #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
146 #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
147 #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
148 #define MIPHY_RX_SIGDET_DATA_SEL 0xcc
149 #define EN_ULTRA_LOW_POWER BIT(0)
150 #define EN_FIRST_HALF BIT(1)
151 #define EN_SECOND_HALF BIT(2)
152 #define EN_DIGIT_SIGNAL_CHECK BIT(3)
154 #define MIPHY_RX_POWER_CTRL_1 0xcd
155 #define MIPHY_RX_POWER_CTRL_2 0xce
156 #define MIPHY_PLL_CALSET_CTRL 0xd3
157 #define MIPHY_PLL_CALSET_1 0xd4
158 #define MIPHY_PLL_CALSET_2 0xd5
159 #define MIPHY_PLL_CALSET_3 0xd6
160 #define MIPHY_PLL_CALSET_4 0xd7
161 #define MIPHY_PLL_SBR_1 0xe3
162 #define SET_NEW_CHANGE BIT(1)
164 #define MIPHY_PLL_SBR_2 0xe4
165 #define MIPHY_PLL_SBR_3 0xe5
166 #define MIPHY_PLL_SBR_4 0xe6
167 #define MIPHY_PLL_COMMON_MISC_2 0xe9
168 #define START_ACT_FILT BIT(6)
170 #define MIPHY_PLL_SPAREIN 0xeb
173 * On STiH407 the glue logic can be different among MiPHY devices; for example:
174 * MiPHY0: OSC_FORCE_EXT means:
175 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
176 * MiPHY1: OSC_FORCE_EXT means:
177 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
178 * Some devices have not the possibility to check if the osc is ready.
180 #define MIPHY_OSC_FORCE_EXT BIT(3)
181 #define MIPHY_OSC_RDY BIT(5)
183 #define MIPHY_CTRL_MASK 0x0f
184 #define MIPHY_CTRL_DEFAULT 0
185 #define MIPHY_CTRL_SYNC_D_EN BIT(2)
187 /* SATA / PCIe defines */
188 #define SATA_CTRL_MASK 0x07
189 #define PCIE_CTRL_MASK 0xff
190 #define SATA_CTRL_SELECT_SATA 1
191 #define SATA_CTRL_SELECT_PCIE 0
192 #define SYSCFG_PCIE_PCIE_VAL 0x80
193 #define SATA_SPDMODE 1
195 #define MIPHY_SATA_BANK_NB 3
196 #define MIPHY_PCIE_BANK_NB 2
206 struct miphy28lp_phy {
208 struct miphy28lp_dev *phydev;
210 void __iomem *pipebase;
218 struct reset_control *miphy_rst;
222 /* Sysconfig registers offsets needed to configure the device */
223 u32 syscfg_reg[SYSCFG_REG_MAX];
227 struct miphy28lp_dev {
229 struct regmap *regmap;
230 struct mutex miphy_mutex;
231 struct miphy28lp_phy **phys;
235 struct miphy_initval {
240 enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
242 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
253 static struct pll_ratio sata_pll_ratio = {
262 static struct pll_ratio pcie_pll_ratio = {
271 static struct pll_ratio usb3_pll_ratio = {
280 struct miphy28lp_pll_gen {
296 static struct miphy28lp_pll_gen sata_pll_gen[] = {
299 .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC,
300 .bias_boost_1 = 0x00,
301 .bias_boost_2 = 0xae,
304 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
306 .rx_equ_gain_1 = 0x7d,
307 .rx_equ_gain_2 = 0x56,
308 .rx_equ_gain_3 = 0x00,
312 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
313 .bias_boost_1 = 0x00,
314 .bias_boost_2 = 0xae,
317 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
319 .rx_equ_gain_1 = 0x7d,
320 .rx_equ_gain_2 = 0x56,
321 .rx_equ_gain_3 = 0x00,
325 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
326 .bias_boost_1 = 0x00,
327 .bias_boost_2 = 0xae,
330 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
332 .rx_equ_gain_1 = 0x7d,
333 .rx_equ_gain_2 = 0x56,
334 .rx_equ_gain_3 = 0x00,
338 static struct miphy28lp_pll_gen pcie_pll_gen[] = {
341 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
342 .bias_boost_1 = 0x00,
343 .bias_boost_2 = 0xa5,
344 .tx_ctrl_1 = TX_REG_STEP_N_25MV,
348 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
350 .rx_equ_gain_1 = 0x79,
351 .rx_equ_gain_2 = 0x56,
355 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
356 .bias_boost_1 = 0x00,
357 .bias_boost_2 = 0xa5,
358 .tx_ctrl_1 = TX_REG_STEP_N_25MV,
362 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
364 .rx_equ_gain_1 = 0x78,
365 .rx_equ_gain_2 = 0x07,
369 static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy)
371 void __iomem *base = miphy_phy->base;
374 /* Putting Macro in reset */
375 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
377 val = RST_APPLI_SW | RST_CONF_SW;
378 writeb_relaxed(val, base + MIPHY_CONF_RESET);
380 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
382 /* Bringing the MIPHY-CPU registers out of reset */
383 if (miphy_phy->type == PHY_TYPE_PCIE) {
384 val = AUTO_RST_RX | TERM_EN_SW;
385 writeb_relaxed(val, base + MIPHY_CONTROL);
387 val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST;
388 writeb_relaxed(val, base + MIPHY_CONTROL);
392 static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy,
393 struct pll_ratio *pll_ratio)
395 void __iomem *base = miphy_phy->base;
398 /* Applying PLL Settings */
399 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
400 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
403 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
404 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
405 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
406 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
407 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
409 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);
411 val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN;
412 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);
414 val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
416 if (miphy_phy->type != PHY_TYPE_SATA)
417 val |= OFFSET_COMPENSATION_EN;
419 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
421 if (miphy_phy->type == PHY_TYPE_USB3) {
422 writeb_relaxed(0x00, base + MIPHY_CONF);
423 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
424 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);
425 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);
426 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);
428 val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF;
429 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);
434 static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy)
436 void __iomem *base = miphy_phy->base;
439 for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) {
440 struct miphy28lp_pll_gen *gen = &sata_pll_gen[i];
442 /* Banked settings */
443 writeb_relaxed(gen->bank, base + MIPHY_CONF);
444 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
445 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
446 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
448 /* TX buffer Settings */
449 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
450 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
452 /* RX Buffer Settings */
453 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
454 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
455 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
456 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
457 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);
461 static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy)
463 void __iomem *base = miphy_phy->base;
466 for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) {
467 struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i];
469 /* Banked settings */
470 writeb_relaxed(gen->bank, base + MIPHY_CONF);
471 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
472 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
473 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
475 /* TX buffer Settings */
476 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);
477 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
478 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
480 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);
482 /* RX Buffer Settings */
483 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
484 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
485 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
486 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
490 static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
494 /* Waiting for Compensation to complete */
495 return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6,
496 val, val & COMP_DONE, 1, 5 * USEC_PER_SEC);
500 static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy,
501 struct pll_ratio *pll_ratio)
503 void __iomem *base = miphy_phy->base;
505 /* Poll for HFC ready after reset release */
506 /* Compensation measurement */
507 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);
509 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
510 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
511 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
513 if (miphy_phy->type == PHY_TYPE_PCIE)
514 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
516 writeb_relaxed(0x00, base + MIPHY_RESET);
517 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
518 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
520 /* TX compensation offset to re-center TX impedance */
521 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
523 if (miphy_phy->type == PHY_TYPE_PCIE)
524 return miphy28lp_wait_compensation(miphy_phy);
529 static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
531 void __iomem *base = miphy_phy->base;
535 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
536 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
537 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);
539 val = RST_COMP_SW | RST_PLL_SW;
540 writeb_relaxed(val, base + MIPHY_RESET);
542 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
543 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
544 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
545 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
546 writeb_relaxed(0x00, base + MIPHY_RESET);
547 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
548 writeb_relaxed(0x00, base + MIPHY_CONF);
549 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
550 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
551 writeb_relaxed(0x00, base + MIPHY_CONF);
552 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
553 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
554 writeb_relaxed(0x00, base + MIPHY_CONF);
557 static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
559 void __iomem *base = miphy_phy->base;
562 /* Compensate Tx impedance to avoid out of range values */
564 * Enable the SSC on PLL for all banks
565 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
567 val = readb_relaxed(base + MIPHY_BOUNDARY_2);
569 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
571 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
573 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
575 for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
576 writeb_relaxed(val, base + MIPHY_CONF);
578 /* Add value to each reference clock cycle */
579 /* and define the period length of the SSC */
580 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
581 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
582 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
584 /* Clear any previous request */
585 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
587 /* requests the PLL to take in account new parameters */
588 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
590 /* To be sure there is no other pending requests */
591 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
595 static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
597 void __iomem *base = miphy_phy->base;
600 /* Compensate Tx impedance to avoid out of range values */
602 * Enable the SSC on PLL for all banks
603 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
605 val = readb_relaxed(base + MIPHY_BOUNDARY_2);
607 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
609 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
611 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
613 for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
614 writeb_relaxed(val, base + MIPHY_CONF);
616 /* Validate Step component */
617 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
618 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
620 /* Validate Period component */
621 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
622 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
624 /* Clear any previous request */
625 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
627 /* requests the PLL to take in account new parameters */
628 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
630 /* To be sure there is no other pending requests */
631 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
635 static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
637 /* Compensate Tx impedance to avoid out of range values */
638 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
641 static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
643 void __iomem *base = miphy_phy->base;
647 /* Putting Macro in reset */
648 miphy28lp_set_reset(miphy_phy);
650 /* PLL calibration */
651 miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio);
653 /* Banked settings Gen1/Gen2/Gen3 */
654 miphy28lp_sata_config_gen(miphy_phy);
657 /* Input bridge enable, manual input bridge control */
658 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
660 /* Macro out of reset */
661 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
663 /* Poll for HFC ready after reset release */
664 /* Compensation measurement */
665 err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio);
669 if (miphy_phy->px_rx_pol_inv) {
670 /* Invert Rx polarity */
671 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
673 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
677 miphy_sata_tune_ssc(miphy_phy);
679 if (miphy_phy->tx_impedance)
680 miphy_tune_tx_impedance(miphy_phy);
685 static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
687 void __iomem *base = miphy_phy->base;
690 /* Putting Macro in reset */
691 miphy28lp_set_reset(miphy_phy);
693 /* PLL calibration */
694 miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio);
696 /* Banked settings Gen1/Gen2 */
697 miphy28lp_pcie_config_gen(miphy_phy);
700 /* Input bridge enable, manual input bridge control */
701 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
703 /* Macro out of reset */
704 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
706 /* Poll for HFC ready after reset release */
707 /* Compensation measurement */
708 err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio);
713 miphy_pcie_tune_ssc(miphy_phy);
715 if (miphy_phy->tx_impedance)
716 miphy_tune_tx_impedance(miphy_phy);
722 static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
724 void __iomem *base = miphy_phy->base;
727 /* Putting Macro in reset */
728 miphy28lp_set_reset(miphy_phy);
730 /* PLL calibration */
731 miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio);
733 /* Writing The Speed Rate */
734 writeb_relaxed(0x00, base + MIPHY_CONF);
736 val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC;
737 writeb_relaxed(val, base + MIPHY_SPEED);
739 /* RX Channel compensation and calibration */
740 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
741 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
742 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
744 val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY |
745 CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
746 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
747 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
748 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
750 val = EQ_DC_GAIN | VGA_GAIN;
751 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);
752 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
753 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
755 /* TX compensation offset to re-center TX impedance */
756 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
758 /* Enable GENSEL_SEL and SSC */
759 /* TX_SEL=0 swing preemp forced by pipe registres */
760 val = SSC_SEL | GENSEL_SEL;
761 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
763 /* MIPHY Bias boost */
764 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
765 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
768 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);
770 /* MIPHY TX control */
771 writeb_relaxed(0x00, base + MIPHY_CONF);
773 /* Validate Step component */
774 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
775 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
777 /* Validate Period component */
778 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
779 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);
781 /* Clear any previous request */
782 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
784 /* requests the PLL to take in account new parameters */
785 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
787 /* To be sure there is no other pending requests */
788 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
790 /* Rx PI controller settings */
791 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
793 /* MIPHY RX input bridge control */
794 /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
795 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
796 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
797 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
799 /* MIPHY Reset for usb3 */
800 miphy28_usb3_miphy_reset(miphy_phy);
803 static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
805 u8 mask = HFC_PLL | HFC_RDY;
809 * For PCIe and USB3 check only that PLL and HFC are ready
810 * For SATA check also that phy is ready!
812 if (miphy_phy->type == PHY_TYPE_SATA)
815 return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1,
816 val, (val & mask) == mask, 1,
820 static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
822 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
825 if (!miphy_phy->osc_rdy)
828 if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])
831 return regmap_read_poll_timeout(miphy_dev->regmap,
832 miphy_phy->syscfg_reg[SYSCFG_STATUS],
833 val, val & MIPHY_OSC_RDY, 1,
837 static int miphy28lp_get_resource_byname(struct device_node *child,
838 char *rname, struct resource *res)
842 index = of_property_match_string(child, "reg-names", rname);
846 return of_address_to_resource(child, index, res);
849 static int miphy28lp_get_one_addr(struct device *dev,
850 struct device_node *child, char *rname,
856 ret = miphy28lp_get_resource_byname(child, rname, &res);
858 *base = devm_ioremap(dev, res.start, resource_size(&res));
860 dev_err(dev, "failed to ioremap %s address region\n"
869 /* MiPHY reset and sysconf setup */
870 static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
873 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
875 if (!miphy_phy->syscfg_reg[SYSCFG_CTRL])
878 err = reset_control_assert(miphy_phy->miphy_rst);
880 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
884 if (miphy_phy->osc_force_ext)
885 miphy_val |= MIPHY_OSC_FORCE_EXT;
887 regmap_update_bits(miphy_dev->regmap,
888 miphy_phy->syscfg_reg[SYSCFG_CTRL],
889 MIPHY_CTRL_MASK, miphy_val);
891 err = reset_control_deassert(miphy_phy->miphy_rst);
893 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
897 return miphy_osc_is_ready(miphy_phy);
900 static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
902 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
903 int err, sata_conf = SATA_CTRL_SELECT_SATA;
905 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
906 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) ||
910 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
912 /* Configure the glue-logic */
913 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
915 regmap_update_bits(miphy_dev->regmap,
916 miphy_phy->syscfg_reg[SYSCFG_SATA],
917 SATA_CTRL_MASK, sata_conf);
919 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
920 PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
922 /* MiPHY path and clocking init */
923 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
926 dev_err(miphy_dev->dev, "SATA phy setup failed\n");
930 /* initialize miphy */
931 miphy28lp_configure_sata(miphy_phy);
933 return miphy_is_ready(miphy_phy);
936 static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
938 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
941 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
942 (!miphy_phy->syscfg_reg[SYSCFG_PCI])
943 || (!miphy_phy->base) || (!miphy_phy->pipebase))
946 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
948 /* Configure the glue-logic */
949 regmap_update_bits(miphy_dev->regmap,
950 miphy_phy->syscfg_reg[SYSCFG_SATA],
951 SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
953 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
954 PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL);
956 /* MiPHY path and clocking init */
957 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
960 dev_err(miphy_dev->dev, "PCIe phy setup failed\n");
964 /* initialize miphy */
965 err = miphy28lp_configure_pcie(miphy_phy);
969 /* PIPE Wrapper Configuration */
970 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
971 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
972 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
973 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
974 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
975 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
977 /* Wait for phy_ready */
978 return miphy_is_ready(miphy_phy);
981 static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
983 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
986 if ((!miphy_phy->base) || (!miphy_phy->pipebase))
989 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
991 /* MiPHY path and clocking init */
992 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
994 dev_err(miphy_dev->dev, "USB3 phy setup failed\n");
998 /* initialize miphy */
999 miphy28lp_configure_usb3(miphy_phy);
1001 /* PIPE Wrapper Configuration */
1002 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
1003 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
1004 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
1005 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
1006 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
1007 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
1009 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
1010 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
1011 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
1012 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
1013 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
1014 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
1015 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
1016 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
1017 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
1019 return miphy_is_ready(miphy_phy);
1022 static int miphy28lp_init(struct phy *phy)
1024 struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
1025 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1028 mutex_lock(&miphy_dev->miphy_mutex);
1030 switch (miphy_phy->type) {
1033 ret = miphy28lp_init_sata(miphy_phy);
1036 ret = miphy28lp_init_pcie(miphy_phy);
1039 ret = miphy28lp_init_usb3(miphy_phy);
1046 mutex_unlock(&miphy_dev->miphy_mutex);
1051 static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
1053 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1054 struct device_node *phynode = miphy_phy->phy->dev.of_node;
1057 if ((miphy_phy->type != PHY_TYPE_SATA) &&
1058 (miphy_phy->type != PHY_TYPE_PCIE) &&
1059 (miphy_phy->type != PHY_TYPE_USB3)) {
1063 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,
1064 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],
1069 if ((miphy_phy->type == PHY_TYPE_PCIE) ||
1070 (miphy_phy->type == PHY_TYPE_USB3)) {
1071 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",
1072 &miphy_phy->pipebase);
1080 static struct phy *miphy28lp_xlate(struct device *dev,
1081 struct of_phandle_args *args)
1083 struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev);
1084 struct miphy28lp_phy *miphy_phy = NULL;
1085 struct device_node *phynode = args->np;
1088 if (args->args_count != 1) {
1089 dev_err(dev, "Invalid number of cells in 'phy' property\n");
1090 return ERR_PTR(-EINVAL);
1093 for (index = 0; index < miphy_dev->nphys; index++)
1094 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
1095 miphy_phy = miphy_dev->phys[index];
1100 dev_err(dev, "Failed to find appropriate phy\n");
1101 return ERR_PTR(-EINVAL);
1104 miphy_phy->type = args->args[0];
1106 ret = miphy28lp_get_addr(miphy_phy);
1108 return ERR_PTR(ret);
1110 return miphy_phy->phy;
1113 static const struct phy_ops miphy28lp_ops = {
1114 .init = miphy28lp_init,
1115 .owner = THIS_MODULE,
1118 static int miphy28lp_probe_resets(struct device_node *node,
1119 struct miphy28lp_phy *miphy_phy)
1121 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1124 miphy_phy->miphy_rst =
1125 of_reset_control_get_shared(node, "miphy-sw-rst");
1127 if (IS_ERR(miphy_phy->miphy_rst)) {
1128 dev_err(miphy_dev->dev,
1129 "miphy soft reset control not defined\n");
1130 return PTR_ERR(miphy_phy->miphy_rst);
1133 err = reset_control_deassert(miphy_phy->miphy_rst);
1135 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
1142 static int miphy28lp_of_probe(struct device_node *np,
1143 struct miphy28lp_phy *miphy_phy)
1148 miphy_phy->osc_force_ext =
1149 of_property_read_bool(np, "st,osc-force-ext");
1151 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
1153 miphy_phy->px_rx_pol_inv =
1154 of_property_read_bool(np, "st,px_rx_pol_inv");
1156 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
1158 miphy_phy->tx_impedance =
1159 of_property_read_bool(np, "st,tx-impedance-comp");
1161 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
1162 if (!miphy_phy->sata_gen)
1163 miphy_phy->sata_gen = SATA_GEN1;
1165 for (i = 0; i < SYSCFG_REG_MAX; i++) {
1166 if (!of_property_read_u32_index(np, "st,syscfg", i, &ctrlreg))
1167 miphy_phy->syscfg_reg[i] = ctrlreg;
1173 static int miphy28lp_probe(struct platform_device *pdev)
1175 struct device_node *child, *np = pdev->dev.of_node;
1176 struct miphy28lp_dev *miphy_dev;
1177 struct phy_provider *provider;
1181 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
1185 miphy_dev->nphys = of_get_child_count(np);
1186 miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
1187 sizeof(*miphy_dev->phys), GFP_KERNEL);
1188 if (!miphy_dev->phys)
1191 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1192 if (IS_ERR(miphy_dev->regmap)) {
1193 dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
1194 return PTR_ERR(miphy_dev->regmap);
1197 miphy_dev->dev = &pdev->dev;
1199 dev_set_drvdata(&pdev->dev, miphy_dev);
1201 mutex_init(&miphy_dev->miphy_mutex);
1203 for_each_child_of_node(np, child) {
1204 struct miphy28lp_phy *miphy_phy;
1206 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
1213 miphy_dev->phys[port] = miphy_phy;
1215 phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);
1217 dev_err(&pdev->dev, "failed to create PHY\n");
1222 miphy_dev->phys[port]->phy = phy;
1223 miphy_dev->phys[port]->phydev = miphy_dev;
1225 ret = miphy28lp_of_probe(child, miphy_phy);
1229 ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);
1233 phy_set_drvdata(phy, miphy_dev->phys[port]);
1238 provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);
1239 return PTR_ERR_OR_ZERO(provider);
1245 static const struct of_device_id miphy28lp_of_match[] = {
1246 {.compatible = "st,miphy28lp-phy", },
1250 MODULE_DEVICE_TABLE(of, miphy28lp_of_match);
1252 static struct platform_driver miphy28lp_driver = {
1253 .probe = miphy28lp_probe,
1255 .name = "miphy28lp-phy",
1256 .of_match_table = miphy28lp_of_match,
1260 module_platform_driver(miphy28lp_driver);
1262 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
1263 MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
1264 MODULE_LICENSE("GPL v2");