1 // SPDX-License-Identifier: GPL-2.0-only
3 * Spreadtrum mailbox driver
5 * Copyright (c) 2020 Spreadtrum Communications Inc.
8 #include <linux/delay.h>
10 #include <linux/interrupt.h>
12 #include <linux/mailbox_controller.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
17 #define SPRD_MBOX_ID 0x0
18 #define SPRD_MBOX_MSG_LOW 0x4
19 #define SPRD_MBOX_MSG_HIGH 0x8
20 #define SPRD_MBOX_TRIGGER 0xc
21 #define SPRD_MBOX_FIFO_RST 0x10
22 #define SPRD_MBOX_FIFO_STS 0x14
23 #define SPRD_MBOX_IRQ_STS 0x18
24 #define SPRD_MBOX_IRQ_MSK 0x1c
25 #define SPRD_MBOX_LOCK 0x20
26 #define SPRD_MBOX_FIFO_DEPTH 0x24
28 /* Bit and mask definiation for inbox's SPRD_MBOX_FIFO_STS register */
29 #define SPRD_INBOX_FIFO_DELIVER_MASK GENMASK(23, 16)
30 #define SPRD_INBOX_FIFO_OVERLOW_MASK GENMASK(15, 8)
31 #define SPRD_INBOX_FIFO_DELIVER_SHIFT 16
32 #define SPRD_INBOX_FIFO_BUSY_MASK GENMASK(7, 0)
34 /* Bit and mask definiation for SPRD_MBOX_IRQ_STS register */
35 #define SPRD_MBOX_IRQ_CLR BIT(0)
37 /* Bit and mask definiation for outbox's SPRD_MBOX_FIFO_STS register */
38 #define SPRD_OUTBOX_FIFO_FULL BIT(2)
39 #define SPRD_OUTBOX_FIFO_WR_SHIFT 16
40 #define SPRD_OUTBOX_FIFO_RD_SHIFT 24
41 #define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0)
43 /* Bit and mask definiation for inbox's SPRD_MBOX_IRQ_MSK register */
44 #define SPRD_INBOX_FIFO_BLOCK_IRQ BIT(0)
45 #define SPRD_INBOX_FIFO_OVERFLOW_IRQ BIT(1)
46 #define SPRD_INBOX_FIFO_DELIVER_IRQ BIT(2)
47 #define SPRD_INBOX_FIFO_IRQ_MASK GENMASK(2, 0)
49 /* Bit and mask definiation for outbox's SPRD_MBOX_IRQ_MSK register */
50 #define SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ BIT(0)
51 #define SPRD_OUTBOX_FIFO_IRQ_MASK GENMASK(4, 0)
53 #define SPRD_MBOX_CHAN_MAX 8
55 struct sprd_mbox_priv {
56 struct mbox_controller mbox;
58 void __iomem *inbox_base;
59 void __iomem *outbox_base;
61 u32 outbox_fifo_depth;
65 struct mbox_chan chan[SPRD_MBOX_CHAN_MAX];
68 static struct sprd_mbox_priv *to_sprd_mbox_priv(struct mbox_controller *mbox)
70 return container_of(mbox, struct sprd_mbox_priv, mbox);
73 static u32 sprd_mbox_get_fifo_len(struct sprd_mbox_priv *priv, u32 fifo_sts)
75 u32 wr_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_WR_SHIFT) &
76 SPRD_OUTBOX_FIFO_POS_MASK;
77 u32 rd_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_RD_SHIFT) &
78 SPRD_OUTBOX_FIFO_POS_MASK;
82 * If the read pointer is equal with write pointer, which means the fifo
85 if (wr_pos == rd_pos) {
86 if (fifo_sts & SPRD_OUTBOX_FIFO_FULL)
87 fifo_len = priv->outbox_fifo_depth;
90 } else if (wr_pos > rd_pos) {
91 fifo_len = wr_pos - rd_pos;
93 fifo_len = priv->outbox_fifo_depth - rd_pos + wr_pos;
99 static irqreturn_t sprd_mbox_outbox_isr(int irq, void *data)
101 struct sprd_mbox_priv *priv = data;
102 struct mbox_chan *chan;
103 u32 fifo_sts, fifo_len, msg[2];
106 fifo_sts = readl(priv->outbox_base + SPRD_MBOX_FIFO_STS);
108 fifo_len = sprd_mbox_get_fifo_len(priv, fifo_sts);
110 dev_warn_ratelimited(priv->dev, "spurious outbox interrupt\n");
114 for (i = 0; i < fifo_len; i++) {
115 msg[0] = readl(priv->outbox_base + SPRD_MBOX_MSG_LOW);
116 msg[1] = readl(priv->outbox_base + SPRD_MBOX_MSG_HIGH);
117 id = readl(priv->outbox_base + SPRD_MBOX_ID);
119 chan = &priv->chan[id];
121 mbox_chan_received_data(chan, (void *)msg);
123 dev_warn_ratelimited(priv->dev,
124 "message's been dropped at ch[%d]\n", id);
126 /* Trigger to update outbox FIFO pointer */
127 writel(0x1, priv->outbox_base + SPRD_MBOX_TRIGGER);
130 /* Clear irq status after reading all message. */
131 writel(SPRD_MBOX_IRQ_CLR, priv->outbox_base + SPRD_MBOX_IRQ_STS);
136 static irqreturn_t sprd_mbox_inbox_isr(int irq, void *data)
138 struct sprd_mbox_priv *priv = data;
139 struct mbox_chan *chan;
140 u32 fifo_sts, send_sts, busy, id;
142 fifo_sts = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS);
144 /* Get the inbox data delivery status */
145 send_sts = (fifo_sts & SPRD_INBOX_FIFO_DELIVER_MASK) >>
146 SPRD_INBOX_FIFO_DELIVER_SHIFT;
148 dev_warn_ratelimited(priv->dev, "spurious inbox interrupt\n");
153 id = __ffs(send_sts);
154 send_sts &= (send_sts - 1);
156 chan = &priv->chan[id];
159 * Check if the message was fetched by remote traget, if yes,
160 * that means the transmission has been completed.
162 busy = fifo_sts & SPRD_INBOX_FIFO_BUSY_MASK;
163 if (!(busy & BIT(id)))
164 mbox_chan_txdone(chan, 0);
167 /* Clear FIFO delivery and overflow status */
169 (SPRD_INBOX_FIFO_DELIVER_MASK | SPRD_INBOX_FIFO_OVERLOW_MASK),
170 priv->inbox_base + SPRD_MBOX_FIFO_RST);
172 /* Clear irq status */
173 writel(SPRD_MBOX_IRQ_CLR, priv->inbox_base + SPRD_MBOX_IRQ_STS);
178 static int sprd_mbox_send_data(struct mbox_chan *chan, void *msg)
180 struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
181 unsigned long id = (unsigned long)chan->con_priv;
184 /* Write data into inbox FIFO, and only support 8 bytes every time */
185 writel(data[0], priv->inbox_base + SPRD_MBOX_MSG_LOW);
186 writel(data[1], priv->inbox_base + SPRD_MBOX_MSG_HIGH);
188 /* Set target core id */
189 writel(id, priv->inbox_base + SPRD_MBOX_ID);
191 /* Trigger remote request */
192 writel(0x1, priv->inbox_base + SPRD_MBOX_TRIGGER);
197 static int sprd_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
199 struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
200 unsigned long id = (unsigned long)chan->con_priv;
203 timeout = jiffies + msecs_to_jiffies(timeout);
205 while (time_before(jiffies, timeout)) {
206 busy = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS) &
207 SPRD_INBOX_FIFO_BUSY_MASK;
208 if (!(busy & BIT(id))) {
209 mbox_chan_txdone(chan, 0);
219 static int sprd_mbox_startup(struct mbox_chan *chan)
221 struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
224 mutex_lock(&priv->lock);
225 if (priv->refcnt++ == 0) {
226 /* Select outbox FIFO mode and reset the outbox FIFO status */
227 writel(0x0, priv->outbox_base + SPRD_MBOX_FIFO_RST);
229 /* Enable inbox FIFO overflow and delivery interrupt */
230 val = readl(priv->inbox_base + SPRD_MBOX_IRQ_MSK);
231 val &= ~(SPRD_INBOX_FIFO_OVERFLOW_IRQ | SPRD_INBOX_FIFO_DELIVER_IRQ);
232 writel(val, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
234 /* Enable outbox FIFO not empty interrupt */
235 val = readl(priv->outbox_base + SPRD_MBOX_IRQ_MSK);
236 val &= ~SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ;
237 writel(val, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
239 mutex_unlock(&priv->lock);
244 static void sprd_mbox_shutdown(struct mbox_chan *chan)
246 struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
248 mutex_lock(&priv->lock);
249 if (--priv->refcnt == 0) {
250 /* Disable inbox & outbox interrupt */
251 writel(SPRD_INBOX_FIFO_IRQ_MASK, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
252 writel(SPRD_OUTBOX_FIFO_IRQ_MASK, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
254 mutex_unlock(&priv->lock);
257 static const struct mbox_chan_ops sprd_mbox_ops = {
258 .send_data = sprd_mbox_send_data,
259 .flush = sprd_mbox_flush,
260 .startup = sprd_mbox_startup,
261 .shutdown = sprd_mbox_shutdown,
264 static void sprd_mbox_disable(void *data)
266 struct sprd_mbox_priv *priv = data;
268 clk_disable_unprepare(priv->clk);
271 static int sprd_mbox_probe(struct platform_device *pdev)
273 struct device *dev = &pdev->dev;
274 struct sprd_mbox_priv *priv;
275 int ret, inbox_irq, outbox_irq;
278 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
283 mutex_init(&priv->lock);
286 * The Spreadtrum mailbox uses an inbox to send messages to the target
287 * core, and uses an outbox to receive messages from other cores.
289 * Thus the mailbox controller supplies 2 different register addresses
290 * and IRQ numbers for inbox and outbox.
292 priv->inbox_base = devm_platform_ioremap_resource(pdev, 0);
293 if (IS_ERR(priv->inbox_base))
294 return PTR_ERR(priv->inbox_base);
296 priv->outbox_base = devm_platform_ioremap_resource(pdev, 1);
297 if (IS_ERR(priv->outbox_base))
298 return PTR_ERR(priv->outbox_base);
300 priv->clk = devm_clk_get(dev, "enable");
301 if (IS_ERR(priv->clk)) {
302 dev_err(dev, "failed to get mailbox clock\n");
303 return PTR_ERR(priv->clk);
306 ret = clk_prepare_enable(priv->clk);
310 ret = devm_add_action_or_reset(dev, sprd_mbox_disable, priv);
312 dev_err(dev, "failed to add mailbox disable action\n");
316 inbox_irq = platform_get_irq(pdev, 0);
320 ret = devm_request_irq(dev, inbox_irq, sprd_mbox_inbox_isr,
321 IRQF_NO_SUSPEND, dev_name(dev), priv);
323 dev_err(dev, "failed to request inbox IRQ: %d\n", ret);
327 outbox_irq = platform_get_irq(pdev, 1);
331 ret = devm_request_irq(dev, outbox_irq, sprd_mbox_outbox_isr,
332 IRQF_NO_SUSPEND, dev_name(dev), priv);
334 dev_err(dev, "failed to request outbox IRQ: %d\n", ret);
338 /* Get the default outbox FIFO depth */
339 priv->outbox_fifo_depth =
340 readl(priv->outbox_base + SPRD_MBOX_FIFO_DEPTH) + 1;
341 priv->mbox.dev = dev;
342 priv->mbox.chans = &priv->chan[0];
343 priv->mbox.num_chans = SPRD_MBOX_CHAN_MAX;
344 priv->mbox.ops = &sprd_mbox_ops;
345 priv->mbox.txdone_irq = true;
347 for (id = 0; id < SPRD_MBOX_CHAN_MAX; id++)
348 priv->chan[id].con_priv = (void *)id;
350 ret = devm_mbox_controller_register(dev, &priv->mbox);
352 dev_err(dev, "failed to register mailbox: %d\n", ret);
359 static const struct of_device_id sprd_mbox_of_match[] = {
360 { .compatible = "sprd,sc9860-mailbox", },
363 MODULE_DEVICE_TABLE(of, sprd_mbox_of_match);
365 static struct platform_driver sprd_mbox_driver = {
367 .name = "sprd-mailbox",
368 .of_match_table = sprd_mbox_of_match,
370 .probe = sprd_mbox_probe,
372 module_platform_driver(sprd_mbox_driver);
374 MODULE_AUTHOR("Baolin Wang <baolin.wang@unisoc.com>");
375 MODULE_DESCRIPTION("Spreadtrum mailbox driver");
376 MODULE_LICENSE("GPL v2");