2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #ifndef _hrt_dummy_use_blob_sp
20 #define _hrt_dummy_use_blob_sp()
23 #define _hrt_cell_load_program_sp(proc) _hrt_cell_load_program_embedded(proc, sp)
26 /* function longjmp: 680D */
28 /* function longjmp: 6A0B */
32 /* function tmpmem_init_dmem: 6558 */
34 /* function tmpmem_init_dmem: 671E */
38 /* function ia_css_dmaproxy_sp_set_addr_B: 3C50 */
40 /* function ia_css_dmaproxy_sp_set_addr_B: 3DC5 */
42 /* function ia_css_pipe_data_init_tagger_resources: AC7 */
45 /* function debug_buffer_set_ddr_addr: DD */
47 #ifndef HIVE_MULTIPLE_PROGRAMS
48 #ifndef HIVE_MEM_vbuf_mipi
49 #define HIVE_MEM_vbuf_mipi scalar_processor_2400_dmem
51 #define HIVE_ADDR_vbuf_mipi 0x7398
53 #define HIVE_ADDR_vbuf_mipi 0x7444
55 #define HIVE_SIZE_vbuf_mipi 12
59 #define HIVE_MEM_sp_vbuf_mipi scalar_processor_2400_dmem
61 #define HIVE_ADDR_sp_vbuf_mipi 0x7398
63 #define HIVE_ADDR_sp_vbuf_mipi 0x7444
65 #define HIVE_SIZE_sp_vbuf_mipi 12
68 /* function ia_css_event_sp_decode: 3E41 */
70 /* function ia_css_event_sp_decode: 3FB6 */
74 /* function ia_css_queue_get_size: 51BF */
76 /* function ia_css_queue_get_size: 53C8 */
80 /* function ia_css_queue_load: 5800 */
82 /* function ia_css_queue_load: 59DF */
86 /* function setjmp: 6816 */
88 /* function setjmp: 6A14 */
92 /* function ia_css_pipeline_sp_sfi_get_current_frame: 27BF */
94 /* function ia_css_pipeline_sp_sfi_get_current_frame: 2790 */
97 #ifndef HIVE_MULTIPLE_PROGRAMS
98 #ifndef HIVE_MEM_sem_for_sp2host_isys_event_queue
99 #define HIVE_MEM_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem
101 #define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x5760
103 #define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x57FC
105 #define HIVE_SIZE_sem_for_sp2host_isys_event_queue 20
109 #define HIVE_MEM_sp_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem
111 #define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x5760
113 #define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x57FC
115 #define HIVE_SIZE_sp_sem_for_sp2host_isys_event_queue 20
118 /* function ia_css_dmaproxy_sp_wait_for_ack: 6DA9 */
120 /* function ia_css_dmaproxy_sp_wait_for_ack: 6FF7 */
124 /* function ia_css_sp_rawcopy_func: 596B */
126 /* function ia_css_sp_rawcopy_func: 5B4A */
130 /* function ia_css_tagger_buf_sp_pop_marked: 3339 */
132 /* function ia_css_tagger_buf_sp_pop_marked: 345C */
135 #ifndef HIVE_MULTIPLE_PROGRAMS
136 #ifndef HIVE_MEM_N_CSI_RX_BE_SID_WIDTH
137 #define HIVE_MEM_N_CSI_RX_BE_SID_WIDTH scalar_processor_2400_dmem
138 #define HIVE_ADDR_N_CSI_RX_BE_SID_WIDTH 0x1D0
139 #define HIVE_SIZE_N_CSI_RX_BE_SID_WIDTH 12
143 #define HIVE_MEM_sp_N_CSI_RX_BE_SID_WIDTH scalar_processor_2400_dmem
144 #define HIVE_ADDR_sp_N_CSI_RX_BE_SID_WIDTH 0x1D0
145 #define HIVE_SIZE_sp_N_CSI_RX_BE_SID_WIDTH 12
147 #ifndef HIVE_MULTIPLE_PROGRAMS
148 #ifndef HIVE_MEM_isp_stage
149 #define HIVE_MEM_isp_stage scalar_processor_2400_dmem
151 #define HIVE_ADDR_isp_stage 0x6C98
153 #define HIVE_ADDR_isp_stage 0x6D48
155 #define HIVE_SIZE_isp_stage 832
159 #define HIVE_MEM_sp_isp_stage scalar_processor_2400_dmem
161 #define HIVE_ADDR_sp_isp_stage 0x6C98
163 #define HIVE_ADDR_sp_isp_stage 0x6D48
165 #define HIVE_SIZE_sp_isp_stage 832
167 #ifndef HIVE_MULTIPLE_PROGRAMS
168 #ifndef HIVE_MEM_vbuf_raw
169 #define HIVE_MEM_vbuf_raw scalar_processor_2400_dmem
171 #define HIVE_ADDR_vbuf_raw 0x37C
173 #define HIVE_ADDR_vbuf_raw 0x394
175 #define HIVE_SIZE_vbuf_raw 4
179 #define HIVE_MEM_sp_vbuf_raw scalar_processor_2400_dmem
181 #define HIVE_ADDR_sp_vbuf_raw 0x37C
183 #define HIVE_ADDR_sp_vbuf_raw 0x394
185 #define HIVE_SIZE_sp_vbuf_raw 4
188 /* function ia_css_sp_bin_copy_func: 594C */
190 /* function ia_css_sp_bin_copy_func: 5B2B */
194 /* function ia_css_queue_item_store: 554E */
196 /* function ia_css_queue_item_store: 572D */
200 /* function input_system_reset: 1286 */
202 /* function input_system_reset: 1201 */
205 #ifndef HIVE_MULTIPLE_PROGRAMS
206 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs
207 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem
209 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5B38
211 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5BE4
213 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_metadata_bufs 20
217 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem
219 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5B38
221 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5BE4
223 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 20
225 #ifndef HIVE_MULTIPLE_PROGRAMS
226 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs
227 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem
229 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5B4C
231 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5BF8
233 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_buffer_bufs 160
237 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem
239 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5B4C
241 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5BF8
243 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 160
245 /* function sp_start_isp: 39C */
247 #ifndef HIVE_MULTIPLE_PROGRAMS
248 #ifndef HIVE_MEM_sp_binary_group
249 #define HIVE_MEM_sp_binary_group scalar_processor_2400_dmem
251 #define HIVE_ADDR_sp_binary_group 0x7088
253 #define HIVE_ADDR_sp_binary_group 0x7138
255 #define HIVE_SIZE_sp_binary_group 32
259 #define HIVE_MEM_sp_sp_binary_group scalar_processor_2400_dmem
261 #define HIVE_ADDR_sp_sp_binary_group 0x7088
263 #define HIVE_ADDR_sp_sp_binary_group 0x7138
265 #define HIVE_SIZE_sp_sp_binary_group 32
267 #ifndef HIVE_MULTIPLE_PROGRAMS
268 #ifndef HIVE_MEM_sp_sw_state
269 #define HIVE_MEM_sp_sw_state scalar_processor_2400_dmem
271 #define HIVE_ADDR_sp_sw_state 0x7344
273 #define HIVE_ADDR_sp_sw_state 0x73F0
275 #define HIVE_SIZE_sp_sw_state 4
279 #define HIVE_MEM_sp_sp_sw_state scalar_processor_2400_dmem
281 #define HIVE_ADDR_sp_sp_sw_state 0x7344
283 #define HIVE_ADDR_sp_sp_sw_state 0x73F0
285 #define HIVE_SIZE_sp_sp_sw_state 4
288 /* function ia_css_thread_sp_main: 13F7 */
290 /* function ia_css_thread_sp_main: 136D */
294 /* function ia_css_ispctrl_sp_init_internal_buffers: 4047 */
296 /* function ia_css_ispctrl_sp_init_internal_buffers: 41F7 */
299 #ifndef HIVE_MULTIPLE_PROGRAMS
300 #ifndef HIVE_MEM_sp2host_psys_event_queue_handle
301 #define HIVE_MEM_sp2host_psys_event_queue_handle scalar_processor_2400_dmem
303 #define HIVE_ADDR_sp2host_psys_event_queue_handle 0x5BEC
305 #define HIVE_ADDR_sp2host_psys_event_queue_handle 0x5C98
307 #define HIVE_SIZE_sp2host_psys_event_queue_handle 12
311 #define HIVE_MEM_sp_sp2host_psys_event_queue_handle scalar_processor_2400_dmem
313 #define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x5BEC
315 #define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x5C98
317 #define HIVE_SIZE_sp_sp2host_psys_event_queue_handle 12
320 /* function pixelgen_unit_test: E68 */
322 /* function pixelgen_unit_test: E62 */
325 #ifndef HIVE_MULTIPLE_PROGRAMS
326 #ifndef HIVE_MEM_sem_for_sp2host_psys_event_queue
327 #define HIVE_MEM_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem
329 #define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x5774
331 #define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x5810
333 #define HIVE_SIZE_sem_for_sp2host_psys_event_queue 20
337 #define HIVE_MEM_sp_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem
339 #define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x5774
341 #define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x5810
343 #define HIVE_SIZE_sp_sem_for_sp2host_psys_event_queue 20
346 /* function ia_css_tagger_sp_propagate_frame: 2D52 */
348 #ifndef HIVE_MULTIPLE_PROGRAMS
349 #ifndef HIVE_MEM_sp_stop_copy_preview
350 #define HIVE_MEM_sp_stop_copy_preview scalar_processor_2400_dmem
351 #define HIVE_ADDR_sp_stop_copy_preview 0x7328
352 #define HIVE_SIZE_sp_stop_copy_preview 4
356 #define HIVE_MEM_sp_sp_stop_copy_preview scalar_processor_2400_dmem
357 #define HIVE_ADDR_sp_sp_stop_copy_preview 0x7328
358 #define HIVE_SIZE_sp_sp_stop_copy_preview 4
360 /* function ia_css_tagger_sp_propagate_frame: 2D23 */
363 #ifndef HIVE_MULTIPLE_PROGRAMS
364 #ifndef HIVE_MEM_vbuf_handles
365 #define HIVE_MEM_vbuf_handles scalar_processor_2400_dmem
367 #define HIVE_ADDR_vbuf_handles 0x73A4
369 #define HIVE_ADDR_vbuf_handles 0x7450
371 #define HIVE_SIZE_vbuf_handles 960
375 #define HIVE_MEM_sp_vbuf_handles scalar_processor_2400_dmem
377 #define HIVE_ADDR_sp_vbuf_handles 0x73A4
379 #define HIVE_ADDR_sp_vbuf_handles 0x7450
381 #define HIVE_SIZE_sp_vbuf_handles 960
384 /* function ia_css_queue_store: 56B4 */
386 /* function ia_css_sp_flash_register: 356E */
388 /* function ia_css_queue_store: 5893 */
392 /* function ia_css_sp_rawcopy_dummy_function: 5CF7 */
394 /* function ia_css_sp_flash_register: 3691 */
398 /* function ia_css_pipeline_sp_init: 201C */
400 /* function ia_css_pipeline_sp_init: 1FD7 */
404 /* function ia_css_tagger_sp_configure: 2C42 */
406 /* function ia_css_tagger_sp_configure: 2C13 */
410 /* function ia_css_ispctrl_sp_end_binary: 3E8A */
412 /* function ia_css_ispctrl_sp_end_binary: 3FFF */
415 #ifndef HIVE_MULTIPLE_PROGRAMS
416 #ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs
417 #define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem
419 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5BF8
421 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5CA4
423 #define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20
427 #define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem
429 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5BF8
431 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5CA4
433 #define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20
436 /* function pixelgen_tpg_run: F1E */
438 /* function pixelgen_tpg_run: F18 */
441 #ifndef HIVE_MULTIPLE_PROGRAMS
442 #ifndef HIVE_MEM_event_is_pending_mask
443 #define HIVE_MEM_event_is_pending_mask scalar_processor_2400_dmem
444 #define HIVE_ADDR_event_is_pending_mask 0x5C
445 #define HIVE_SIZE_event_is_pending_mask 44
449 #define HIVE_MEM_sp_event_is_pending_mask scalar_processor_2400_dmem
450 #define HIVE_ADDR_sp_event_is_pending_mask 0x5C
451 #define HIVE_SIZE_sp_event_is_pending_mask 44
453 #ifndef HIVE_MULTIPLE_PROGRAMS
454 #ifndef HIVE_MEM_sp_all_cb_elems_frame
455 #define HIVE_MEM_sp_all_cb_elems_frame scalar_processor_2400_dmem
457 #define HIVE_ADDR_sp_all_cb_elems_frame 0x5788
459 #define HIVE_ADDR_sp_all_cb_elems_frame 0x5824
461 #define HIVE_SIZE_sp_all_cb_elems_frame 16
465 #define HIVE_MEM_sp_sp_all_cb_elems_frame scalar_processor_2400_dmem
467 #define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x5788
469 #define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x5824
471 #define HIVE_SIZE_sp_sp_all_cb_elems_frame 16
473 #ifndef HIVE_MULTIPLE_PROGRAMS
474 #ifndef HIVE_MEM_sp2host_isys_event_queue_handle
475 #define HIVE_MEM_sp2host_isys_event_queue_handle scalar_processor_2400_dmem
477 #define HIVE_ADDR_sp2host_isys_event_queue_handle 0x5C0C
479 #define HIVE_ADDR_sp2host_isys_event_queue_handle 0x5CB8
481 #define HIVE_SIZE_sp2host_isys_event_queue_handle 12
485 #define HIVE_MEM_sp_sp2host_isys_event_queue_handle scalar_processor_2400_dmem
487 #define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x5C0C
489 #define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x5CB8
491 #define HIVE_SIZE_sp_sp2host_isys_event_queue_handle 12
493 #ifndef HIVE_MULTIPLE_PROGRAMS
494 #ifndef HIVE_MEM_host_sp_com
495 #define HIVE_MEM_host_sp_com scalar_processor_2400_dmem
497 #define HIVE_ADDR_host_sp_com 0x3E48
499 #define HIVE_ADDR_host_sp_com 0x3E6C
501 #define HIVE_SIZE_host_sp_com 220
505 #define HIVE_MEM_sp_host_sp_com scalar_processor_2400_dmem
507 #define HIVE_ADDR_sp_host_sp_com 0x3E48
509 #define HIVE_ADDR_sp_host_sp_com 0x3E6C
511 #define HIVE_SIZE_sp_host_sp_com 220
514 /* function ia_css_queue_get_free_space: 5313 */
516 /* function ia_css_queue_get_free_space: 54F2 */
520 /* function exec_image_pipe: 5E6 */
522 /* function exec_image_pipe: 57A */
525 #ifndef HIVE_MULTIPLE_PROGRAMS
526 #ifndef HIVE_MEM_sp_init_dmem_data
527 #define HIVE_MEM_sp_init_dmem_data scalar_processor_2400_dmem
529 #define HIVE_ADDR_sp_init_dmem_data 0x7348
531 #define HIVE_ADDR_sp_init_dmem_data 0x73F4
533 #define HIVE_SIZE_sp_init_dmem_data 24
537 #define HIVE_MEM_sp_sp_init_dmem_data scalar_processor_2400_dmem
539 #define HIVE_ADDR_sp_sp_init_dmem_data 0x7348
541 #define HIVE_ADDR_sp_sp_init_dmem_data 0x73F4
543 #define HIVE_SIZE_sp_sp_init_dmem_data 24
546 /* function ia_css_sp_metadata_start: 5DD1 */
548 /* function ia_css_sp_metadata_start: 5EB3 */
552 /* function ia_css_bufq_sp_init_buffer_queues: 35BF */
554 /* function ia_css_bufq_sp_init_buffer_queues: 36E2 */
558 /* function ia_css_pipeline_sp_stop: 1FFF */
560 /* function ia_css_pipeline_sp_stop: 1FBA */
564 /* function ia_css_tagger_sp_connect_pipes: 312C */
566 /* function ia_css_tagger_sp_connect_pipes: 30FD */
570 /* function sp_isys_copy_wait: 644 */
572 /* function sp_isys_copy_wait: 5D8 */
575 /* function is_isp_debug_buffer_full: 337 */
578 /* function ia_css_dmaproxy_sp_configure_channel_from_info: 3BD3 */
580 /* function ia_css_dmaproxy_sp_configure_channel_from_info: 3D35 */
584 /* function encode_and_post_timer_event: AA8 */
586 /* function encode_and_post_timer_event: A3C */
589 #ifndef HIVE_MULTIPLE_PROGRAMS
590 #ifndef HIVE_MEM_input_system_bz2788_active
591 #define HIVE_MEM_input_system_bz2788_active scalar_processor_2400_dmem
593 #define HIVE_ADDR_input_system_bz2788_active 0x250C
595 #define HIVE_ADDR_input_system_bz2788_active 0x2524
597 #define HIVE_SIZE_input_system_bz2788_active 4
601 #define HIVE_MEM_sp_input_system_bz2788_active scalar_processor_2400_dmem
603 #define HIVE_ADDR_sp_input_system_bz2788_active 0x250C
605 #define HIVE_ADDR_sp_input_system_bz2788_active 0x2524
607 #define HIVE_SIZE_sp_input_system_bz2788_active 4
609 #ifndef HIVE_MULTIPLE_PROGRAMS
610 #ifndef HIVE_MEM_N_IBUF_CTRL_PROCS
611 #define HIVE_MEM_N_IBUF_CTRL_PROCS scalar_processor_2400_dmem
612 #define HIVE_ADDR_N_IBUF_CTRL_PROCS 0x1FC
613 #define HIVE_SIZE_N_IBUF_CTRL_PROCS 12
617 #define HIVE_MEM_sp_N_IBUF_CTRL_PROCS scalar_processor_2400_dmem
618 #define HIVE_ADDR_sp_N_IBUF_CTRL_PROCS 0x1FC
619 #define HIVE_SIZE_sp_N_IBUF_CTRL_PROCS 12
621 #ifndef HIVE_MULTIPLE_PROGRAMS
622 #ifndef HIVE_MEM_sp_per_frame_data
623 #define HIVE_MEM_sp_per_frame_data scalar_processor_2400_dmem
625 #define HIVE_ADDR_sp_per_frame_data 0x3F24
627 #define HIVE_ADDR_sp_per_frame_data 0x3F48
629 #define HIVE_SIZE_sp_per_frame_data 4
633 #define HIVE_MEM_sp_sp_per_frame_data scalar_processor_2400_dmem
635 #define HIVE_ADDR_sp_sp_per_frame_data 0x3F24
637 #define HIVE_ADDR_sp_sp_per_frame_data 0x3F48
639 #define HIVE_SIZE_sp_sp_per_frame_data 4
642 /* function ia_css_rmgr_sp_vbuf_dequeue: 62AC */
644 /* function ia_css_rmgr_sp_vbuf_dequeue: 6472 */
647 #ifndef HIVE_MULTIPLE_PROGRAMS
648 #ifndef HIVE_MEM_host2sp_psys_event_queue_handle
649 #define HIVE_MEM_host2sp_psys_event_queue_handle scalar_processor_2400_dmem
651 #define HIVE_ADDR_host2sp_psys_event_queue_handle 0x5C18
653 #define HIVE_ADDR_host2sp_psys_event_queue_handle 0x5CC4
655 #define HIVE_SIZE_host2sp_psys_event_queue_handle 12
659 #define HIVE_MEM_sp_host2sp_psys_event_queue_handle scalar_processor_2400_dmem
661 #define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x5C18
663 #define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x5CC4
665 #define HIVE_SIZE_sp_host2sp_psys_event_queue_handle 12
667 #ifndef HIVE_MULTIPLE_PROGRAMS
668 #ifndef HIVE_MEM_xmem_bin_addr
669 #define HIVE_MEM_xmem_bin_addr scalar_processor_2400_dmem
671 #define HIVE_ADDR_xmem_bin_addr 0x3F28
673 #define HIVE_ADDR_xmem_bin_addr 0x3F4C
675 #define HIVE_SIZE_xmem_bin_addr 4
679 #define HIVE_MEM_sp_xmem_bin_addr scalar_processor_2400_dmem
681 #define HIVE_ADDR_sp_xmem_bin_addr 0x3F28
683 #define HIVE_ADDR_sp_xmem_bin_addr 0x3F4C
685 #define HIVE_SIZE_sp_xmem_bin_addr 4
688 /* function tmr_clock_init: 16F9 */
690 /* function tmr_clock_init: 166F */
694 /* function ia_css_pipeline_sp_run: 1ABF */
696 /* function ia_css_pipeline_sp_run: 1A61 */
700 /* function memcpy: 68B6 */
702 /* function memcpy: 6AB4 */
705 #ifndef HIVE_MULTIPLE_PROGRAMS
706 #ifndef HIVE_MEM_N_ISYS2401_DMA_CHANNEL_PROCS
707 #define HIVE_MEM_N_ISYS2401_DMA_CHANNEL_PROCS scalar_processor_2400_dmem
708 #define HIVE_ADDR_N_ISYS2401_DMA_CHANNEL_PROCS 0x214
709 #define HIVE_SIZE_N_ISYS2401_DMA_CHANNEL_PROCS 4
713 #define HIVE_MEM_sp_N_ISYS2401_DMA_CHANNEL_PROCS scalar_processor_2400_dmem
714 #define HIVE_ADDR_sp_N_ISYS2401_DMA_CHANNEL_PROCS 0x214
715 #define HIVE_SIZE_sp_N_ISYS2401_DMA_CHANNEL_PROCS 4
717 #ifndef HIVE_MULTIPLE_PROGRAMS
718 #ifndef HIVE_MEM_GP_DEVICE_BASE
719 #define HIVE_MEM_GP_DEVICE_BASE scalar_processor_2400_dmem
721 #define HIVE_ADDR_GP_DEVICE_BASE 0x384
723 #define HIVE_ADDR_GP_DEVICE_BASE 0x39C
725 #define HIVE_SIZE_GP_DEVICE_BASE 4
729 #define HIVE_MEM_sp_GP_DEVICE_BASE scalar_processor_2400_dmem
731 #define HIVE_ADDR_sp_GP_DEVICE_BASE 0x384
733 #define HIVE_ADDR_sp_GP_DEVICE_BASE 0x39C
735 #define HIVE_SIZE_sp_GP_DEVICE_BASE 4
737 #ifndef HIVE_MULTIPLE_PROGRAMS
738 #ifndef HIVE_MEM_ia_css_thread_sp_ready_queue
739 #define HIVE_MEM_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem
741 #define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x278
743 #define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x27C
745 #define HIVE_SIZE_ia_css_thread_sp_ready_queue 12
749 #define HIVE_MEM_sp_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem
751 #define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x278
753 #define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x27C
755 #define HIVE_SIZE_sp_ia_css_thread_sp_ready_queue 12
758 /* function stream2mmio_send_command: E0A */
760 /* function stream2mmio_send_command: E04 */
764 /* function ia_css_uds_sp_scale_params: 65BF */
766 /* function ia_css_uds_sp_scale_params: 67BD */
770 /* function ia_css_circbuf_increase_size: 14DC */
772 /* function ia_css_circbuf_increase_size: 1452 */
776 /* function __divu: 6834 */
778 /* function __divu: 6A32 */
782 /* function ia_css_thread_sp_get_state: 131F */
784 /* function ia_css_thread_sp_get_state: 1295 */
787 #ifndef HIVE_MULTIPLE_PROGRAMS
788 #ifndef HIVE_MEM_sem_for_cont_capt_stop
789 #define HIVE_MEM_sem_for_cont_capt_stop scalar_processor_2400_dmem
791 #define HIVE_ADDR_sem_for_cont_capt_stop 0x5798
793 #define HIVE_ADDR_sem_for_cont_capt_stop 0x5834
795 #define HIVE_SIZE_sem_for_cont_capt_stop 20
799 #define HIVE_MEM_sp_sem_for_cont_capt_stop scalar_processor_2400_dmem
801 #define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x5798
803 #define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x5834
805 #define HIVE_SIZE_sp_sem_for_cont_capt_stop 20
807 #ifndef HIVE_MULTIPLE_PROGRAMS
808 #ifndef HIVE_MEM_N_SHORT_PACKET_LUT_ENTRIES
809 #define HIVE_MEM_N_SHORT_PACKET_LUT_ENTRIES scalar_processor_2400_dmem
810 #define HIVE_ADDR_N_SHORT_PACKET_LUT_ENTRIES 0x1AC
811 #define HIVE_SIZE_N_SHORT_PACKET_LUT_ENTRIES 12
815 #define HIVE_MEM_sp_N_SHORT_PACKET_LUT_ENTRIES scalar_processor_2400_dmem
816 #define HIVE_ADDR_sp_N_SHORT_PACKET_LUT_ENTRIES 0x1AC
817 #define HIVE_SIZE_sp_N_SHORT_PACKET_LUT_ENTRIES 12
820 /* function thread_fiber_sp_main: 14D5 */
822 /* function thread_fiber_sp_main: 144B */
825 #ifndef HIVE_MULTIPLE_PROGRAMS
826 #ifndef HIVE_MEM_sp_isp_pipe_thread
827 #define HIVE_MEM_sp_isp_pipe_thread scalar_processor_2400_dmem
829 #define HIVE_ADDR_sp_isp_pipe_thread 0x58DC
830 #define HIVE_SIZE_sp_isp_pipe_thread 340
832 #define HIVE_ADDR_sp_isp_pipe_thread 0x5978
833 #define HIVE_SIZE_sp_isp_pipe_thread 360
838 #define HIVE_MEM_sp_sp_isp_pipe_thread scalar_processor_2400_dmem
840 #define HIVE_ADDR_sp_sp_isp_pipe_thread 0x58DC
841 #define HIVE_SIZE_sp_sp_isp_pipe_thread 340
843 #define HIVE_ADDR_sp_sp_isp_pipe_thread 0x5978
844 #define HIVE_SIZE_sp_sp_isp_pipe_thread 360
848 /* function ia_css_parambuf_sp_handle_parameter_sets: 193F */
850 /* function ia_css_parambuf_sp_handle_parameter_sets: 18B5 */
854 /* function ia_css_spctrl_sp_set_state: 5DED */
856 /* function ia_css_spctrl_sp_set_state: 5ECF */
860 /* function ia_css_thread_sem_sp_signal: 6A99 */
862 /* function ia_css_thread_sem_sp_signal: 6D18 */
865 #ifndef HIVE_MULTIPLE_PROGRAMS
866 #ifndef HIVE_MEM_IRQ_BASE
867 #define HIVE_MEM_IRQ_BASE scalar_processor_2400_dmem
868 #define HIVE_ADDR_IRQ_BASE 0x2C
869 #define HIVE_SIZE_IRQ_BASE 16
873 #define HIVE_MEM_sp_IRQ_BASE scalar_processor_2400_dmem
874 #define HIVE_ADDR_sp_IRQ_BASE 0x2C
875 #define HIVE_SIZE_sp_IRQ_BASE 16
878 /* function ia_css_virtual_isys_sp_isr_init: 5E8C */
880 /* function ia_css_virtual_isys_sp_isr_init: 5F70 */
883 #ifndef HIVE_MULTIPLE_PROGRAMS
884 #ifndef HIVE_MEM_TIMED_CTRL_BASE
885 #define HIVE_MEM_TIMED_CTRL_BASE scalar_processor_2400_dmem
886 #define HIVE_ADDR_TIMED_CTRL_BASE 0x40
887 #define HIVE_SIZE_TIMED_CTRL_BASE 4
891 #define HIVE_MEM_sp_TIMED_CTRL_BASE scalar_processor_2400_dmem
892 #define HIVE_ADDR_sp_TIMED_CTRL_BASE 0x40
893 #define HIVE_SIZE_sp_TIMED_CTRL_BASE 4
896 /* function ia_css_isys_sp_generate_exp_id: 613C */
898 /* function ia_css_rmgr_sp_init: 61A7 */
900 /* function ia_css_isys_sp_generate_exp_id: 6302 */
904 /* function ia_css_thread_sem_sp_init: 6B6A */
906 /* function ia_css_rmgr_sp_init: 636D */
910 #ifndef HIVE_MULTIPLE_PROGRAMS
911 #ifndef HIVE_MEM_is_isp_requested
912 #define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem
913 #define HIVE_ADDR_is_isp_requested 0x390
914 #define HIVE_SIZE_is_isp_requested 4
918 #define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem
919 #define HIVE_ADDR_sp_is_isp_requested 0x390
920 #define HIVE_SIZE_sp_is_isp_requested 4
922 /* function ia_css_thread_sem_sp_init: 6DE7 */
925 #ifndef HIVE_MULTIPLE_PROGRAMS
926 #ifndef HIVE_MEM_sem_for_reading_cb_frame
927 #define HIVE_MEM_sem_for_reading_cb_frame scalar_processor_2400_dmem
929 #define HIVE_ADDR_sem_for_reading_cb_frame 0x57AC
931 #define HIVE_ADDR_sem_for_reading_cb_frame 0x5848
933 #define HIVE_SIZE_sem_for_reading_cb_frame 40
937 #define HIVE_MEM_sp_sem_for_reading_cb_frame scalar_processor_2400_dmem
939 #define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x57AC
941 #define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x5848
943 #define HIVE_SIZE_sp_sem_for_reading_cb_frame 40
946 /* function ia_css_dmaproxy_sp_execute: 3B3B */
948 #ifndef HIVE_MULTIPLE_PROGRAMS
949 #ifndef HIVE_MEM_is_isp_requested
950 #define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem
951 #define HIVE_ADDR_is_isp_requested 0x3A8
952 #define HIVE_SIZE_is_isp_requested 4
956 #define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem
957 #define HIVE_ADDR_sp_is_isp_requested 0x3A8
958 #define HIVE_SIZE_sp_is_isp_requested 4
960 /* function ia_css_dmaproxy_sp_execute: 3C9B */
964 /* function csi_rx_backend_rst: CE6 */
966 /* function csi_rx_backend_rst: CE0 */
970 /* function ia_css_queue_is_empty: 51FA */
972 /* function ia_css_queue_is_empty: 7144 */
976 /* function ia_css_pipeline_sp_has_stopped: 1FF5 */
978 /* function ia_css_pipeline_sp_has_stopped: 1FB0 */
982 /* function ia_css_circbuf_extract: 15E0 */
984 /* function ia_css_circbuf_extract: 1556 */
988 /* function ia_css_tagger_buf_sp_is_locked_from_start: 344F */
990 /* function ia_css_tagger_buf_sp_is_locked_from_start: 3572 */
993 #ifndef HIVE_MULTIPLE_PROGRAMS
994 #ifndef HIVE_MEM_current_sp_thread
995 #define HIVE_MEM_current_sp_thread scalar_processor_2400_dmem
996 #define HIVE_ADDR_current_sp_thread 0x274
997 #define HIVE_SIZE_current_sp_thread 4
1001 #define HIVE_MEM_sp_current_sp_thread scalar_processor_2400_dmem
1002 #define HIVE_ADDR_sp_current_sp_thread 0x274
1003 #define HIVE_SIZE_sp_current_sp_thread 4
1006 /* function ia_css_spctrl_sp_get_spid: 5DF4 */
1008 /* function ia_css_spctrl_sp_get_spid: 5ED6 */
1012 /* function ia_css_bufq_sp_reset_buffers: 3646 */
1014 /* function ia_css_bufq_sp_reset_buffers: 3769 */
1018 /* function ia_css_dmaproxy_sp_read_byte_addr: 6DD7 */
1020 /* function ia_css_dmaproxy_sp_read_byte_addr: 7025 */
1024 /* function ia_css_rmgr_sp_uninit: 61A0 */
1026 /* function ia_css_rmgr_sp_uninit: 6366 */
1029 #ifndef HIVE_MULTIPLE_PROGRAMS
1030 #ifndef HIVE_MEM_sp_threads_stack
1031 #define HIVE_MEM_sp_threads_stack scalar_processor_2400_dmem
1032 #define HIVE_ADDR_sp_threads_stack 0x164
1033 #define HIVE_SIZE_sp_threads_stack 24
1037 #define HIVE_MEM_sp_sp_threads_stack scalar_processor_2400_dmem
1038 #define HIVE_ADDR_sp_sp_threads_stack 0x164
1039 #define HIVE_SIZE_sp_sp_threads_stack 24
1041 #ifndef HIVE_MULTIPLE_PROGRAMS
1042 #ifndef HIVE_MEM_N_STREAM2MMIO_SID_PROCS
1043 #define HIVE_MEM_N_STREAM2MMIO_SID_PROCS scalar_processor_2400_dmem
1044 #define HIVE_ADDR_N_STREAM2MMIO_SID_PROCS 0x218
1045 #define HIVE_SIZE_N_STREAM2MMIO_SID_PROCS 12
1049 #define HIVE_MEM_sp_N_STREAM2MMIO_SID_PROCS scalar_processor_2400_dmem
1050 #define HIVE_ADDR_sp_N_STREAM2MMIO_SID_PROCS 0x218
1051 #define HIVE_SIZE_sp_N_STREAM2MMIO_SID_PROCS 12
1054 /* function ia_css_circbuf_peek: 15C2 */
1056 /* function ia_css_circbuf_peek: 1538 */
1060 /* function ia_css_parambuf_sp_wait_for_in_param: 1708 */
1062 /* function ia_css_parambuf_sp_wait_for_in_param: 167E */
1065 #ifndef HIVE_MULTIPLE_PROGRAMS
1066 #ifndef HIVE_MEM_sp_all_cb_elems_param
1067 #define HIVE_MEM_sp_all_cb_elems_param scalar_processor_2400_dmem
1069 #define HIVE_ADDR_sp_all_cb_elems_param 0x57D4
1071 #define HIVE_ADDR_sp_all_cb_elems_param 0x5870
1073 #define HIVE_SIZE_sp_all_cb_elems_param 16
1077 #define HIVE_MEM_sp_sp_all_cb_elems_param scalar_processor_2400_dmem
1079 #define HIVE_ADDR_sp_sp_all_cb_elems_param 0x57D4
1081 #define HIVE_ADDR_sp_sp_all_cb_elems_param 0x5870
1083 #define HIVE_SIZE_sp_sp_all_cb_elems_param 16
1085 #ifndef HIVE_MULTIPLE_PROGRAMS
1086 #ifndef HIVE_MEM_pipeline_sp_curr_binary_id
1087 #define HIVE_MEM_pipeline_sp_curr_binary_id scalar_processor_2400_dmem
1089 #define HIVE_ADDR_pipeline_sp_curr_binary_id 0x284
1091 #define HIVE_ADDR_pipeline_sp_curr_binary_id 0x288
1093 #define HIVE_SIZE_pipeline_sp_curr_binary_id 4
1097 #define HIVE_MEM_sp_pipeline_sp_curr_binary_id scalar_processor_2400_dmem
1099 #define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x284
1101 #define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x288
1103 #define HIVE_SIZE_sp_pipeline_sp_curr_binary_id 4
1105 #ifndef HIVE_MULTIPLE_PROGRAMS
1106 #ifndef HIVE_MEM_sp_all_cbs_frame_desc
1107 #define HIVE_MEM_sp_all_cbs_frame_desc scalar_processor_2400_dmem
1109 #define HIVE_ADDR_sp_all_cbs_frame_desc 0x57E4
1111 #define HIVE_ADDR_sp_all_cbs_frame_desc 0x5880
1113 #define HIVE_SIZE_sp_all_cbs_frame_desc 8
1117 #define HIVE_MEM_sp_sp_all_cbs_frame_desc scalar_processor_2400_dmem
1119 #define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x57E4
1121 #define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x5880
1123 #define HIVE_SIZE_sp_sp_all_cbs_frame_desc 8
1126 /* function sp_isys_copy_func_v2: 629 */
1128 /* function sp_isys_copy_func_v2: 5BD */
1131 #ifndef HIVE_MULTIPLE_PROGRAMS
1132 #ifndef HIVE_MEM_sem_for_reading_cb_param
1133 #define HIVE_MEM_sem_for_reading_cb_param scalar_processor_2400_dmem
1135 #define HIVE_ADDR_sem_for_reading_cb_param 0x57EC
1137 #define HIVE_ADDR_sem_for_reading_cb_param 0x5888
1139 #define HIVE_SIZE_sem_for_reading_cb_param 40
1143 #define HIVE_MEM_sp_sem_for_reading_cb_param scalar_processor_2400_dmem
1145 #define HIVE_ADDR_sp_sem_for_reading_cb_param 0x57EC
1147 #define HIVE_ADDR_sp_sem_for_reading_cb_param 0x5888
1149 #define HIVE_SIZE_sp_sem_for_reading_cb_param 40
1152 /* function ia_css_queue_get_used_space: 52C7 */
1154 /* function ia_css_queue_get_used_space: 54A6 */
1157 #ifndef HIVE_MULTIPLE_PROGRAMS
1158 #ifndef HIVE_MEM_sem_for_cont_capt_start
1159 #define HIVE_MEM_sem_for_cont_capt_start scalar_processor_2400_dmem
1161 #define HIVE_ADDR_sem_for_cont_capt_start 0x5814
1163 #define HIVE_ADDR_sem_for_cont_capt_start 0x58B0
1165 #define HIVE_SIZE_sem_for_cont_capt_start 20
1169 #define HIVE_MEM_sp_sem_for_cont_capt_start scalar_processor_2400_dmem
1171 #define HIVE_ADDR_sp_sem_for_cont_capt_start 0x5814
1173 #define HIVE_ADDR_sp_sem_for_cont_capt_start 0x58B0
1175 #define HIVE_SIZE_sp_sem_for_cont_capt_start 20
1177 #ifndef HIVE_MULTIPLE_PROGRAMS
1178 #ifndef HIVE_MEM_tmp_heap
1179 #define HIVE_MEM_tmp_heap scalar_processor_2400_dmem
1181 #define HIVE_ADDR_tmp_heap 0x70A8
1183 #define HIVE_ADDR_tmp_heap 0x7158
1185 #define HIVE_SIZE_tmp_heap 640
1189 #define HIVE_MEM_sp_tmp_heap scalar_processor_2400_dmem
1191 #define HIVE_ADDR_sp_tmp_heap 0x70A8
1193 #define HIVE_ADDR_sp_tmp_heap 0x7158
1195 #define HIVE_SIZE_sp_tmp_heap 640
1198 /* function ia_css_rmgr_sp_get_num_vbuf: 64B0 */
1200 /* function ia_css_rmgr_sp_get_num_vbuf: 6676 */
1204 /* function ia_css_ispctrl_sp_output_compute_dma_info: 4863 */
1206 /* function ia_css_ispctrl_sp_output_compute_dma_info: 4A27 */
1210 /* function ia_css_tagger_sp_lock_exp_id: 2A0F */
1212 /* function ia_css_tagger_sp_lock_exp_id: 29E0 */
1215 #ifndef HIVE_MULTIPLE_PROGRAMS
1216 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs
1217 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem
1219 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5C24
1221 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5CD0
1223 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_s3a_bufs 60
1227 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem
1229 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5C24
1231 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5CD0
1233 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 60
1236 /* function ia_css_queue_is_full: 535E */
1238 /* function ia_css_queue_is_full: 553D */
1241 /* function debug_buffer_init_isp: E4 */
1244 /* function ia_css_tagger_sp_exp_id_is_locked: 2945 */
1246 /* function ia_css_tagger_sp_exp_id_is_locked: 2916 */
1249 #ifndef HIVE_MULTIPLE_PROGRAMS
1250 #ifndef HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem
1251 #define HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem
1253 #define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x7764
1255 #define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x7810
1257 #define HIVE_SIZE_ia_css_rmgr_sp_mipi_frame_sem 60
1261 #define HIVE_MEM_sp_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem
1263 #define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x7764
1265 #define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x7810
1267 #define HIVE_SIZE_sp_ia_css_rmgr_sp_mipi_frame_sem 60
1270 /* function ia_css_rmgr_sp_refcount_dump: 6287 */
1272 /* function ia_css_rmgr_sp_refcount_dump: 644D */
1275 #ifndef HIVE_MULTIPLE_PROGRAMS
1276 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id
1277 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem
1279 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5C60
1281 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5D0C
1283 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_isp_parameters_id 20
1287 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem
1289 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5C60
1291 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5D0C
1293 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 20
1295 #ifndef HIVE_MULTIPLE_PROGRAMS
1296 #ifndef HIVE_MEM_sp_pipe_threads
1297 #define HIVE_MEM_sp_pipe_threads scalar_processor_2400_dmem
1298 #define HIVE_ADDR_sp_pipe_threads 0x150
1299 #define HIVE_SIZE_sp_pipe_threads 20
1303 #define HIVE_MEM_sp_sp_pipe_threads scalar_processor_2400_dmem
1304 #define HIVE_ADDR_sp_sp_pipe_threads 0x150
1305 #define HIVE_SIZE_sp_sp_pipe_threads 20
1308 /* function sp_event_proxy_func: 78D */
1310 /* function sp_event_proxy_func: 721 */
1314 /* function ibuf_ctrl_run: D7F */
1316 /* function ibuf_ctrl_run: D79 */
1319 #ifndef HIVE_MULTIPLE_PROGRAMS
1320 #ifndef HIVE_MEM_host2sp_isys_event_queue_handle
1321 #define HIVE_MEM_host2sp_isys_event_queue_handle scalar_processor_2400_dmem
1323 #define HIVE_ADDR_host2sp_isys_event_queue_handle 0x5C74
1325 #define HIVE_ADDR_host2sp_isys_event_queue_handle 0x5D20
1327 #define HIVE_SIZE_host2sp_isys_event_queue_handle 12
1331 #define HIVE_MEM_sp_host2sp_isys_event_queue_handle scalar_processor_2400_dmem
1333 #define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x5C74
1335 #define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x5D20
1337 #define HIVE_SIZE_sp_host2sp_isys_event_queue_handle 12
1340 /* function ia_css_thread_sp_yield: 6A12 */
1342 /* function ia_css_thread_sp_yield: 6C96 */
1345 #ifndef HIVE_MULTIPLE_PROGRAMS
1346 #ifndef HIVE_MEM_sp_all_cbs_param_desc
1347 #define HIVE_MEM_sp_all_cbs_param_desc scalar_processor_2400_dmem
1349 #define HIVE_ADDR_sp_all_cbs_param_desc 0x5828
1351 #define HIVE_ADDR_sp_all_cbs_param_desc 0x58C4
1353 #define HIVE_SIZE_sp_all_cbs_param_desc 8
1357 #define HIVE_MEM_sp_sp_all_cbs_param_desc scalar_processor_2400_dmem
1359 #define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x5828
1361 #define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x58C4
1363 #define HIVE_SIZE_sp_sp_all_cbs_param_desc 8
1365 #ifndef HIVE_MULTIPLE_PROGRAMS
1366 #ifndef HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb
1367 #define HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem
1369 #define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x6C8C
1371 #define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x6D38
1373 #define HIVE_SIZE_ia_css_dmaproxy_sp_invalidate_tlb 4
1377 #define HIVE_MEM_sp_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem
1379 #define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x6C8C
1381 #define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x6D38
1383 #define HIVE_SIZE_sp_ia_css_dmaproxy_sp_invalidate_tlb 4
1386 /* function ia_css_thread_sp_fork: 13AC */
1388 /* function ia_css_thread_sp_fork: 1322 */
1392 /* function ia_css_tagger_sp_destroy: 3136 */
1394 /* function ia_css_tagger_sp_destroy: 3107 */
1398 /* function ia_css_dmaproxy_sp_vmem_read: 3ADB */
1400 /* function ia_css_dmaproxy_sp_vmem_read: 3C3B */
1403 #ifndef HIVE_MULTIPLE_PROGRAMS
1404 #ifndef HIVE_MEM_N_LONG_PACKET_LUT_ENTRIES
1405 #define HIVE_MEM_N_LONG_PACKET_LUT_ENTRIES scalar_processor_2400_dmem
1406 #define HIVE_ADDR_N_LONG_PACKET_LUT_ENTRIES 0x1B8
1407 #define HIVE_SIZE_N_LONG_PACKET_LUT_ENTRIES 12
1411 #define HIVE_MEM_sp_N_LONG_PACKET_LUT_ENTRIES scalar_processor_2400_dmem
1412 #define HIVE_ADDR_sp_N_LONG_PACKET_LUT_ENTRIES 0x1B8
1413 #define HIVE_SIZE_sp_N_LONG_PACKET_LUT_ENTRIES 12
1416 /* function initialize_sp_group: 5F6 */
1418 /* function initialize_sp_group: 58A */
1422 /* function ia_css_tagger_buf_sp_peek: 325B */
1424 /* function ia_css_tagger_buf_sp_peek: 337E */
1428 /* function ia_css_thread_sp_init: 13D8 */
1430 /* function ia_css_thread_sp_init: 134E */
1434 /* function ia_css_isys_sp_reset_exp_id: 6133 */
1436 /* function qos_scheduler_update_fps: 67AD */
1440 /* function qos_scheduler_update_fps: 65AF */
1442 /* function ia_css_isys_sp_reset_exp_id: 62F9 */
1446 /* function ia_css_ispctrl_sp_set_stream_base_addr: 4F38 */
1448 /* function ia_css_ispctrl_sp_set_stream_base_addr: 5114 */
1451 #ifndef HIVE_MULTIPLE_PROGRAMS
1452 #ifndef HIVE_MEM_ISP_DMEM_BASE
1453 #define HIVE_MEM_ISP_DMEM_BASE scalar_processor_2400_dmem
1454 #define HIVE_ADDR_ISP_DMEM_BASE 0x10
1455 #define HIVE_SIZE_ISP_DMEM_BASE 4
1459 #define HIVE_MEM_sp_ISP_DMEM_BASE scalar_processor_2400_dmem
1460 #define HIVE_ADDR_sp_ISP_DMEM_BASE 0x10
1461 #define HIVE_SIZE_sp_ISP_DMEM_BASE 4
1463 #ifndef HIVE_MULTIPLE_PROGRAMS
1464 #ifndef HIVE_MEM_SP_DMEM_BASE
1465 #define HIVE_MEM_SP_DMEM_BASE scalar_processor_2400_dmem
1466 #define HIVE_ADDR_SP_DMEM_BASE 0x4
1467 #define HIVE_SIZE_SP_DMEM_BASE 4
1471 #define HIVE_MEM_sp_SP_DMEM_BASE scalar_processor_2400_dmem
1472 #define HIVE_ADDR_sp_SP_DMEM_BASE 0x4
1473 #define HIVE_SIZE_sp_SP_DMEM_BASE 4
1476 /* function ibuf_ctrl_transfer: D67 */
1478 /* function ibuf_ctrl_transfer: D61 */
1480 /* function __ia_css_queue_is_empty_text: 5403 */
1484 /* function ia_css_dmaproxy_sp_read: 3B51 */
1486 /* function ia_css_dmaproxy_sp_read: 3CB1 */
1490 /* function virtual_isys_stream_is_capture_done: 5EB0 */
1492 /* function virtual_isys_stream_is_capture_done: 5F94 */
1495 #ifndef HIVE_MULTIPLE_PROGRAMS
1496 #ifndef HIVE_MEM_raw_copy_line_count
1497 #define HIVE_MEM_raw_copy_line_count scalar_processor_2400_dmem
1499 #define HIVE_ADDR_raw_copy_line_count 0x360
1501 #define HIVE_ADDR_raw_copy_line_count 0x378
1503 #define HIVE_SIZE_raw_copy_line_count 4
1507 #define HIVE_MEM_sp_raw_copy_line_count scalar_processor_2400_dmem
1509 #define HIVE_ADDR_sp_raw_copy_line_count 0x360
1511 #define HIVE_ADDR_sp_raw_copy_line_count 0x378
1513 #define HIVE_SIZE_sp_raw_copy_line_count 4
1515 #ifndef HIVE_MULTIPLE_PROGRAMS
1516 #ifndef HIVE_MEM_host2sp_tag_cmd_queue_handle
1517 #define HIVE_MEM_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem
1519 #define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x5C80
1521 #define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x5D2C
1523 #define HIVE_SIZE_host2sp_tag_cmd_queue_handle 12
1527 #define HIVE_MEM_sp_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem
1529 #define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x5C80
1531 #define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x5D2C
1533 #define HIVE_SIZE_sp_host2sp_tag_cmd_queue_handle 12
1536 /* function ia_css_queue_peek: 523D */
1538 /* function ia_css_queue_peek: 541C */
1541 #ifndef HIVE_MULTIPLE_PROGRAMS
1542 #ifndef HIVE_MEM_ia_css_flash_sp_frame_cnt
1543 #define HIVE_MEM_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem
1545 #define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x5B2C
1547 #define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x5BD8
1549 #define HIVE_SIZE_ia_css_flash_sp_frame_cnt 4
1553 #define HIVE_MEM_sp_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem
1555 #define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x5B2C
1557 #define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x5BD8
1559 #define HIVE_SIZE_sp_ia_css_flash_sp_frame_cnt 4
1561 #ifndef HIVE_MULTIPLE_PROGRAMS
1562 #ifndef HIVE_MEM_event_can_send_token_mask
1563 #define HIVE_MEM_event_can_send_token_mask scalar_processor_2400_dmem
1564 #define HIVE_ADDR_event_can_send_token_mask 0x88
1565 #define HIVE_SIZE_event_can_send_token_mask 44
1569 #define HIVE_MEM_sp_event_can_send_token_mask scalar_processor_2400_dmem
1570 #define HIVE_ADDR_sp_event_can_send_token_mask 0x88
1571 #define HIVE_SIZE_sp_event_can_send_token_mask 44
1574 /* function csi_rx_frontend_stop: C11 */
1576 /* function csi_rx_frontend_stop: C0B */
1579 #ifndef HIVE_MULTIPLE_PROGRAMS
1580 #ifndef HIVE_MEM_isp_thread
1581 #define HIVE_MEM_isp_thread scalar_processor_2400_dmem
1583 #define HIVE_ADDR_isp_thread 0x6FD8
1585 #define HIVE_ADDR_isp_thread 0x7088
1587 #define HIVE_SIZE_isp_thread 4
1591 #define HIVE_MEM_sp_isp_thread scalar_processor_2400_dmem
1593 #define HIVE_ADDR_sp_isp_thread 0x6FD8
1595 #define HIVE_ADDR_sp_isp_thread 0x7088
1597 #define HIVE_SIZE_sp_isp_thread 4
1600 /* function encode_and_post_sp_event_non_blocking: AF0 */
1602 /* function encode_and_post_sp_event_non_blocking: A84 */
1605 /* function is_ddr_debug_buffer_full: 2CC */
1608 /* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 32AB */
1610 /* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 33CE */
1613 #ifndef HIVE_MULTIPLE_PROGRAMS
1614 #ifndef HIVE_MEM_sp_threads_fiber
1615 #define HIVE_MEM_sp_threads_fiber scalar_processor_2400_dmem
1616 #define HIVE_ADDR_sp_threads_fiber 0x194
1617 #define HIVE_SIZE_sp_threads_fiber 24
1621 #define HIVE_MEM_sp_sp_threads_fiber scalar_processor_2400_dmem
1622 #define HIVE_ADDR_sp_sp_threads_fiber 0x194
1623 #define HIVE_SIZE_sp_sp_threads_fiber 24
1626 /* function encode_and_post_sp_event: A79 */
1628 /* function encode_and_post_sp_event: A0D */
1631 /* function debug_enqueue_ddr: EE */
1634 /* function ia_css_rmgr_sp_refcount_init_vbuf: 6242 */
1636 /* function ia_css_rmgr_sp_refcount_init_vbuf: 6408 */
1640 /* function dmaproxy_sp_read_write: 6E86 */
1642 /* function dmaproxy_sp_read_write: 70C3 */
1645 #ifndef HIVE_MULTIPLE_PROGRAMS
1646 #ifndef HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer
1647 #define HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem
1649 #define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6C90
1651 #define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6D3C
1653 #define HIVE_SIZE_ia_css_dmaproxy_isp_dma_cmd_buffer 4
1657 #define HIVE_MEM_sp_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem
1659 #define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6C90
1661 #define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6D3C
1663 #define HIVE_SIZE_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 4
1665 #ifndef HIVE_MULTIPLE_PROGRAMS
1666 #ifndef HIVE_MEM_host2sp_buffer_queue_handle
1667 #define HIVE_MEM_host2sp_buffer_queue_handle scalar_processor_2400_dmem
1669 #define HIVE_ADDR_host2sp_buffer_queue_handle 0x5C8C
1671 #define HIVE_ADDR_host2sp_buffer_queue_handle 0x5D38
1673 #define HIVE_SIZE_host2sp_buffer_queue_handle 480
1677 #define HIVE_MEM_sp_host2sp_buffer_queue_handle scalar_processor_2400_dmem
1679 #define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x5C8C
1681 #define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x5D38
1683 #define HIVE_SIZE_sp_host2sp_buffer_queue_handle 480
1685 #ifndef HIVE_MULTIPLE_PROGRAMS
1686 #ifndef HIVE_MEM_ia_css_flash_sp_in_service
1687 #define HIVE_MEM_ia_css_flash_sp_in_service scalar_processor_2400_dmem
1689 #define HIVE_ADDR_ia_css_flash_sp_in_service 0x3054
1691 #define HIVE_ADDR_ia_css_flash_sp_in_service 0x3074
1693 #define HIVE_SIZE_ia_css_flash_sp_in_service 4
1697 #define HIVE_MEM_sp_ia_css_flash_sp_in_service scalar_processor_2400_dmem
1699 #define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3054
1701 #define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3074
1703 #define HIVE_SIZE_sp_ia_css_flash_sp_in_service 4
1706 /* function ia_css_dmaproxy_sp_process: 6B92 */
1708 /* function ia_css_dmaproxy_sp_process: 6E0F */
1712 /* function ia_css_tagger_buf_sp_mark_from_end: 3533 */
1714 /* function ia_css_tagger_buf_sp_mark_from_end: 3656 */
1718 /* function ia_css_ispctrl_sp_init_cs: 3F77 */
1720 /* function ia_css_ispctrl_sp_init_cs: 40FA */
1724 /* function ia_css_spctrl_sp_init: 5E02 */
1726 /* function ia_css_spctrl_sp_init: 5EE4 */
1730 /* function sp_event_proxy_init: 7A2 */
1732 /* function sp_event_proxy_init: 736 */
1736 /* function input_system_input_port_close: 109B */
1738 /* function input_system_input_port_close: 1095 */
1741 #ifndef HIVE_MULTIPLE_PROGRAMS
1742 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick
1743 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem
1745 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5E6C
1747 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5F18
1749 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_previous_clock_tick 40
1753 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem
1755 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5E6C
1757 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5F18
1759 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 40
1761 #ifndef HIVE_MULTIPLE_PROGRAMS
1762 #ifndef HIVE_MEM_sp_output
1763 #define HIVE_MEM_sp_output scalar_processor_2400_dmem
1765 #define HIVE_ADDR_sp_output 0x3F2C
1767 #define HIVE_ADDR_sp_output 0x3F50
1769 #define HIVE_SIZE_sp_output 16
1773 #define HIVE_MEM_sp_sp_output scalar_processor_2400_dmem
1775 #define HIVE_ADDR_sp_sp_output 0x3F2C
1777 #define HIVE_ADDR_sp_sp_output 0x3F50
1779 #define HIVE_SIZE_sp_sp_output 16
1781 #ifndef HIVE_MULTIPLE_PROGRAMS
1782 #ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues
1783 #define HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem
1785 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5E94
1787 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5F40
1789 #define HIVE_SIZE_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800
1793 #define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem
1795 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5E94
1797 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5F40
1799 #define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800
1802 /* function pixelgen_prbs_config: E93 */
1804 /* function pixelgen_prbs_config: E8D */
1807 #ifndef HIVE_MULTIPLE_PROGRAMS
1808 #ifndef HIVE_MEM_ISP_CTRL_BASE
1809 #define HIVE_MEM_ISP_CTRL_BASE scalar_processor_2400_dmem
1810 #define HIVE_ADDR_ISP_CTRL_BASE 0x8
1811 #define HIVE_SIZE_ISP_CTRL_BASE 4
1815 #define HIVE_MEM_sp_ISP_CTRL_BASE scalar_processor_2400_dmem
1816 #define HIVE_ADDR_sp_ISP_CTRL_BASE 0x8
1817 #define HIVE_SIZE_sp_ISP_CTRL_BASE 4
1819 #ifndef HIVE_MULTIPLE_PROGRAMS
1820 #ifndef HIVE_MEM_INPUT_FORMATTER_BASE
1821 #define HIVE_MEM_INPUT_FORMATTER_BASE scalar_processor_2400_dmem
1822 #define HIVE_ADDR_INPUT_FORMATTER_BASE 0x4C
1823 #define HIVE_SIZE_INPUT_FORMATTER_BASE 16
1827 #define HIVE_MEM_sp_INPUT_FORMATTER_BASE scalar_processor_2400_dmem
1828 #define HIVE_ADDR_sp_INPUT_FORMATTER_BASE 0x4C
1829 #define HIVE_SIZE_sp_INPUT_FORMATTER_BASE 16
1832 /* function sp_dma_proxy_reset_channels: 3DAB */
1834 /* function sp_dma_proxy_reset_channels: 3F20 */
1838 /* function ia_css_tagger_sp_update_size: 322A */
1840 /* function ia_css_tagger_sp_update_size: 334D */
1843 #ifndef HIVE_MULTIPLE_PROGRAMS
1844 #ifndef HIVE_MEM_ia_css_bufq_host_sp_queue
1845 #define HIVE_MEM_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem
1847 #define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x61B4
1849 #define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x6260
1851 #define HIVE_SIZE_ia_css_bufq_host_sp_queue 2008
1855 #define HIVE_MEM_sp_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem
1857 #define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x61B4
1859 #define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x6260
1861 #define HIVE_SIZE_sp_ia_css_bufq_host_sp_queue 2008
1864 /* function thread_fiber_sp_create: 1444 */
1866 /* function thread_fiber_sp_create: 13BA */
1870 /* function ia_css_dmaproxy_sp_set_increments: 3C3D */
1872 /* function ia_css_dmaproxy_sp_set_increments: 3DB2 */
1875 #ifndef HIVE_MULTIPLE_PROGRAMS
1876 #ifndef HIVE_MEM_sem_for_writing_cb_frame
1877 #define HIVE_MEM_sem_for_writing_cb_frame scalar_processor_2400_dmem
1879 #define HIVE_ADDR_sem_for_writing_cb_frame 0x5830
1881 #define HIVE_ADDR_sem_for_writing_cb_frame 0x58CC
1883 #define HIVE_SIZE_sem_for_writing_cb_frame 20
1887 #define HIVE_MEM_sp_sem_for_writing_cb_frame scalar_processor_2400_dmem
1889 #define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x5830
1891 #define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x58CC
1893 #define HIVE_SIZE_sp_sem_for_writing_cb_frame 20
1895 #ifndef HIVE_MULTIPLE_PROGRAMS
1896 #ifndef HIVE_MEM_sem_for_writing_cb_param
1897 #define HIVE_MEM_sem_for_writing_cb_param scalar_processor_2400_dmem
1899 #define HIVE_ADDR_sem_for_writing_cb_param 0x5844
1901 #define HIVE_ADDR_sem_for_writing_cb_param 0x58E0
1903 #define HIVE_SIZE_sem_for_writing_cb_param 20
1907 #define HIVE_MEM_sp_sem_for_writing_cb_param scalar_processor_2400_dmem
1909 #define HIVE_ADDR_sp_sem_for_writing_cb_param 0x5844
1911 #define HIVE_ADDR_sp_sem_for_writing_cb_param 0x58E0
1913 #define HIVE_SIZE_sp_sem_for_writing_cb_param 20
1916 /* function pixelgen_tpg_is_done: F0D */
1918 /* function pixelgen_tpg_is_done: F07 */
1922 /* function ia_css_isys_stream_capture_indication: 5FB6 */
1924 /* function ia_css_isys_stream_capture_indication: 60D7 */
1927 /* function sp_start_isp_entry: 392 */
1928 #ifndef HIVE_MULTIPLE_PROGRAMS
1929 #ifdef HIVE_ADDR_sp_start_isp_entry
1931 #define HIVE_ADDR_sp_start_isp_entry 0x392
1933 #define HIVE_ADDR_sp_sp_start_isp_entry 0x392
1936 /* function ia_css_tagger_buf_sp_unmark_all: 34B7 */
1938 /* function ia_css_tagger_buf_sp_unmark_all: 35DA */
1942 /* function ia_css_tagger_buf_sp_unmark_from_start: 34F8 */
1944 /* function ia_css_tagger_buf_sp_unmark_from_start: 361B */
1948 /* function ia_css_dmaproxy_sp_channel_acquire: 3DD7 */
1950 /* function ia_css_dmaproxy_sp_channel_acquire: 3F4C */
1954 /* function ia_css_rmgr_sp_add_num_vbuf: 648C */
1956 /* function ia_css_rmgr_sp_add_num_vbuf: 6652 */
1960 /* function ibuf_ctrl_config: D8B */
1962 /* function ibuf_ctrl_config: D85 */
1966 /* function ia_css_isys_stream_stop: 602E */
1968 /* function ia_css_isys_stream_stop: 61F4 */
1972 /* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3AA7 */
1974 /* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3C07 */
1978 /* function ia_css_tagger_sp_acquire_buf_elem: 291D */
1980 /* function ia_css_tagger_sp_acquire_buf_elem: 28EE */
1984 /* function ia_css_bufq_sp_is_dynamic_buffer: 3990 */
1986 /* function ia_css_bufq_sp_is_dynamic_buffer: 3AB3 */
1989 #ifndef HIVE_MULTIPLE_PROGRAMS
1990 #ifndef HIVE_MEM_sp_group
1991 #define HIVE_MEM_sp_group scalar_processor_2400_dmem
1993 #define HIVE_ADDR_sp_group 0x3F3C
1994 #define HIVE_SIZE_sp_group 6176
1996 #define HIVE_ADDR_sp_group 0x3F60
1997 #define HIVE_SIZE_sp_group 6296
2002 #define HIVE_MEM_sp_sp_group scalar_processor_2400_dmem
2004 #define HIVE_ADDR_sp_sp_group 0x3F3C
2005 #define HIVE_SIZE_sp_sp_group 6176
2007 #define HIVE_ADDR_sp_sp_group 0x3F60
2008 #define HIVE_SIZE_sp_sp_group 6296
2011 #ifndef HIVE_MULTIPLE_PROGRAMS
2012 #ifndef HIVE_MEM_sp_event_proxy_thread
2013 #define HIVE_MEM_sp_event_proxy_thread scalar_processor_2400_dmem
2015 #define HIVE_ADDR_sp_event_proxy_thread 0x5A30
2016 #define HIVE_SIZE_sp_event_proxy_thread 68
2018 #define HIVE_ADDR_sp_event_proxy_thread 0x5AE0
2019 #define HIVE_SIZE_sp_event_proxy_thread 72
2024 #define HIVE_MEM_sp_sp_event_proxy_thread scalar_processor_2400_dmem
2026 #define HIVE_ADDR_sp_sp_event_proxy_thread 0x5A30
2027 #define HIVE_SIZE_sp_sp_event_proxy_thread 68
2029 #define HIVE_ADDR_sp_sp_event_proxy_thread 0x5AE0
2030 #define HIVE_SIZE_sp_sp_event_proxy_thread 72
2034 /* function ia_css_thread_sp_kill: 1372 */
2036 /* function ia_css_thread_sp_kill: 12E8 */
2040 /* function ia_css_tagger_sp_create: 31E4 */
2042 /* function ia_css_tagger_sp_create: 32FB */
2046 /* function tmpmem_acquire_dmem: 6539 */
2048 /* function tmpmem_acquire_dmem: 66FF */
2051 #ifndef HIVE_MULTIPLE_PROGRAMS
2052 #ifndef HIVE_MEM_MMU_BASE
2053 #define HIVE_MEM_MMU_BASE scalar_processor_2400_dmem
2054 #define HIVE_ADDR_MMU_BASE 0x24
2055 #define HIVE_SIZE_MMU_BASE 8
2059 #define HIVE_MEM_sp_MMU_BASE scalar_processor_2400_dmem
2060 #define HIVE_ADDR_sp_MMU_BASE 0x24
2061 #define HIVE_SIZE_sp_MMU_BASE 8
2064 /* function ia_css_dmaproxy_sp_channel_release: 3DC3 */
2066 /* function ia_css_dmaproxy_sp_channel_release: 3F38 */
2070 /* function pixelgen_prbs_run: E81 */
2072 /* function pixelgen_prbs_run: E7B */
2076 /* function ia_css_dmaproxy_sp_is_idle: 3DA3 */
2078 /* function ia_css_dmaproxy_sp_is_idle: 3F18 */
2081 #ifndef HIVE_MULTIPLE_PROGRAMS
2082 #ifndef HIVE_MEM_sem_for_qos_start
2083 #define HIVE_MEM_sem_for_qos_start scalar_processor_2400_dmem
2085 #define HIVE_ADDR_sem_for_qos_start 0x5858
2087 #define HIVE_ADDR_sem_for_qos_start 0x58F4
2089 #define HIVE_SIZE_sem_for_qos_start 20
2093 #define HIVE_MEM_sp_sem_for_qos_start scalar_processor_2400_dmem
2095 #define HIVE_ADDR_sp_sem_for_qos_start 0x5858
2097 #define HIVE_ADDR_sp_sem_for_qos_start 0x58F4
2099 #define HIVE_SIZE_sp_sem_for_qos_start 20
2102 /* function isp_hmem_load: B63 */
2104 /* function isp_hmem_load: B5D */
2108 /* function ia_css_tagger_sp_release_buf_elem: 28F9 */
2110 /* function ia_css_tagger_sp_release_buf_elem: 28CA */
2114 /* function ia_css_eventq_sp_send: 3E19 */
2116 /* function ia_css_eventq_sp_send: 3F8E */
2120 /* function ia_css_tagger_buf_sp_unlock_from_start: 33E7 */
2122 /* function ia_css_tagger_buf_sp_unlock_from_start: 350A */
2125 #ifndef HIVE_MULTIPLE_PROGRAMS
2126 #ifndef HIVE_MEM_debug_buffer_ddr_address
2127 #define HIVE_MEM_debug_buffer_ddr_address scalar_processor_2400_dmem
2128 #define HIVE_ADDR_debug_buffer_ddr_address 0xBC
2129 #define HIVE_SIZE_debug_buffer_ddr_address 4
2133 #define HIVE_MEM_sp_debug_buffer_ddr_address scalar_processor_2400_dmem
2134 #define HIVE_ADDR_sp_debug_buffer_ddr_address 0xBC
2135 #define HIVE_SIZE_sp_debug_buffer_ddr_address 4
2138 /* function sp_isys_copy_request: 6ED */
2140 /* function sp_isys_copy_request: 681 */
2144 /* function ia_css_rmgr_sp_refcount_retain_vbuf: 631C */
2146 /* function ia_css_rmgr_sp_refcount_retain_vbuf: 64E2 */
2150 /* function ia_css_thread_sp_set_priority: 136A */
2152 /* function ia_css_thread_sp_set_priority: 12E0 */
2156 /* function sizeof_hmem: C0A */
2158 /* function sizeof_hmem: C04 */
2162 /* function input_system_channel_open: 1241 */
2164 /* function input_system_channel_open: 11BC */
2168 /* function pixelgen_tpg_stop: EFB */
2170 /* function pixelgen_tpg_stop: EF5 */
2174 /* function tmpmem_release_dmem: 6528 */
2176 /* function tmpmem_release_dmem: 66EE */
2180 /* function ia_css_dmaproxy_sp_set_width_exception: 3C28 */
2182 /* function __ia_css_dmaproxy_sp_process_text: 3BAB */
2186 /* function sp_event_assert: 929 */
2188 /* function ia_css_dmaproxy_sp_set_width_exception: 3D9D */
2192 /* function ia_css_flash_sp_init_internal_params: 35B4 */
2194 /* function sp_event_assert: 8BD */
2198 /* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 32ED */
2200 /* function ia_css_flash_sp_init_internal_params: 36D7 */
2204 /* function __modu: 687A */
2206 /* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 3410 */
2210 /* function ia_css_dmaproxy_sp_init_isp_vector: 3AAD */
2212 /* function __modu: 6A78 */
2216 /* function input_system_channel_transfer: 122A */
2218 /* function ia_css_dmaproxy_sp_init_isp_vector: 3C0D */
2220 /* function input_system_channel_transfer: 11A5 */
2223 /* function isp_vamem_store: 0 */
2226 /* function ia_css_tagger_sp_set_copy_pipe: 32F2 */
2229 #ifndef HIVE_MULTIPLE_PROGRAMS
2230 #ifndef HIVE_MEM_GDC_BASE
2231 #define HIVE_MEM_GDC_BASE scalar_processor_2400_dmem
2232 #define HIVE_ADDR_GDC_BASE 0x44
2233 #define HIVE_SIZE_GDC_BASE 8
2237 #define HIVE_MEM_sp_GDC_BASE scalar_processor_2400_dmem
2238 #define HIVE_ADDR_sp_GDC_BASE 0x44
2239 #define HIVE_SIZE_sp_GDC_BASE 8
2242 /* function ia_css_queue_local_init: 5528 */
2244 /* function ia_css_queue_local_init: 5707 */
2248 /* function sp_event_proxy_callout_func: 6947 */
2250 /* function sp_event_proxy_callout_func: 6B45 */
2254 /* function qos_scheduler_schedule_stage: 6580 */
2256 /* function qos_scheduler_schedule_stage: 6759 */
2259 #ifndef HIVE_MULTIPLE_PROGRAMS
2260 #ifndef HIVE_MEM_ia_css_thread_sp_num_ready_threads
2261 #define HIVE_MEM_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem
2263 #define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x5A78
2265 #define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x5B28
2267 #define HIVE_SIZE_ia_css_thread_sp_num_ready_threads 4
2271 #define HIVE_MEM_sp_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem
2273 #define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x5A78
2275 #define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x5B28
2277 #define HIVE_SIZE_sp_ia_css_thread_sp_num_ready_threads 4
2279 #ifndef HIVE_MULTIPLE_PROGRAMS
2280 #ifndef HIVE_MEM_sp_threads_stack_size
2281 #define HIVE_MEM_sp_threads_stack_size scalar_processor_2400_dmem
2282 #define HIVE_ADDR_sp_threads_stack_size 0x17C
2283 #define HIVE_SIZE_sp_threads_stack_size 24
2287 #define HIVE_MEM_sp_sp_threads_stack_size scalar_processor_2400_dmem
2288 #define HIVE_ADDR_sp_sp_threads_stack_size 0x17C
2289 #define HIVE_SIZE_sp_sp_threads_stack_size 24
2292 /* function ia_css_ispctrl_sp_isp_done_row_striping: 4849 */
2294 /* function ia_css_ispctrl_sp_isp_done_row_striping: 4A0D */
2298 /* function __ia_css_virtual_isys_sp_isr_text: 5E45 */
2300 /* function __ia_css_virtual_isys_sp_isr_text: 5F4E */
2304 /* function ia_css_queue_dequeue: 53A6 */
2306 /* function ia_css_queue_dequeue: 5585 */
2310 /* function ia_css_dmaproxy_sp_configure_channel: 6DEE */
2312 /* function is_qos_standalone_mode: 6734 */
2314 /* function ia_css_dmaproxy_sp_configure_channel: 703C */
2317 #ifndef HIVE_MULTIPLE_PROGRAMS
2318 #ifndef HIVE_MEM_current_thread_fiber_sp
2319 #define HIVE_MEM_current_thread_fiber_sp scalar_processor_2400_dmem
2321 #define HIVE_ADDR_current_thread_fiber_sp 0x5A80
2323 #define HIVE_ADDR_current_thread_fiber_sp 0x5B2C
2325 #define HIVE_SIZE_current_thread_fiber_sp 4
2329 #define HIVE_MEM_sp_current_thread_fiber_sp scalar_processor_2400_dmem
2331 #define HIVE_ADDR_sp_current_thread_fiber_sp 0x5A80
2333 #define HIVE_ADDR_sp_current_thread_fiber_sp 0x5B2C
2335 #define HIVE_SIZE_sp_current_thread_fiber_sp 4
2338 /* function ia_css_circbuf_pop: 1674 */
2340 /* function ia_css_circbuf_pop: 15EA */
2344 /* function memset: 68F9 */
2346 /* function memset: 6AF7 */
2349 /* function irq_raise_set_token: B6 */
2351 #ifndef HIVE_MULTIPLE_PROGRAMS
2352 #ifndef HIVE_MEM_GPIO_BASE
2353 #define HIVE_MEM_GPIO_BASE scalar_processor_2400_dmem
2354 #define HIVE_ADDR_GPIO_BASE 0x3C
2355 #define HIVE_SIZE_GPIO_BASE 4
2359 #define HIVE_MEM_sp_GPIO_BASE scalar_processor_2400_dmem
2360 #define HIVE_ADDR_sp_GPIO_BASE 0x3C
2361 #define HIVE_SIZE_sp_GPIO_BASE 4
2364 /* function pixelgen_prbs_stop: E6F */
2366 /* function pixelgen_prbs_stop: E69 */
2370 /* function ia_css_pipeline_acc_stage_enable: 1FC0 */
2372 /* function ia_css_pipeline_acc_stage_enable: 1F69 */
2376 /* function ia_css_tagger_sp_unlock_exp_id: 296A */
2378 /* function ia_css_tagger_sp_unlock_exp_id: 293B */
2381 #ifndef HIVE_MULTIPLE_PROGRAMS
2382 #ifndef HIVE_MEM_isp_ph
2383 #define HIVE_MEM_isp_ph scalar_processor_2400_dmem
2385 #define HIVE_ADDR_isp_ph 0x7360
2387 #define HIVE_ADDR_isp_ph 0x740C
2389 #define HIVE_SIZE_isp_ph 28
2393 #define HIVE_MEM_sp_isp_ph scalar_processor_2400_dmem
2395 #define HIVE_ADDR_sp_isp_ph 0x7360
2397 #define HIVE_ADDR_sp_isp_ph 0x740C
2399 #define HIVE_SIZE_sp_isp_ph 28
2402 /* function ia_css_ispctrl_sp_init_ds: 40D6 */
2404 /* function ia_css_ispctrl_sp_init_ds: 4286 */
2408 /* function get_xmem_base_addr_raw: 4479 */
2410 /* function get_xmem_base_addr_raw: 4635 */
2413 #ifndef HIVE_MULTIPLE_PROGRAMS
2414 #ifndef HIVE_MEM_sp_all_cbs_param
2415 #define HIVE_MEM_sp_all_cbs_param scalar_processor_2400_dmem
2417 #define HIVE_ADDR_sp_all_cbs_param 0x586C
2419 #define HIVE_ADDR_sp_all_cbs_param 0x5908
2421 #define HIVE_SIZE_sp_all_cbs_param 16
2425 #define HIVE_MEM_sp_sp_all_cbs_param scalar_processor_2400_dmem
2427 #define HIVE_ADDR_sp_sp_all_cbs_param 0x586C
2429 #define HIVE_ADDR_sp_sp_all_cbs_param 0x5908
2431 #define HIVE_SIZE_sp_sp_all_cbs_param 16
2434 /* function pixelgen_tpg_config: F30 */
2436 /* function pixelgen_tpg_config: F2A */
2440 /* function ia_css_circbuf_create: 16C2 */
2442 /* function ia_css_circbuf_create: 1638 */
2445 #ifndef HIVE_MULTIPLE_PROGRAMS
2446 #ifndef HIVE_MEM_sem_for_sp_group
2447 #define HIVE_MEM_sem_for_sp_group scalar_processor_2400_dmem
2449 #define HIVE_ADDR_sem_for_sp_group 0x587C
2451 #define HIVE_ADDR_sem_for_sp_group 0x5918
2453 #define HIVE_SIZE_sem_for_sp_group 20
2457 #define HIVE_MEM_sp_sem_for_sp_group scalar_processor_2400_dmem
2459 #define HIVE_ADDR_sp_sem_for_sp_group 0x587C
2461 #define HIVE_ADDR_sp_sem_for_sp_group 0x5918
2463 #define HIVE_SIZE_sp_sem_for_sp_group 20
2466 /* function csi_rx_frontend_run: C22 */
2468 /* function csi_rx_frontend_run: C1C */
2470 /* function __ia_css_dmaproxy_sp_configure_channel_text: 3D7C */
2474 /* function ia_css_framebuf_sp_wait_for_in_frame: 64B7 */
2476 /* function ia_css_framebuf_sp_wait_for_in_frame: 667D */
2480 /* function ia_css_isys_stream_open: 60E3 */
2482 /* function ia_css_isys_stream_open: 62A9 */
2486 /* function ia_css_sp_rawcopy_tag_frame: 5C71 */
2488 /* function ia_css_sp_rawcopy_tag_frame: 5E35 */
2492 /* function input_system_channel_configure: 125D */
2494 /* function input_system_channel_configure: 11D8 */
2498 /* function isp_hmem_clear: B33 */
2500 /* function isp_hmem_clear: B2D */
2504 /* function ia_css_framebuf_sp_release_in_frame: 64FA */
2506 /* function ia_css_framebuf_sp_release_in_frame: 66C0 */
2510 /* function stream2mmio_config: E1B */
2512 /* function stream2mmio_config: E15 */
2516 /* function ia_css_ispctrl_sp_start_binary: 3F55 */
2518 /* function ia_css_ispctrl_sp_start_binary: 40D8 */
2521 #ifndef HIVE_MULTIPLE_PROGRAMS
2522 #ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs
2523 #define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem
2525 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x698C
2527 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x6A38
2529 #define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20
2533 #define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem
2535 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x698C
2537 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x6A38
2539 #define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20
2542 /* function ia_css_eventq_sp_recv: 3DEB */
2544 /* function ia_css_eventq_sp_recv: 3F60 */
2548 /* function csi_rx_frontend_config: C7A */
2550 /* function csi_rx_frontend_config: C74 */
2553 #ifndef HIVE_MULTIPLE_PROGRAMS
2554 #ifndef HIVE_MEM_isp_pool
2555 #define HIVE_MEM_isp_pool scalar_processor_2400_dmem
2557 #define HIVE_ADDR_isp_pool 0x370
2559 #define HIVE_ADDR_isp_pool 0x388
2561 #define HIVE_SIZE_isp_pool 4
2565 #define HIVE_MEM_sp_isp_pool scalar_processor_2400_dmem
2567 #define HIVE_ADDR_sp_isp_pool 0x370
2569 #define HIVE_ADDR_sp_isp_pool 0x388
2571 #define HIVE_SIZE_sp_isp_pool 4
2574 /* function ia_css_rmgr_sp_rel_gen: 61E9 */
2576 /* function ia_css_rmgr_sp_rel_gen: 63AF */
2578 /* function ia_css_tagger_sp_unblock_clients: 31C3 */
2582 /* function css_get_frame_processing_time_end: 28E9 */
2584 /* function css_get_frame_processing_time_end: 28BA */
2587 #ifndef HIVE_MULTIPLE_PROGRAMS
2588 #ifndef HIVE_MEM_event_any_pending_mask
2589 #define HIVE_MEM_event_any_pending_mask scalar_processor_2400_dmem
2591 #define HIVE_ADDR_event_any_pending_mask 0x388
2593 #define HIVE_ADDR_event_any_pending_mask 0x3A0
2595 #define HIVE_SIZE_event_any_pending_mask 8
2599 #define HIVE_MEM_sp_event_any_pending_mask scalar_processor_2400_dmem
2601 #define HIVE_ADDR_sp_event_any_pending_mask 0x388
2603 #define HIVE_ADDR_sp_event_any_pending_mask 0x3A0
2605 #define HIVE_SIZE_sp_event_any_pending_mask 8
2608 /* function ia_css_pipeline_sp_get_pipe_io_status: 1AB8 */
2610 /* function ia_css_pipeline_sp_get_pipe_io_status: 1A5A */
2613 /* function sh_css_decode_tag_descr: 352 */
2615 /* function debug_enqueue_isp: 27B */
2618 /* function qos_scheduler_update_stage_budget: 656E */
2620 /* function qos_scheduler_update_stage_budget: 673C */
2624 /* function ia_css_spctrl_sp_uninit: 5DFB */
2626 /* function ia_css_spctrl_sp_uninit: 5EDD */
2630 /* function csi_rx_backend_run: C68 */
2632 /* function csi_rx_backend_run: C62 */
2635 #ifndef HIVE_MULTIPLE_PROGRAMS
2636 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs
2637 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem
2639 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x69A0
2641 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x6A4C
2643 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_dis_bufs 140
2647 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem
2649 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x69A0
2651 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x6A4C
2653 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_dis_bufs 140
2656 /* function ia_css_tagger_buf_sp_lock_from_start: 341B */
2658 /* function ia_css_tagger_buf_sp_lock_from_start: 353E */
2661 #ifndef HIVE_MULTIPLE_PROGRAMS
2662 #ifndef HIVE_MEM_sem_for_isp_idle
2663 #define HIVE_MEM_sem_for_isp_idle scalar_processor_2400_dmem
2665 #define HIVE_ADDR_sem_for_isp_idle 0x5890
2667 #define HIVE_ADDR_sem_for_isp_idle 0x592C
2669 #define HIVE_SIZE_sem_for_isp_idle 20
2673 #define HIVE_MEM_sp_sem_for_isp_idle scalar_processor_2400_dmem
2675 #define HIVE_ADDR_sp_sem_for_isp_idle 0x5890
2677 #define HIVE_ADDR_sp_sem_for_isp_idle 0x592C
2679 #define HIVE_SIZE_sp_sem_for_isp_idle 20
2682 /* function ia_css_dmaproxy_sp_write_byte_addr: 3B0A */
2684 /* function ia_css_dmaproxy_sp_write_byte_addr: 3C6A */
2688 /* function ia_css_dmaproxy_sp_init: 3A81 */
2690 /* function ia_css_dmaproxy_sp_init: 3BE1 */
2694 /* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 3686 */
2696 /* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 37A9 */
2699 #ifndef HIVE_MULTIPLE_PROGRAMS
2700 #ifndef HIVE_MEM_ISP_VAMEM_BASE
2701 #define HIVE_MEM_ISP_VAMEM_BASE scalar_processor_2400_dmem
2702 #define HIVE_ADDR_ISP_VAMEM_BASE 0x14
2703 #define HIVE_SIZE_ISP_VAMEM_BASE 12
2707 #define HIVE_MEM_sp_ISP_VAMEM_BASE scalar_processor_2400_dmem
2708 #define HIVE_ADDR_sp_ISP_VAMEM_BASE 0x14
2709 #define HIVE_SIZE_sp_ISP_VAMEM_BASE 12
2712 /* function input_system_channel_sync: 11A4 */
2714 /* function input_system_channel_sync: 6C10 */
2717 #ifndef HIVE_MULTIPLE_PROGRAMS
2718 #ifndef HIVE_MEM_ia_css_rawcopy_sp_tagger
2719 #define HIVE_MEM_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem
2721 #define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x732C
2723 #define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x73D8
2725 #define HIVE_SIZE_ia_css_rawcopy_sp_tagger 24
2729 #define HIVE_MEM_sp_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem
2731 #define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x732C
2733 #define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x73D8
2735 #define HIVE_SIZE_sp_ia_css_rawcopy_sp_tagger 24
2737 #ifndef HIVE_MULTIPLE_PROGRAMS
2738 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids
2739 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem
2741 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x6A2C
2743 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x6AD8
2745 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_exp_ids 70
2749 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem
2751 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x6A2C
2753 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x6AD8
2755 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_exp_ids 70
2758 /* function ia_css_queue_item_load: 561A */
2760 /* function ia_css_queue_item_load: 57F9 */
2764 /* function ia_css_spctrl_sp_get_state: 5DE6 */
2766 /* function ia_css_spctrl_sp_get_state: 5EC8 */
2769 #ifndef HIVE_MULTIPLE_PROGRAMS
2770 #ifndef HIVE_MEM_callout_sp_thread
2771 #define HIVE_MEM_callout_sp_thread scalar_processor_2400_dmem
2773 #define HIVE_ADDR_callout_sp_thread 0x5A74
2775 #define HIVE_ADDR_callout_sp_thread 0x278
2777 #define HIVE_SIZE_callout_sp_thread 4
2781 #define HIVE_MEM_sp_callout_sp_thread scalar_processor_2400_dmem
2783 #define HIVE_ADDR_sp_callout_sp_thread 0x5A74
2785 #define HIVE_ADDR_sp_callout_sp_thread 0x278
2787 #define HIVE_SIZE_sp_callout_sp_thread 4
2790 /* function thread_fiber_sp_init: 14CB */
2792 /* function thread_fiber_sp_init: 1441 */
2795 #ifndef HIVE_MULTIPLE_PROGRAMS
2796 #ifndef HIVE_MEM_SP_PMEM_BASE
2797 #define HIVE_MEM_SP_PMEM_BASE scalar_processor_2400_dmem
2798 #define HIVE_ADDR_SP_PMEM_BASE 0x0
2799 #define HIVE_SIZE_SP_PMEM_BASE 4
2803 #define HIVE_MEM_sp_SP_PMEM_BASE scalar_processor_2400_dmem
2804 #define HIVE_ADDR_sp_SP_PMEM_BASE 0x0
2805 #define HIVE_SIZE_sp_SP_PMEM_BASE 4
2807 #ifndef HIVE_MULTIPLE_PROGRAMS
2808 #ifndef HIVE_MEM_sp_isp_input_stream_format
2809 #define HIVE_MEM_sp_isp_input_stream_format scalar_processor_2400_dmem
2811 #define HIVE_ADDR_sp_isp_input_stream_format 0x3E2C
2813 #define HIVE_ADDR_sp_isp_input_stream_format 0x3E50
2815 #define HIVE_SIZE_sp_isp_input_stream_format 20
2819 #define HIVE_MEM_sp_sp_isp_input_stream_format scalar_processor_2400_dmem
2821 #define HIVE_ADDR_sp_sp_isp_input_stream_format 0x3E2C
2823 #define HIVE_ADDR_sp_sp_isp_input_stream_format 0x3E50
2825 #define HIVE_SIZE_sp_sp_isp_input_stream_format 20
2828 /* function __mod: 6866 */
2830 /* function __mod: 6A64 */
2834 /* function ia_css_dmaproxy_sp_init_dmem_channel: 3B6B */
2836 /* function ia_css_dmaproxy_sp_init_dmem_channel: 3CCB */
2840 /* function ia_css_thread_sp_join: 139B */
2842 /* function ia_css_thread_sp_join: 1311 */
2846 /* function ia_css_dmaproxy_sp_add_command: 6EF1 */
2848 /* function ia_css_dmaproxy_sp_add_command: 712E */
2852 /* function ia_css_sp_metadata_thread_func: 5DDF */
2854 /* function ia_css_sp_metadata_thread_func: 5EC1 */
2858 /* function __sp_event_proxy_func_critical: 6934 */
2860 /* function __sp_event_proxy_func_critical: 6B32 */
2864 /* function ia_css_pipeline_sp_wait_for_isys_stream_N: 5F53 */
2866 /* function ia_css_pipeline_sp_wait_for_isys_stream_N: 6074 */
2870 /* function ia_css_sp_metadata_wait: 5DD8 */
2872 /* function ia_css_sp_metadata_wait: 5EBA */
2876 /* function ia_css_circbuf_peek_from_start: 15A4 */
2878 /* function ia_css_circbuf_peek_from_start: 151A */
2882 /* function ia_css_event_sp_encode: 3E76 */
2884 /* function ia_css_event_sp_encode: 3FEB */
2888 /* function ia_css_thread_sp_run: 140E */
2890 /* function ia_css_thread_sp_run: 1384 */
2894 /* function sp_isys_copy_func: 618 */
2896 /* function sp_isys_copy_func: 5AC */
2900 /* function ia_css_sp_isp_param_init_isp_memories: 50A3 */
2902 /* function ia_css_sp_isp_param_init_isp_memories: 52AC */
2906 /* function register_isr: 921 */
2908 /* function register_isr: 8B5 */
2911 /* function irq_raise: C8 */
2914 /* function ia_css_dmaproxy_sp_mmu_invalidate: 3A48 */
2916 /* function ia_css_dmaproxy_sp_mmu_invalidate: 3B71 */
2920 /* function csi_rx_backend_disable: C34 */
2922 /* function csi_rx_backend_disable: C2E */
2926 /* function pipeline_sp_initialize_stage: 2104 */
2928 /* function pipeline_sp_initialize_stage: 20BF */
2931 #ifndef HIVE_MULTIPLE_PROGRAMS
2932 #ifndef HIVE_MEM_N_CSI_RX_FE_CTRL_DLANES
2933 #define HIVE_MEM_N_CSI_RX_FE_CTRL_DLANES scalar_processor_2400_dmem
2934 #define HIVE_ADDR_N_CSI_RX_FE_CTRL_DLANES 0x1C4
2935 #define HIVE_SIZE_N_CSI_RX_FE_CTRL_DLANES 12
2939 #define HIVE_MEM_sp_N_CSI_RX_FE_CTRL_DLANES scalar_processor_2400_dmem
2940 #define HIVE_ADDR_sp_N_CSI_RX_FE_CTRL_DLANES 0x1C4
2941 #define HIVE_SIZE_sp_N_CSI_RX_FE_CTRL_DLANES 12
2944 /* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6DC0 */
2946 /* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 700E */
2950 /* function ia_css_ispctrl_sp_done_ds: 40BD */
2952 /* function ia_css_ispctrl_sp_done_ds: 426D */
2956 /* function csi_rx_backend_config: C8B */
2958 /* function csi_rx_backend_config: C85 */
2962 /* function ia_css_sp_isp_param_get_mem_inits: 507E */
2964 /* function ia_css_sp_isp_param_get_mem_inits: 5287 */
2968 /* function ia_css_parambuf_sp_init_buffer_queues: 1A85 */
2970 /* function ia_css_parambuf_sp_init_buffer_queues: 1A27 */
2973 #ifndef HIVE_MULTIPLE_PROGRAMS
2974 #ifndef HIVE_MEM_vbuf_pfp_spref
2975 #define HIVE_MEM_vbuf_pfp_spref scalar_processor_2400_dmem
2977 #define HIVE_ADDR_vbuf_pfp_spref 0x378
2979 #define HIVE_ADDR_vbuf_pfp_spref 0x390
2981 #define HIVE_SIZE_vbuf_pfp_spref 4
2985 #define HIVE_MEM_sp_vbuf_pfp_spref scalar_processor_2400_dmem
2987 #define HIVE_ADDR_sp_vbuf_pfp_spref 0x378
2989 #define HIVE_ADDR_sp_vbuf_pfp_spref 0x390
2991 #define HIVE_SIZE_sp_vbuf_pfp_spref 4
2993 #ifndef HIVE_MULTIPLE_PROGRAMS
2994 #ifndef HIVE_MEM_ISP_HMEM_BASE
2995 #define HIVE_MEM_ISP_HMEM_BASE scalar_processor_2400_dmem
2996 #define HIVE_ADDR_ISP_HMEM_BASE 0x20
2997 #define HIVE_SIZE_ISP_HMEM_BASE 4
3001 #define HIVE_MEM_sp_ISP_HMEM_BASE scalar_processor_2400_dmem
3002 #define HIVE_ADDR_sp_ISP_HMEM_BASE 0x20
3003 #define HIVE_SIZE_sp_ISP_HMEM_BASE 4
3005 #ifndef HIVE_MULTIPLE_PROGRAMS
3006 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_frames
3007 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem
3009 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x6A74
3011 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x6B20
3013 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_frames 280
3017 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem
3019 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x6A74
3021 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x6B20
3023 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_frames 280
3026 /* function qos_scheduler_init_stage_budget: 65A7 */
3028 /* function qos_scheduler_init_stage_budget: 679A */
3031 #ifndef HIVE_MULTIPLE_PROGRAMS
3032 #ifndef HIVE_MEM_sp2host_buffer_queue_handle
3033 #define HIVE_MEM_sp2host_buffer_queue_handle scalar_processor_2400_dmem
3035 #define HIVE_ADDR_sp2host_buffer_queue_handle 0x6B8C
3037 #define HIVE_ADDR_sp2host_buffer_queue_handle 0x6C38
3039 #define HIVE_SIZE_sp2host_buffer_queue_handle 96
3043 #define HIVE_MEM_sp_sp2host_buffer_queue_handle scalar_processor_2400_dmem
3045 #define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x6B8C
3047 #define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x6C38
3049 #define HIVE_SIZE_sp_sp2host_buffer_queue_handle 96
3052 /* function ia_css_ispctrl_sp_init_isp_vars: 4D9D */
3054 /* function ia_css_ispctrl_sp_init_isp_vars: 4F79 */
3058 /* function ia_css_isys_stream_start: 6010 */
3060 /* function ia_css_isys_stream_start: 6187 */
3064 /* function sp_warning: 954 */
3066 /* function sp_warning: 8E8 */
3070 /* function ia_css_rmgr_sp_vbuf_enqueue: 62DC */
3072 /* function ia_css_rmgr_sp_vbuf_enqueue: 64A2 */
3076 /* function ia_css_tagger_sp_tag_exp_id: 2A84 */
3078 /* function ia_css_tagger_sp_tag_exp_id: 2A55 */
3082 /* function ia_css_pipeline_sp_sfi_release_current_frame: 276B */
3084 /* function ia_css_pipeline_sp_sfi_release_current_frame: 273C */
3088 /* function ia_css_dmaproxy_sp_write: 3B21 */
3090 /* function ia_css_dmaproxy_sp_write: 3C81 */
3094 /* function ia_css_isys_stream_start_async: 608A */
3096 /* function ia_css_isys_stream_start_async: 6250 */
3100 /* function ia_css_parambuf_sp_release_in_param: 1905 */
3102 /* function ia_css_parambuf_sp_release_in_param: 187B */
3105 #ifndef HIVE_MULTIPLE_PROGRAMS
3106 #ifndef HIVE_MEM_irq_sw_interrupt_token
3107 #define HIVE_MEM_irq_sw_interrupt_token scalar_processor_2400_dmem
3109 #define HIVE_ADDR_irq_sw_interrupt_token 0x3E28
3111 #define HIVE_ADDR_irq_sw_interrupt_token 0x3E4C
3113 #define HIVE_SIZE_irq_sw_interrupt_token 4
3117 #define HIVE_MEM_sp_irq_sw_interrupt_token scalar_processor_2400_dmem
3119 #define HIVE_ADDR_sp_irq_sw_interrupt_token 0x3E28
3121 #define HIVE_ADDR_sp_irq_sw_interrupt_token 0x3E4C
3123 #define HIVE_SIZE_sp_irq_sw_interrupt_token 4
3125 #ifndef HIVE_MULTIPLE_PROGRAMS
3126 #ifndef HIVE_MEM_sp_isp_addresses
3127 #define HIVE_MEM_sp_isp_addresses scalar_processor_2400_dmem
3129 #define HIVE_ADDR_sp_isp_addresses 0x6FDC
3131 #define HIVE_ADDR_sp_isp_addresses 0x708C
3133 #define HIVE_SIZE_sp_isp_addresses 172
3137 #define HIVE_MEM_sp_sp_isp_addresses scalar_processor_2400_dmem
3139 #define HIVE_ADDR_sp_sp_isp_addresses 0x6FDC
3141 #define HIVE_ADDR_sp_sp_isp_addresses 0x708C
3143 #define HIVE_SIZE_sp_sp_isp_addresses 172
3146 /* function ia_css_rmgr_sp_acq_gen: 6201 */
3148 /* function ia_css_rmgr_sp_acq_gen: 63C7 */
3152 /* function input_system_input_port_open: 10ED */
3154 /* function input_system_input_port_open: 10E7 */
3157 #ifndef HIVE_MULTIPLE_PROGRAMS
3158 #ifndef HIVE_MEM_isps
3159 #define HIVE_MEM_isps scalar_processor_2400_dmem
3161 #define HIVE_ADDR_isps 0x737C
3163 #define HIVE_ADDR_isps 0x7428
3165 #define HIVE_SIZE_isps 28
3169 #define HIVE_MEM_sp_isps scalar_processor_2400_dmem
3171 #define HIVE_ADDR_sp_isps 0x737C
3173 #define HIVE_ADDR_sp_isps 0x7428
3175 #define HIVE_SIZE_sp_isps 28
3177 #ifndef HIVE_MULTIPLE_PROGRAMS
3178 #ifndef HIVE_MEM_host_sp_queues_initialized
3179 #define HIVE_MEM_host_sp_queues_initialized scalar_processor_2400_dmem
3181 #define HIVE_ADDR_host_sp_queues_initialized 0x3E40
3183 #define HIVE_ADDR_host_sp_queues_initialized 0x3E64
3185 #define HIVE_SIZE_host_sp_queues_initialized 4
3189 #define HIVE_MEM_sp_host_sp_queues_initialized scalar_processor_2400_dmem
3191 #define HIVE_ADDR_sp_host_sp_queues_initialized 0x3E40
3193 #define HIVE_ADDR_sp_host_sp_queues_initialized 0x3E64
3195 #define HIVE_SIZE_sp_host_sp_queues_initialized 4
3198 /* function ia_css_queue_uninit: 54E6 */
3200 /* function ia_css_queue_uninit: 56C5 */
3203 #ifndef HIVE_MULTIPLE_PROGRAMS
3204 #ifndef HIVE_MEM_ia_css_ispctrl_sp_isp_started
3205 #define HIVE_MEM_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem
3207 #define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x6C94
3209 #define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x6D40
3211 #define HIVE_SIZE_ia_css_ispctrl_sp_isp_started 4
3215 #define HIVE_MEM_sp_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem
3217 #define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x6C94
3219 #define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x6D40
3221 #define HIVE_SIZE_sp_ia_css_ispctrl_sp_isp_started 4
3224 /* function ia_css_bufq_sp_release_dynamic_buf: 36F2 */
3226 /* function ia_css_bufq_sp_release_dynamic_buf: 3815 */
3230 /* function ia_css_dmaproxy_sp_set_height_exception: 3C19 */
3232 /* function ia_css_dmaproxy_sp_set_height_exception: 3D8E */
3236 /* function ia_css_dmaproxy_sp_init_vmem_channel: 3B9E */
3238 /* function ia_css_dmaproxy_sp_init_vmem_channel: 3CFF */
3242 /* function csi_rx_backend_stop: C57 */
3244 /* function csi_rx_backend_stop: C51 */
3248 #ifndef HIVE_MULTIPLE_PROGRAMS
3249 #ifndef HIVE_MEM_num_ready_threads
3250 #define HIVE_MEM_num_ready_threads scalar_processor_2400_dmem
3251 #define HIVE_ADDR_num_ready_threads 0x5A7C
3252 #define HIVE_SIZE_num_ready_threads 4
3256 #define HIVE_MEM_sp_num_ready_threads scalar_processor_2400_dmem
3257 #define HIVE_ADDR_sp_num_ready_threads 0x5A7C
3258 #define HIVE_SIZE_sp_num_ready_threads 4
3260 /* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 3AF3 */
3262 /* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 3C53 */
3265 #ifndef HIVE_MULTIPLE_PROGRAMS
3266 #ifndef HIVE_MEM_vbuf_spref
3267 #define HIVE_MEM_vbuf_spref scalar_processor_2400_dmem
3269 #define HIVE_ADDR_vbuf_spref 0x374
3271 #define HIVE_ADDR_vbuf_spref 0x38C
3273 #define HIVE_SIZE_vbuf_spref 4
3277 #define HIVE_MEM_sp_vbuf_spref scalar_processor_2400_dmem
3279 #define HIVE_ADDR_sp_vbuf_spref 0x374
3281 #define HIVE_ADDR_sp_vbuf_spref 0x38C
3283 #define HIVE_SIZE_sp_vbuf_spref 4
3286 /* function ia_css_queue_enqueue: 5430 */
3288 /* function ia_css_queue_enqueue: 560F */
3291 #ifndef HIVE_MULTIPLE_PROGRAMS
3292 #ifndef HIVE_MEM_ia_css_flash_sp_request
3293 #define HIVE_MEM_ia_css_flash_sp_request scalar_processor_2400_dmem
3295 #define HIVE_ADDR_ia_css_flash_sp_request 0x5B30
3297 #define HIVE_ADDR_ia_css_flash_sp_request 0x5BDC
3299 #define HIVE_SIZE_ia_css_flash_sp_request 4
3303 #define HIVE_MEM_sp_ia_css_flash_sp_request scalar_processor_2400_dmem
3305 #define HIVE_ADDR_sp_ia_css_flash_sp_request 0x5B30
3307 #define HIVE_ADDR_sp_ia_css_flash_sp_request 0x5BDC
3309 #define HIVE_SIZE_sp_ia_css_flash_sp_request 4
3312 /* function ia_css_dmaproxy_sp_vmem_write: 3AC4 */
3314 /* function ia_css_dmaproxy_sp_vmem_write: 3C24 */
3317 #ifndef HIVE_MULTIPLE_PROGRAMS
3318 #ifndef HIVE_MEM_tagger_frames
3319 #define HIVE_MEM_tagger_frames scalar_processor_2400_dmem
3321 #define HIVE_ADDR_tagger_frames 0x5A84
3323 #define HIVE_ADDR_tagger_frames 0x5B30
3325 #define HIVE_SIZE_tagger_frames 168
3329 #define HIVE_MEM_sp_tagger_frames scalar_processor_2400_dmem
3331 #define HIVE_ADDR_sp_tagger_frames 0x5A84
3333 #define HIVE_ADDR_sp_tagger_frames 0x5B30
3335 #define HIVE_SIZE_sp_tagger_frames 168
3337 #ifndef HIVE_MULTIPLE_PROGRAMS
3338 #ifndef HIVE_MEM_sem_for_reading_if
3339 #define HIVE_MEM_sem_for_reading_if scalar_processor_2400_dmem
3341 #define HIVE_ADDR_sem_for_reading_if 0x58A4
3343 #define HIVE_ADDR_sem_for_reading_if 0x5940
3345 #define HIVE_SIZE_sem_for_reading_if 20
3349 #define HIVE_MEM_sp_sem_for_reading_if scalar_processor_2400_dmem
3351 #define HIVE_ADDR_sp_sem_for_reading_if 0x58A4
3353 #define HIVE_ADDR_sp_sem_for_reading_if 0x5940
3355 #define HIVE_SIZE_sp_sem_for_reading_if 20
3358 /* function sp_generate_interrupts: 9D3 */
3360 /* function sp_generate_interrupts: 967 */
3362 /* function ia_css_pipeline_sp_start: 1FC2 */
3366 /* function ia_css_pipeline_sp_start: 2007 */
3368 /* function ia_css_thread_default_callout: 6C8F */
3372 /* function csi_rx_backend_enable: C45 */
3374 /* function csi_rx_backend_enable: C3F */
3378 /* function ia_css_sp_rawcopy_init: 5953 */
3380 /* function ia_css_sp_rawcopy_init: 5B32 */
3384 /* function input_system_input_port_configure: 113F */
3386 /* function input_system_input_port_configure: 1139 */
3390 /* function tmr_clock_read: 16EF */
3392 /* function tmr_clock_read: 1665 */
3395 #ifndef HIVE_MULTIPLE_PROGRAMS
3396 #ifndef HIVE_MEM_ISP_BAMEM_BASE
3397 #define HIVE_MEM_ISP_BAMEM_BASE scalar_processor_2400_dmem
3399 #define HIVE_ADDR_ISP_BAMEM_BASE 0x380
3401 #define HIVE_ADDR_ISP_BAMEM_BASE 0x398
3403 #define HIVE_SIZE_ISP_BAMEM_BASE 4
3407 #define HIVE_MEM_sp_ISP_BAMEM_BASE scalar_processor_2400_dmem
3409 #define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x380
3411 #define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x398
3413 #define HIVE_SIZE_sp_ISP_BAMEM_BASE 4
3415 #ifndef HIVE_MULTIPLE_PROGRAMS
3416 #ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues
3417 #define HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem
3419 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6BEC
3421 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6C98
3423 #define HIVE_SIZE_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160
3427 #define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem
3429 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6BEC
3431 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6C98
3433 #define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160
3436 /* function isys2401_dma_config_legacy: DE0 */
3438 /* function isys2401_dma_config_legacy: DDA */
3441 #ifndef HIVE_MULTIPLE_PROGRAMS
3442 #ifndef HIVE_MEM_ibuf_ctrl_master_ports
3443 #define HIVE_MEM_ibuf_ctrl_master_ports scalar_processor_2400_dmem
3444 #define HIVE_ADDR_ibuf_ctrl_master_ports 0x208
3445 #define HIVE_SIZE_ibuf_ctrl_master_ports 12
3449 #define HIVE_MEM_sp_ibuf_ctrl_master_ports scalar_processor_2400_dmem
3450 #define HIVE_ADDR_sp_ibuf_ctrl_master_ports 0x208
3451 #define HIVE_SIZE_sp_ibuf_ctrl_master_ports 12
3454 /* function css_get_frame_processing_time_start: 28F1 */
3456 /* function css_get_frame_processing_time_start: 28C2 */
3459 #ifndef HIVE_MULTIPLE_PROGRAMS
3460 #ifndef HIVE_MEM_sp_all_cbs_frame
3461 #define HIVE_MEM_sp_all_cbs_frame scalar_processor_2400_dmem
3463 #define HIVE_ADDR_sp_all_cbs_frame 0x58B8
3465 #define HIVE_ADDR_sp_all_cbs_frame 0x5954
3467 #define HIVE_SIZE_sp_all_cbs_frame 16
3471 #define HIVE_MEM_sp_sp_all_cbs_frame scalar_processor_2400_dmem
3473 #define HIVE_ADDR_sp_sp_all_cbs_frame 0x58B8
3475 #define HIVE_ADDR_sp_sp_all_cbs_frame 0x5954
3477 #define HIVE_SIZE_sp_sp_all_cbs_frame 16
3480 /* function ia_css_virtual_isys_sp_isr: 6F07 */
3482 /* function ia_css_virtual_isys_sp_isr: 716E */
3486 /* function thread_sp_queue_print: 142B */
3488 /* function thread_sp_queue_print: 13A1 */
3492 /* function sp_notify_eof: 97F */
3494 /* function sp_notify_eof: 913 */
3497 #ifndef HIVE_MULTIPLE_PROGRAMS
3498 #ifndef HIVE_MEM_sem_for_str2mem
3499 #define HIVE_MEM_sem_for_str2mem scalar_processor_2400_dmem
3501 #define HIVE_ADDR_sem_for_str2mem 0x58C8
3503 #define HIVE_ADDR_sem_for_str2mem 0x5964
3505 #define HIVE_SIZE_sem_for_str2mem 20
3509 #define HIVE_MEM_sp_sem_for_str2mem scalar_processor_2400_dmem
3511 #define HIVE_ADDR_sp_sem_for_str2mem 0x58C8
3513 #define HIVE_ADDR_sp_sem_for_str2mem 0x5964
3515 #define HIVE_SIZE_sp_sem_for_str2mem 20
3518 /* function ia_css_tagger_buf_sp_is_marked_from_start: 3483 */
3520 /* function ia_css_tagger_buf_sp_is_marked_from_start: 35A6 */
3524 /* function ia_css_bufq_sp_acquire_dynamic_buf: 38AA */
3526 /* function ia_css_bufq_sp_acquire_dynamic_buf: 39CD */
3530 /* function ia_css_pipeline_sp_sfi_mode_is_enabled: 28BF */
3532 /* function ia_css_pipeline_sp_sfi_mode_is_enabled: 2890 */
3536 /* function ia_css_circbuf_destroy: 16B9 */
3538 /* function ia_css_circbuf_destroy: 162F */
3541 #ifndef HIVE_MULTIPLE_PROGRAMS
3542 #ifndef HIVE_MEM_ISP_PMEM_BASE
3543 #define HIVE_MEM_ISP_PMEM_BASE scalar_processor_2400_dmem
3544 #define HIVE_ADDR_ISP_PMEM_BASE 0xC
3545 #define HIVE_SIZE_ISP_PMEM_BASE 4
3549 #define HIVE_MEM_sp_ISP_PMEM_BASE scalar_processor_2400_dmem
3550 #define HIVE_ADDR_sp_ISP_PMEM_BASE 0xC
3551 #define HIVE_SIZE_sp_ISP_PMEM_BASE 4
3554 /* function ia_css_sp_isp_param_mem_load: 5011 */
3556 /* function ia_css_sp_isp_param_mem_load: 521A */
3560 /* function ia_css_tagger_buf_sp_pop_from_start: 326F */
3562 /* function ia_css_tagger_buf_sp_pop_from_start: 3392 */
3566 /* function __div: 681E */
3568 /* function __div: 6A1C */
3572 /* function ia_css_rmgr_sp_refcount_release_vbuf: 62FB */
3574 /* function ia_css_rmgr_sp_refcount_release_vbuf: 64C1 */
3577 #ifndef HIVE_MULTIPLE_PROGRAMS
3578 #ifndef HIVE_MEM_ia_css_flash_sp_in_use
3579 #define HIVE_MEM_ia_css_flash_sp_in_use scalar_processor_2400_dmem
3581 #define HIVE_ADDR_ia_css_flash_sp_in_use 0x5B34
3583 #define HIVE_ADDR_ia_css_flash_sp_in_use 0x5BE0
3585 #define HIVE_SIZE_ia_css_flash_sp_in_use 4
3589 #define HIVE_MEM_sp_ia_css_flash_sp_in_use scalar_processor_2400_dmem
3591 #define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x5B34
3593 #define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x5BE0
3595 #define HIVE_SIZE_sp_ia_css_flash_sp_in_use 4
3598 /* function ia_css_thread_sem_sp_wait: 6AE4 */
3600 /* function ia_css_thread_sem_sp_wait: 6D63 */
3603 #ifndef HIVE_MULTIPLE_PROGRAMS
3604 #ifndef HIVE_MEM_sp_sleep_mode
3605 #define HIVE_MEM_sp_sleep_mode scalar_processor_2400_dmem
3607 #define HIVE_ADDR_sp_sleep_mode 0x3E44
3609 #define HIVE_ADDR_sp_sleep_mode 0x3E68
3611 #define HIVE_SIZE_sp_sleep_mode 4
3615 #define HIVE_MEM_sp_sp_sleep_mode scalar_processor_2400_dmem
3617 #define HIVE_ADDR_sp_sp_sleep_mode 0x3E44
3619 #define HIVE_ADDR_sp_sp_sleep_mode 0x3E68
3621 #define HIVE_SIZE_sp_sp_sleep_mode 4
3624 /* function ia_css_tagger_buf_sp_push: 337E */
3626 /* function ia_css_tagger_buf_sp_push: 34A1 */
3629 /* function mmu_invalidate_cache: D3 */
3631 #ifndef HIVE_MULTIPLE_PROGRAMS
3632 #ifndef HIVE_MEM_sp_max_cb_elems
3633 #define HIVE_MEM_sp_max_cb_elems scalar_processor_2400_dmem
3634 #define HIVE_ADDR_sp_max_cb_elems 0x148
3635 #define HIVE_SIZE_sp_max_cb_elems 8
3639 #define HIVE_MEM_sp_sp_max_cb_elems scalar_processor_2400_dmem
3640 #define HIVE_ADDR_sp_sp_max_cb_elems 0x148
3641 #define HIVE_SIZE_sp_sp_max_cb_elems 8
3644 /* function ia_css_queue_remote_init: 5508 */
3646 /* function ia_css_queue_remote_init: 56E7 */
3649 #ifndef HIVE_MULTIPLE_PROGRAMS
3650 #ifndef HIVE_MEM_isp_stop_req
3651 #define HIVE_MEM_isp_stop_req scalar_processor_2400_dmem
3653 #define HIVE_ADDR_isp_stop_req 0x575C
3655 #define HIVE_ADDR_isp_stop_req 0x57F8
3657 #define HIVE_SIZE_isp_stop_req 4
3661 #define HIVE_MEM_sp_isp_stop_req scalar_processor_2400_dmem
3663 #define HIVE_ADDR_sp_isp_stop_req 0x575C
3665 #define HIVE_ADDR_sp_isp_stop_req 0x57F8
3667 #define HIVE_SIZE_sp_isp_stop_req 4
3670 /* function ia_css_pipeline_sp_sfi_request_next_frame: 2781 */
3672 /* function ia_css_pipeline_sp_sfi_request_next_frame: 2752 */
3676 #define HIVE_ICACHE_sp_critical_SEGMENT_START 0
3677 #define HIVE_ICACHE_sp_critical_NUM_SEGMENTS 1
3680 #endif /* _sp_map_h_ */
3682 extern void sh_css_dump_sp_dmem(void);
3683 void sh_css_dump_sp_dmem(void)