4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/mfd/syscon.h>
35 #include <linux/regmap.h>
36 #include <linux/sizes.h>
38 #include <linux/spi/spi.h>
45 struct completion transfer_complete;
47 /* list synchronization */
48 struct mutex list_lock;
50 struct spi_master *master;
52 void __iomem *mmap_base;
53 struct regmap *ctrl_base;
54 unsigned int ctrl_reg;
58 struct ti_qspi_regs ctx_reg;
60 dma_addr_t mmap_phys_base;
61 dma_addr_t rx_bb_dma_addr;
63 struct dma_chan *rx_chan;
65 u32 spi_max_frequency;
72 #define QSPI_PID (0x0)
73 #define QSPI_SYSCONFIG (0x10)
74 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
75 #define QSPI_SPI_DC_REG (0x44)
76 #define QSPI_SPI_CMD_REG (0x48)
77 #define QSPI_SPI_STATUS_REG (0x4c)
78 #define QSPI_SPI_DATA_REG (0x50)
79 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
80 #define QSPI_SPI_SWITCH_REG (0x64)
81 #define QSPI_SPI_DATA_REG_1 (0x68)
82 #define QSPI_SPI_DATA_REG_2 (0x6c)
83 #define QSPI_SPI_DATA_REG_3 (0x70)
85 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
87 #define QSPI_FCLK 192000000
90 #define QSPI_CLK_EN (1 << 31)
91 #define QSPI_CLK_DIV_MAX 0xffff
94 #define QSPI_EN_CS(n) (n << 28)
95 #define QSPI_WLEN(n) ((n - 1) << 19)
96 #define QSPI_3_PIN (1 << 18)
97 #define QSPI_RD_SNGL (1 << 16)
98 #define QSPI_WR_SNGL (2 << 16)
99 #define QSPI_RD_DUAL (3 << 16)
100 #define QSPI_RD_QUAD (7 << 16)
101 #define QSPI_INVAL (4 << 16)
102 #define QSPI_FLEN(n) ((n - 1) << 0)
103 #define QSPI_WLEN_MAX_BITS 128
104 #define QSPI_WLEN_MAX_BYTES 16
105 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
107 /* STATUS REGISTER */
112 #define QSPI_DD(m, n) (m << (3 + n * 8))
113 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
114 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
115 #define QSPI_CKPOL(n) (1 << (n * 8))
117 #define QSPI_FRAME 4096
119 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
121 #define MEM_CS_EN(n) ((n + 1) << 8)
122 #define MEM_CS_MASK (7 << 8)
124 #define MM_SWITCH 0x1
126 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
127 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
128 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
129 #define QSPI_SETUP_ADDR_SHIFT 8
130 #define QSPI_SETUP_DUMMY_SHIFT 10
132 #define QSPI_DMA_BUFFER_SIZE SZ_64K
134 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
137 return readl(qspi->base + reg);
140 static inline void ti_qspi_write(struct ti_qspi *qspi,
141 unsigned long val, unsigned long reg)
143 writel(val, qspi->base + reg);
146 static int ti_qspi_setup(struct spi_device *spi)
148 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
149 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
150 int clk_div = 0, ret;
151 u32 clk_ctrl_reg, clk_rate, clk_mask;
153 if (spi->master->busy) {
154 dev_dbg(qspi->dev, "master busy doing other transfers\n");
158 if (!qspi->spi_max_frequency) {
159 dev_err(qspi->dev, "spi max frequency not defined\n");
163 clk_rate = clk_get_rate(qspi->fclk);
165 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
168 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
172 if (clk_div > QSPI_CLK_DIV_MAX) {
173 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
174 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
178 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
179 qspi->spi_max_frequency, clk_div);
181 ret = pm_runtime_get_sync(qspi->dev);
183 pm_runtime_put_noidle(qspi->dev);
184 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
188 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
190 clk_ctrl_reg &= ~QSPI_CLK_EN;
193 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
196 clk_mask = QSPI_CLK_EN | clk_div;
197 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
198 ctx_reg->clkctrl = clk_mask;
200 pm_runtime_mark_last_busy(qspi->dev);
201 ret = pm_runtime_put_autosuspend(qspi->dev);
203 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
210 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
212 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
214 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
217 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
220 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
222 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
223 while ((stat & BUSY) && time_after(timeout, jiffies)) {
225 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
228 WARN(stat & BUSY, "qspi busy\n");
232 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
235 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
238 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
242 } while (time_after(timeout, jiffies));
244 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
250 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
259 cmd = qspi->cmd | QSPI_WR_SNGL;
260 wlen = t->bits_per_word >> 3; /* in bytes */
264 if (qspi_is_busy(qspi))
269 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
270 cmd, qspi->dc, *txbuf);
271 if (count >= QSPI_WLEN_MAX_BYTES) {
272 u32 *txp = (u32 *)txbuf;
274 data = cpu_to_be32(*txp++);
275 writel(data, qspi->base +
276 QSPI_SPI_DATA_REG_3);
277 data = cpu_to_be32(*txp++);
278 writel(data, qspi->base +
279 QSPI_SPI_DATA_REG_2);
280 data = cpu_to_be32(*txp++);
281 writel(data, qspi->base +
282 QSPI_SPI_DATA_REG_1);
283 data = cpu_to_be32(*txp++);
284 writel(data, qspi->base +
286 xfer_len = QSPI_WLEN_MAX_BYTES;
287 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
289 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
290 cmd = qspi->cmd | QSPI_WR_SNGL;
292 cmd |= QSPI_WLEN(wlen);
296 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
297 cmd, qspi->dc, *txbuf);
298 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
301 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
302 cmd, qspi->dc, *txbuf);
303 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
307 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
308 if (ti_qspi_poll_wc(qspi)) {
309 dev_err(qspi->dev, "write timed out\n");
319 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
328 switch (t->rx_nbits) {
339 wlen = t->bits_per_word >> 3; /* in bytes */
342 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
343 if (qspi_is_busy(qspi))
346 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
347 if (ti_qspi_poll_wc(qspi)) {
348 dev_err(qspi->dev, "read timed out\n");
353 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
356 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
359 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
369 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
375 ret = qspi_write_msg(qspi, t, count);
377 dev_dbg(qspi->dev, "Error while writing\n");
383 ret = qspi_read_msg(qspi, t, count);
385 dev_dbg(qspi->dev, "Error while reading\n");
393 static void ti_qspi_dma_callback(void *param)
395 struct ti_qspi *qspi = param;
397 complete(&qspi->transfer_complete);
400 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
401 dma_addr_t dma_src, size_t len)
403 struct dma_chan *chan = qspi->rx_chan;
405 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
406 struct dma_async_tx_descriptor *tx;
409 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
411 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
415 tx->callback = ti_qspi_dma_callback;
416 tx->callback_param = qspi;
417 cookie = tx->tx_submit(tx);
418 reinit_completion(&qspi->transfer_complete);
420 ret = dma_submit_error(cookie);
422 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
426 dma_async_issue_pending(chan);
427 ret = wait_for_completion_timeout(&qspi->transfer_complete,
428 msecs_to_jiffies(len));
430 dmaengine_terminate_sync(chan);
431 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
438 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi,
439 struct spi_flash_read_message *msg)
441 size_t readsize = msg->len;
443 dma_addr_t dma_src = qspi->mmap_phys_base + msg->from;
447 * Use bounce buffer as FS like jffs2, ubifs may pass
448 * buffers that does not belong to kernel lowmem region.
450 while (readsize != 0) {
451 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
454 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
458 memcpy(to, qspi->rx_bb_addr, xfer_len);
459 readsize -= xfer_len;
467 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
470 struct scatterlist *sg;
471 dma_addr_t dma_src = qspi->mmap_phys_base + from;
475 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
476 dma_dst = sg_dma_address(sg);
477 len = sg_dma_len(sg);
478 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
487 static void ti_qspi_enable_memory_map(struct spi_device *spi)
489 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
491 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
492 if (qspi->ctrl_base) {
493 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
495 MEM_CS_EN(spi->chip_select));
497 qspi->mmap_enabled = true;
500 static void ti_qspi_disable_memory_map(struct spi_device *spi)
502 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
504 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
506 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
508 qspi->mmap_enabled = false;
511 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
512 struct spi_flash_read_message *msg)
514 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
515 u32 memval = msg->read_opcode;
517 switch (msg->data_nbits) {
519 memval |= QSPI_SETUP_RD_QUAD;
522 memval |= QSPI_SETUP_RD_DUAL;
525 memval |= QSPI_SETUP_RD_NORMAL;
528 memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
529 msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
530 ti_qspi_write(qspi, memval,
531 QSPI_SPI_SETUP_REG(spi->chip_select));
534 static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi,
535 struct spi_flash_read_message *msg)
537 return virt_addr_valid(msg->buf);
540 static int ti_qspi_spi_flash_read(struct spi_device *spi,
541 struct spi_flash_read_message *msg)
543 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
546 mutex_lock(&qspi->list_lock);
548 if (!qspi->mmap_enabled)
549 ti_qspi_enable_memory_map(spi);
550 ti_qspi_setup_mmap_read(spi, msg);
553 if (msg->cur_msg_mapped)
554 ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
556 ret = ti_qspi_dma_bounce_buffer(qspi, msg);
560 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
562 msg->retlen = msg->len;
565 mutex_unlock(&qspi->list_lock);
570 static int ti_qspi_start_transfer_one(struct spi_master *master,
571 struct spi_message *m)
573 struct ti_qspi *qspi = spi_master_get_devdata(master);
574 struct spi_device *spi = m->spi;
575 struct spi_transfer *t;
577 unsigned int frame_len_words, transfer_len_words;
580 /* setup device control reg */
583 if (spi->mode & SPI_CPHA)
584 qspi->dc |= QSPI_CKPHA(spi->chip_select);
585 if (spi->mode & SPI_CPOL)
586 qspi->dc |= QSPI_CKPOL(spi->chip_select);
587 if (spi->mode & SPI_CS_HIGH)
588 qspi->dc |= QSPI_CSPOL(spi->chip_select);
591 list_for_each_entry(t, &m->transfers, transfer_list)
592 frame_len_words += t->len / (t->bits_per_word >> 3);
593 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
595 /* setup command reg */
597 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
598 qspi->cmd |= QSPI_FLEN(frame_len_words);
600 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
602 mutex_lock(&qspi->list_lock);
604 if (qspi->mmap_enabled)
605 ti_qspi_disable_memory_map(spi);
607 list_for_each_entry(t, &m->transfers, transfer_list) {
608 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
609 QSPI_WLEN(t->bits_per_word));
611 wlen = t->bits_per_word >> 3;
612 transfer_len_words = min(t->len / wlen, frame_len_words);
614 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
616 dev_dbg(qspi->dev, "transfer message failed\n");
617 mutex_unlock(&qspi->list_lock);
621 m->actual_length += transfer_len_words * wlen;
622 frame_len_words -= transfer_len_words;
623 if (frame_len_words == 0)
627 mutex_unlock(&qspi->list_lock);
629 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
631 spi_finalize_current_message(master);
636 static int ti_qspi_runtime_resume(struct device *dev)
638 struct ti_qspi *qspi;
640 qspi = dev_get_drvdata(dev);
641 ti_qspi_restore_ctx(qspi);
646 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
648 if (qspi->rx_bb_addr)
649 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
651 qspi->rx_bb_dma_addr);
654 dma_release_channel(qspi->rx_chan);
657 static const struct of_device_id ti_qspi_match[] = {
658 {.compatible = "ti,dra7xxx-qspi" },
659 {.compatible = "ti,am4372-qspi" },
662 MODULE_DEVICE_TABLE(of, ti_qspi_match);
664 static int ti_qspi_probe(struct platform_device *pdev)
666 struct ti_qspi *qspi;
667 struct spi_master *master;
668 struct resource *r, *res_mmap;
669 struct device_node *np = pdev->dev.of_node;
671 int ret = 0, num_cs, irq;
674 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
678 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
680 master->flags = SPI_MASTER_HALF_DUPLEX;
681 master->setup = ti_qspi_setup;
682 master->auto_runtime_pm = true;
683 master->transfer_one_message = ti_qspi_start_transfer_one;
684 master->dev.of_node = pdev->dev.of_node;
685 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
687 master->spi_flash_read = ti_qspi_spi_flash_read;
689 if (!of_property_read_u32(np, "num-cs", &num_cs))
690 master->num_chipselect = num_cs;
692 qspi = spi_master_get_devdata(master);
693 qspi->master = master;
694 qspi->dev = &pdev->dev;
695 platform_set_drvdata(pdev, qspi);
697 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
699 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701 dev_err(&pdev->dev, "missing platform data\n");
707 res_mmap = platform_get_resource_byname(pdev,
708 IORESOURCE_MEM, "qspi_mmap");
709 if (res_mmap == NULL) {
710 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
711 if (res_mmap == NULL) {
713 "memory mapped resource not required\n");
717 irq = platform_get_irq(pdev, 0);
719 dev_err(&pdev->dev, "no irq resource?\n");
724 mutex_init(&qspi->list_lock);
726 qspi->base = devm_ioremap_resource(&pdev->dev, r);
727 if (IS_ERR(qspi->base)) {
728 ret = PTR_ERR(qspi->base);
733 if (of_property_read_bool(np, "syscon-chipselects")) {
735 syscon_regmap_lookup_by_phandle(np,
736 "syscon-chipselects");
737 if (IS_ERR(qspi->ctrl_base)) {
738 ret = PTR_ERR(qspi->ctrl_base);
741 ret = of_property_read_u32_index(np,
742 "syscon-chipselects",
746 "couldn't get ctrl_mod reg index\n");
751 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
752 if (IS_ERR(qspi->fclk)) {
753 ret = PTR_ERR(qspi->fclk);
754 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
757 pm_runtime_use_autosuspend(&pdev->dev);
758 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
759 pm_runtime_enable(&pdev->dev);
761 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
762 qspi->spi_max_frequency = max_freq;
765 dma_cap_set(DMA_MEMCPY, mask);
767 qspi->rx_chan = dma_request_chan_by_mask(&mask);
768 if (IS_ERR(qspi->rx_chan)) {
770 "No Rx DMA available, trying mmap mode\n");
771 qspi->rx_chan = NULL;
775 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
776 QSPI_DMA_BUFFER_SIZE,
777 &qspi->rx_bb_dma_addr,
778 GFP_KERNEL | GFP_DMA);
779 if (!qspi->rx_bb_addr) {
781 "dma_alloc_coherent failed, using PIO mode\n");
782 dma_release_channel(qspi->rx_chan);
785 master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma;
786 master->dma_rx = qspi->rx_chan;
787 init_completion(&qspi->transfer_complete);
789 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
792 if (!qspi->rx_chan && res_mmap) {
793 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
794 if (IS_ERR(qspi->mmap_base)) {
796 "mmap failed with error %ld using PIO mode\n",
797 PTR_ERR(qspi->mmap_base));
798 qspi->mmap_base = NULL;
799 master->spi_flash_read = NULL;
802 qspi->mmap_enabled = false;
804 ret = devm_spi_register_master(&pdev->dev, master);
808 ti_qspi_dma_cleanup(qspi);
810 pm_runtime_disable(&pdev->dev);
812 spi_master_put(master);
816 static int ti_qspi_remove(struct platform_device *pdev)
818 struct ti_qspi *qspi = platform_get_drvdata(pdev);
821 rc = spi_master_suspend(qspi->master);
825 pm_runtime_put_sync(&pdev->dev);
826 pm_runtime_disable(&pdev->dev);
828 ti_qspi_dma_cleanup(qspi);
833 static const struct dev_pm_ops ti_qspi_pm_ops = {
834 .runtime_resume = ti_qspi_runtime_resume,
837 static struct platform_driver ti_qspi_driver = {
838 .probe = ti_qspi_probe,
839 .remove = ti_qspi_remove,
842 .pm = &ti_qspi_pm_ops,
843 .of_match_table = ti_qspi_match,
847 module_platform_driver(ti_qspi_driver);
849 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
850 MODULE_LICENSE("GPL v2");
851 MODULE_DESCRIPTION("TI QSPI controller driver");
852 MODULE_ALIAS("platform:ti-qspi");