2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/clk.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/acpi.h>
37 #include "spi-pxa2xx.h"
39 MODULE_AUTHOR("Stephen Street");
40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41 MODULE_LICENSE("GPL");
42 MODULE_ALIAS("platform:pxa2xx-spi");
44 #define TIMOUT_DFLT 1000
47 * for testing SSCR1 changes that require SSP restart, basically
48 * everything except the service and interrupt enables, the pxa270 developer
49 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
50 * list, but the PXA255 dev man says all bits without really meaning the
51 * service and interrupt enables
53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
54 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
55 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
56 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
57 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
61 | QUARK_X1000_SSCR1_EFWR \
62 | QUARK_X1000_SSCR1_RFT \
63 | QUARK_X1000_SSCR1_TFT \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
67 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
68 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
69 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
70 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
73 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
74 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
75 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
76 #define LPSS_CAPS_CS_EN_SHIFT 9
77 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
79 #define LPSS_PRIV_CLOCK_GATE 0x38
80 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
81 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
84 /* LPSS offset from drv_data->ioaddr */
86 /* Register offsets from drv_data->lpss_base or -1 */
95 /* Chip select control */
96 unsigned cs_sel_shift;
100 unsigned cs_clk_stays_gated : 1;
103 /* Keep these sorted with enum pxa_ssp_type */
104 static const struct lpss_config lpss_platforms[] = {
110 .reg_capabilities = -1,
112 .tx_threshold_lo = 160,
113 .tx_threshold_hi = 224,
120 .reg_capabilities = -1,
122 .tx_threshold_lo = 160,
123 .tx_threshold_hi = 224,
130 .reg_capabilities = -1,
132 .tx_threshold_lo = 160,
133 .tx_threshold_hi = 224,
135 .cs_sel_mask = 1 << 2,
143 .reg_capabilities = -1,
145 .tx_threshold_lo = 32,
146 .tx_threshold_hi = 56,
153 .reg_capabilities = 0xfc,
155 .tx_threshold_lo = 16,
156 .tx_threshold_hi = 48,
158 .cs_sel_mask = 3 << 8,
159 .cs_clk_stays_gated = true,
166 .reg_capabilities = 0xfc,
168 .tx_threshold_lo = 32,
169 .tx_threshold_hi = 56,
171 .cs_sel_mask = 3 << 8,
172 .cs_clk_stays_gated = true,
176 static inline const struct lpss_config
177 *lpss_get_config(const struct driver_data *drv_data)
179 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
182 static bool is_lpss_ssp(const struct driver_data *drv_data)
184 switch (drv_data->ssp_type) {
197 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
199 return drv_data->ssp_type == QUARK_X1000_SSP;
202 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
204 switch (drv_data->ssp_type) {
205 case QUARK_X1000_SSP:
206 return QUARK_X1000_SSCR1_CHANGE_MASK;
208 return CE4100_SSCR1_CHANGE_MASK;
210 return SSCR1_CHANGE_MASK;
215 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
217 switch (drv_data->ssp_type) {
218 case QUARK_X1000_SSP:
219 return RX_THRESH_QUARK_X1000_DFLT;
221 return RX_THRESH_CE4100_DFLT;
223 return RX_THRESH_DFLT;
227 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
231 switch (drv_data->ssp_type) {
232 case QUARK_X1000_SSP:
233 mask = QUARK_X1000_SSSR_TFL_MASK;
236 mask = CE4100_SSSR_TFL_MASK;
239 mask = SSSR_TFL_MASK;
243 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
246 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
251 switch (drv_data->ssp_type) {
252 case QUARK_X1000_SSP:
253 mask = QUARK_X1000_SSCR1_RFT;
256 mask = CE4100_SSCR1_RFT;
265 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
266 u32 *sccr1_reg, u32 threshold)
268 switch (drv_data->ssp_type) {
269 case QUARK_X1000_SSP:
270 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
273 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
276 *sccr1_reg |= SSCR1_RxTresh(threshold);
281 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
282 u32 clk_div, u8 bits)
284 switch (drv_data->ssp_type) {
285 case QUARK_X1000_SSP:
287 | QUARK_X1000_SSCR0_Motorola
288 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
293 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
295 | (bits > 16 ? SSCR0_EDSS : 0);
300 * Read and write LPSS SSP private registers. Caller must first check that
301 * is_lpss_ssp() returns true before these can be called.
303 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
305 WARN_ON(!drv_data->lpss_base);
306 return readl(drv_data->lpss_base + offset);
309 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
310 unsigned offset, u32 value)
312 WARN_ON(!drv_data->lpss_base);
313 writel(value, drv_data->lpss_base + offset);
317 * lpss_ssp_setup - perform LPSS SSP specific setup
318 * @drv_data: pointer to the driver private data
320 * Perform LPSS SSP specific setup. This function must be called first if
321 * one is going to use LPSS SSP private registers.
323 static void lpss_ssp_setup(struct driver_data *drv_data)
325 const struct lpss_config *config;
328 config = lpss_get_config(drv_data);
329 drv_data->lpss_base = drv_data->ioaddr + config->offset;
331 /* Enable software chip select control */
332 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
333 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
334 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
335 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
337 /* Enable multiblock DMA transfers */
338 if (drv_data->master_info->enable_dma) {
339 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
341 if (config->reg_general >= 0) {
342 value = __lpss_ssp_read_priv(drv_data,
343 config->reg_general);
344 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
345 __lpss_ssp_write_priv(drv_data,
346 config->reg_general, value);
351 static void lpss_ssp_select_cs(struct driver_data *drv_data,
352 const struct lpss_config *config)
356 if (!config->cs_sel_mask)
359 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
361 cs = drv_data->master->cur_msg->spi->chip_select;
362 cs <<= config->cs_sel_shift;
363 if (cs != (value & config->cs_sel_mask)) {
365 * When switching another chip select output active the
366 * output must be selected first and wait 2 ssp_clk cycles
367 * before changing state to active. Otherwise a short
368 * glitch will occur on the previous chip select since
369 * output select is latched but state control is not.
371 value &= ~config->cs_sel_mask;
373 __lpss_ssp_write_priv(drv_data,
374 config->reg_cs_ctrl, value);
376 (drv_data->master->max_speed_hz / 2));
380 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
382 const struct lpss_config *config;
385 config = lpss_get_config(drv_data);
388 lpss_ssp_select_cs(drv_data, config);
390 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
392 value &= ~LPSS_CS_CONTROL_CS_HIGH;
394 value |= LPSS_CS_CONTROL_CS_HIGH;
395 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
396 if (config->cs_clk_stays_gated) {
400 * Changing CS alone when dynamic clock gating is on won't
401 * actually flip CS at that time. This ruins SPI transfers
402 * that specify delays, or have no data. Toggle the clock mode
403 * to force on briefly to poke the CS pin to move.
405 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
406 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
407 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
409 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
410 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
414 static void cs_assert(struct driver_data *drv_data)
416 struct chip_data *chip =
417 spi_get_ctldata(drv_data->master->cur_msg->spi);
419 if (drv_data->ssp_type == CE4100_SSP) {
420 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
424 if (chip->cs_control) {
425 chip->cs_control(PXA2XX_CS_ASSERT);
429 if (chip->gpiod_cs) {
430 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
434 if (is_lpss_ssp(drv_data))
435 lpss_ssp_cs_control(drv_data, true);
438 static void cs_deassert(struct driver_data *drv_data)
440 struct chip_data *chip =
441 spi_get_ctldata(drv_data->master->cur_msg->spi);
443 if (drv_data->ssp_type == CE4100_SSP)
446 if (chip->cs_control) {
447 chip->cs_control(PXA2XX_CS_DEASSERT);
451 if (chip->gpiod_cs) {
452 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
456 if (is_lpss_ssp(drv_data))
457 lpss_ssp_cs_control(drv_data, false);
460 int pxa2xx_spi_flush(struct driver_data *drv_data)
462 unsigned long limit = loops_per_jiffy << 1;
465 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
466 pxa2xx_spi_read(drv_data, SSDR);
467 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
468 write_SSSR_CS(drv_data, SSSR_ROR);
473 static int null_writer(struct driver_data *drv_data)
475 u8 n_bytes = drv_data->n_bytes;
477 if (pxa2xx_spi_txfifo_full(drv_data)
478 || (drv_data->tx == drv_data->tx_end))
481 pxa2xx_spi_write(drv_data, SSDR, 0);
482 drv_data->tx += n_bytes;
487 static int null_reader(struct driver_data *drv_data)
489 u8 n_bytes = drv_data->n_bytes;
491 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
492 && (drv_data->rx < drv_data->rx_end)) {
493 pxa2xx_spi_read(drv_data, SSDR);
494 drv_data->rx += n_bytes;
497 return drv_data->rx == drv_data->rx_end;
500 static int u8_writer(struct driver_data *drv_data)
502 if (pxa2xx_spi_txfifo_full(drv_data)
503 || (drv_data->tx == drv_data->tx_end))
506 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
512 static int u8_reader(struct driver_data *drv_data)
514 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
515 && (drv_data->rx < drv_data->rx_end)) {
516 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
520 return drv_data->rx == drv_data->rx_end;
523 static int u16_writer(struct driver_data *drv_data)
525 if (pxa2xx_spi_txfifo_full(drv_data)
526 || (drv_data->tx == drv_data->tx_end))
529 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
535 static int u16_reader(struct driver_data *drv_data)
537 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
538 && (drv_data->rx < drv_data->rx_end)) {
539 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
543 return drv_data->rx == drv_data->rx_end;
546 static int u32_writer(struct driver_data *drv_data)
548 if (pxa2xx_spi_txfifo_full(drv_data)
549 || (drv_data->tx == drv_data->tx_end))
552 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
558 static int u32_reader(struct driver_data *drv_data)
560 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
561 && (drv_data->rx < drv_data->rx_end)) {
562 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
566 return drv_data->rx == drv_data->rx_end;
569 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
571 struct spi_message *msg = drv_data->master->cur_msg;
572 struct spi_transfer *trans = drv_data->cur_transfer;
574 /* Move to next transfer */
575 if (trans->transfer_list.next != &msg->transfers) {
576 drv_data->cur_transfer =
577 list_entry(trans->transfer_list.next,
580 return RUNNING_STATE;
585 /* caller already set message->status; dma and pio irqs are blocked */
586 static void giveback(struct driver_data *drv_data)
588 struct spi_transfer* last_transfer;
589 struct spi_message *msg;
590 unsigned long timeout;
592 msg = drv_data->master->cur_msg;
593 drv_data->cur_transfer = NULL;
595 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
598 /* Delay if requested before any change in chip select */
599 if (last_transfer->delay_usecs)
600 udelay(last_transfer->delay_usecs);
602 /* Wait until SSP becomes idle before deasserting the CS */
603 timeout = jiffies + msecs_to_jiffies(10);
604 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
605 !time_after(jiffies, timeout))
608 /* Drop chip select UNLESS cs_change is true or we are returning
609 * a message with an error, or next message is for another chip
611 if (!last_transfer->cs_change)
612 cs_deassert(drv_data);
614 struct spi_message *next_msg;
616 /* Holding of cs was hinted, but we need to make sure
617 * the next message is for the same chip. Don't waste
618 * time with the following tests unless this was hinted.
620 * We cannot postpone this until pump_messages, because
621 * after calling msg->complete (below) the driver that
622 * sent the current message could be unloaded, which
623 * could invalidate the cs_control() callback...
626 /* get a pointer to the next message, if any */
627 next_msg = spi_get_next_queued_message(drv_data->master);
629 /* see if the next and current messages point
632 if ((next_msg && next_msg->spi != msg->spi) ||
633 msg->state == ERROR_STATE)
634 cs_deassert(drv_data);
637 spi_finalize_current_message(drv_data->master);
640 static void reset_sccr1(struct driver_data *drv_data)
642 struct chip_data *chip =
643 spi_get_ctldata(drv_data->master->cur_msg->spi);
646 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
647 switch (drv_data->ssp_type) {
648 case QUARK_X1000_SSP:
649 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
652 sccr1_reg &= ~CE4100_SSCR1_RFT;
655 sccr1_reg &= ~SSCR1_RFT;
658 sccr1_reg |= chip->threshold;
659 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
662 static void int_error_stop(struct driver_data *drv_data, const char* msg)
664 /* Stop and reset SSP */
665 write_SSSR_CS(drv_data, drv_data->clear_sr);
666 reset_sccr1(drv_data);
667 if (!pxa25x_ssp_comp(drv_data))
668 pxa2xx_spi_write(drv_data, SSTO, 0);
669 pxa2xx_spi_flush(drv_data);
670 pxa2xx_spi_write(drv_data, SSCR0,
671 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
673 dev_err(&drv_data->pdev->dev, "%s\n", msg);
675 drv_data->master->cur_msg->state = ERROR_STATE;
676 tasklet_schedule(&drv_data->pump_transfers);
679 static void int_transfer_complete(struct driver_data *drv_data)
681 /* Clear and disable interrupts */
682 write_SSSR_CS(drv_data, drv_data->clear_sr);
683 reset_sccr1(drv_data);
684 if (!pxa25x_ssp_comp(drv_data))
685 pxa2xx_spi_write(drv_data, SSTO, 0);
687 /* Update total byte transferred return count actual bytes read */
688 drv_data->master->cur_msg->actual_length += drv_data->len -
689 (drv_data->rx_end - drv_data->rx);
691 /* Transfer delays and chip select release are
692 * handled in pump_transfers or giveback
695 /* Move to next transfer */
696 drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
698 /* Schedule transfer tasklet */
699 tasklet_schedule(&drv_data->pump_transfers);
702 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
704 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
705 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
707 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
709 if (irq_status & SSSR_ROR) {
710 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
714 if (irq_status & SSSR_TINT) {
715 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
716 if (drv_data->read(drv_data)) {
717 int_transfer_complete(drv_data);
722 /* Drain rx fifo, Fill tx fifo and prevent overruns */
724 if (drv_data->read(drv_data)) {
725 int_transfer_complete(drv_data);
728 } while (drv_data->write(drv_data));
730 if (drv_data->read(drv_data)) {
731 int_transfer_complete(drv_data);
735 if (drv_data->tx == drv_data->tx_end) {
739 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
740 sccr1_reg &= ~SSCR1_TIE;
743 * PXA25x_SSP has no timeout, set up rx threshould for the
744 * remaining RX bytes.
746 if (pxa25x_ssp_comp(drv_data)) {
749 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
751 bytes_left = drv_data->rx_end - drv_data->rx;
752 switch (drv_data->n_bytes) {
759 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
760 if (rx_thre > bytes_left)
761 rx_thre = bytes_left;
763 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
765 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
768 /* We did something */
772 static void handle_bad_msg(struct driver_data *drv_data)
774 pxa2xx_spi_write(drv_data, SSCR0,
775 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
776 pxa2xx_spi_write(drv_data, SSCR1,
777 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
778 if (!pxa25x_ssp_comp(drv_data))
779 pxa2xx_spi_write(drv_data, SSTO, 0);
780 write_SSSR_CS(drv_data, drv_data->clear_sr);
782 dev_err(&drv_data->pdev->dev,
783 "bad message state in interrupt handler\n");
786 static irqreturn_t ssp_int(int irq, void *dev_id)
788 struct driver_data *drv_data = dev_id;
790 u32 mask = drv_data->mask_sr;
794 * The IRQ might be shared with other peripherals so we must first
795 * check that are we RPM suspended or not. If we are we assume that
796 * the IRQ was not for us (we shouldn't be RPM suspended when the
797 * interrupt is enabled).
799 if (pm_runtime_suspended(&drv_data->pdev->dev))
803 * If the device is not yet in RPM suspended state and we get an
804 * interrupt that is meant for another device, check if status bits
805 * are all set to one. That means that the device is already
808 status = pxa2xx_spi_read(drv_data, SSSR);
812 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
814 /* Ignore possible writes if we don't need to write */
815 if (!(sccr1_reg & SSCR1_TIE))
818 /* Ignore RX timeout interrupt if it is disabled */
819 if (!(sccr1_reg & SSCR1_TINTE))
822 if (!(status & mask))
825 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
826 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
828 if (!drv_data->master->cur_msg) {
829 handle_bad_msg(drv_data);
834 return drv_data->transfer_handler(drv_data);
838 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
839 * input frequency by fractions of 2^24. It also has a divider by 5.
841 * There are formulas to get baud rate value for given input frequency and
842 * divider parameters, such as DDS_CLK_RATE and SCR:
846 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
847 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
849 * DDS_CLK_RATE either 2^n or 2^n / 5.
850 * SCR is in range 0 .. 255
852 * Divisor = 5^i * 2^j * 2 * k
853 * i = [0, 1] i = 1 iff j = 0 or j > 3
854 * j = [0, 23] j = 0 iff i = 1
856 * Special case: j = 0, i = 1: Divisor = 2 / 5
858 * Accordingly to the specification the recommended values for DDS_CLK_RATE
860 * Case 1: 2^n, n = [0, 23]
861 * Case 2: 2^24 * 2 / 5 (0x666666)
862 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
864 * In all cases the lowest possible value is better.
866 * The function calculates parameters for all cases and chooses the one closest
867 * to the asked baud rate.
869 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
871 unsigned long xtal = 200000000;
872 unsigned long fref = xtal / 2; /* mandatory division by 2,
875 unsigned long fref1 = fref / 2; /* case 1 */
876 unsigned long fref2 = fref * 2 / 5; /* case 2 */
878 unsigned long q, q1, q2;
884 /* Set initial value for DDS_CLK_RATE */
885 mul = (1 << 24) >> 1;
887 /* Calculate initial quot */
888 q1 = DIV_ROUND_UP(fref1, rate);
890 /* Scale q1 if it's too big */
892 /* Scale q1 to range [1, 512] */
893 scale = fls_long(q1 - 1);
899 /* Round the result if we have a remainder */
903 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
908 /* Get the remainder */
909 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
913 q2 = DIV_ROUND_UP(fref2, rate);
914 r2 = abs(fref2 / q2 - rate);
917 * Choose the best between two: less remainder we have the better. We
918 * can't go case 2 if q2 is greater than 256 since SCR register can
919 * hold only values 0 .. 255.
921 if (r2 >= r1 || q2 > 256) {
922 /* case 1 is better */
926 /* case 2 is better */
929 mul = (1 << 24) * 2 / 5;
932 /* Check case 3 only if the divisor is big enough */
933 if (fref / rate >= 80) {
937 /* Calculate initial quot */
938 q1 = DIV_ROUND_UP(fref, rate);
941 /* Get the remainder */
942 fssp = (u64)fref * m;
943 do_div(fssp, 1 << 24);
944 r1 = abs(fssp - rate);
946 /* Choose this one if it suits better */
948 /* case 3 is better */
958 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
960 unsigned long ssp_clk = drv_data->master->max_speed_hz;
961 const struct ssp_device *ssp = drv_data->ssp;
963 rate = min_t(int, ssp_clk, rate);
966 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
967 * that the SSP transmission rate can be greater than the device rate
969 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
970 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
972 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
975 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
978 struct chip_data *chip =
979 spi_get_ctldata(drv_data->master->cur_msg->spi);
980 unsigned int clk_div;
982 switch (drv_data->ssp_type) {
983 case QUARK_X1000_SSP:
984 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
987 clk_div = ssp_get_clk_div(drv_data, rate);
993 static bool pxa2xx_spi_can_dma(struct spi_master *master,
994 struct spi_device *spi,
995 struct spi_transfer *xfer)
997 struct chip_data *chip = spi_get_ctldata(spi);
999 return chip->enable_dma &&
1000 xfer->len <= MAX_DMA_LEN &&
1001 xfer->len >= chip->dma_burst_size;
1004 static void pump_transfers(unsigned long data)
1006 struct driver_data *drv_data = (struct driver_data *)data;
1007 struct spi_master *master = drv_data->master;
1008 struct spi_message *message = master->cur_msg;
1009 struct chip_data *chip = spi_get_ctldata(message->spi);
1010 u32 dma_thresh = chip->dma_threshold;
1011 u32 dma_burst = chip->dma_burst_size;
1012 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
1013 struct spi_transfer *transfer;
1014 struct spi_transfer *previous;
1023 /* Get current state information */
1024 transfer = drv_data->cur_transfer;
1026 /* Handle for abort */
1027 if (message->state == ERROR_STATE) {
1028 message->status = -EIO;
1033 /* Handle end of message */
1034 if (message->state == DONE_STATE) {
1035 message->status = 0;
1040 /* Delay if requested at end of transfer before CS change */
1041 if (message->state == RUNNING_STATE) {
1042 previous = list_entry(transfer->transfer_list.prev,
1043 struct spi_transfer,
1045 if (previous->delay_usecs)
1046 udelay(previous->delay_usecs);
1048 /* Drop chip select only if cs_change is requested */
1049 if (previous->cs_change)
1050 cs_deassert(drv_data);
1053 /* Check if we can DMA this transfer */
1054 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
1056 /* reject already-mapped transfers; PIO won't always work */
1057 if (message->is_dma_mapped
1058 || transfer->rx_dma || transfer->tx_dma) {
1059 dev_err(&drv_data->pdev->dev,
1060 "pump_transfers: mapped transfer length of "
1061 "%u is greater than %d\n",
1062 transfer->len, MAX_DMA_LEN);
1063 message->status = -EINVAL;
1068 /* warn ... we force this to PIO mode */
1069 dev_warn_ratelimited(&message->spi->dev,
1070 "pump_transfers: DMA disabled for transfer length %ld "
1071 "greater than %d\n",
1072 (long)drv_data->len, MAX_DMA_LEN);
1075 /* Setup the transfer state based on the type of transfer */
1076 if (pxa2xx_spi_flush(drv_data) == 0) {
1077 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1078 message->status = -EIO;
1082 drv_data->n_bytes = chip->n_bytes;
1083 drv_data->tx = (void *)transfer->tx_buf;
1084 drv_data->tx_end = drv_data->tx + transfer->len;
1085 drv_data->rx = transfer->rx_buf;
1086 drv_data->rx_end = drv_data->rx + transfer->len;
1087 drv_data->len = transfer->len;
1088 drv_data->write = drv_data->tx ? chip->write : null_writer;
1089 drv_data->read = drv_data->rx ? chip->read : null_reader;
1091 /* Change speed and bit per word on a per transfer */
1092 bits = transfer->bits_per_word;
1093 speed = transfer->speed_hz;
1095 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1098 drv_data->n_bytes = 1;
1099 drv_data->read = drv_data->read != null_reader ?
1100 u8_reader : null_reader;
1101 drv_data->write = drv_data->write != null_writer ?
1102 u8_writer : null_writer;
1103 } else if (bits <= 16) {
1104 drv_data->n_bytes = 2;
1105 drv_data->read = drv_data->read != null_reader ?
1106 u16_reader : null_reader;
1107 drv_data->write = drv_data->write != null_writer ?
1108 u16_writer : null_writer;
1109 } else if (bits <= 32) {
1110 drv_data->n_bytes = 4;
1111 drv_data->read = drv_data->read != null_reader ?
1112 u32_reader : null_reader;
1113 drv_data->write = drv_data->write != null_writer ?
1114 u32_writer : null_writer;
1117 * if bits/word is changed in dma mode, then must check the
1118 * thresholds and burst also
1120 if (chip->enable_dma) {
1121 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1125 dev_warn_ratelimited(&message->spi->dev,
1126 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1129 message->state = RUNNING_STATE;
1131 dma_mapped = master->can_dma &&
1132 master->can_dma(master, message->spi, transfer) &&
1133 master->cur_msg_mapped;
1136 /* Ensure we have the correct interrupt handler */
1137 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1139 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1141 message->status = err;
1146 /* Clear status and start DMA engine */
1147 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1148 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1150 pxa2xx_spi_dma_start(drv_data);
1152 /* Ensure we have the correct interrupt handler */
1153 drv_data->transfer_handler = interrupt_transfer;
1156 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1157 write_SSSR_CS(drv_data, drv_data->clear_sr);
1160 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1161 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1162 if (!pxa25x_ssp_comp(drv_data))
1163 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1164 master->max_speed_hz
1165 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1166 dma_mapped ? "DMA" : "PIO");
1168 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1169 master->max_speed_hz / 2
1170 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1171 dma_mapped ? "DMA" : "PIO");
1173 if (is_lpss_ssp(drv_data)) {
1174 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1175 != chip->lpss_rx_threshold)
1176 pxa2xx_spi_write(drv_data, SSIRF,
1177 chip->lpss_rx_threshold);
1178 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1179 != chip->lpss_tx_threshold)
1180 pxa2xx_spi_write(drv_data, SSITF,
1181 chip->lpss_tx_threshold);
1184 if (is_quark_x1000_ssp(drv_data) &&
1185 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1186 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1188 /* see if we need to reload the config registers */
1189 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1190 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1191 != (cr1 & change_mask)) {
1192 /* stop the SSP, and update the other bits */
1193 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1194 if (!pxa25x_ssp_comp(drv_data))
1195 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1196 /* first set CR1 without interrupt and service enables */
1197 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1198 /* restart the SSP */
1199 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1202 if (!pxa25x_ssp_comp(drv_data))
1203 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1206 cs_assert(drv_data);
1208 /* after chip select, release the data by enabling service
1209 * requests and interrupts, without changing any mode bits */
1210 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1213 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1214 struct spi_message *msg)
1216 struct driver_data *drv_data = spi_master_get_devdata(master);
1218 /* Initial message state*/
1219 msg->state = START_STATE;
1220 drv_data->cur_transfer = list_entry(msg->transfers.next,
1221 struct spi_transfer,
1224 /* Mark as busy and launch transfers */
1225 tasklet_schedule(&drv_data->pump_transfers);
1229 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1231 struct driver_data *drv_data = spi_master_get_devdata(master);
1233 /* Disable the SSP now */
1234 pxa2xx_spi_write(drv_data, SSCR0,
1235 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1240 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1241 struct pxa2xx_spi_chip *chip_info)
1243 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1244 struct gpio_desc *gpiod;
1250 if (drv_data->cs_gpiods) {
1251 gpiod = drv_data->cs_gpiods[spi->chip_select];
1253 chip->gpiod_cs = gpiod;
1254 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1255 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1261 if (chip_info == NULL)
1264 /* NOTE: setup() can be called multiple times, possibly with
1265 * different chip_info, release previously requested GPIO
1267 if (chip->gpiod_cs) {
1268 gpio_free(desc_to_gpio(chip->gpiod_cs));
1269 chip->gpiod_cs = NULL;
1272 /* If (*cs_control) is provided, ignore GPIO chip select */
1273 if (chip_info->cs_control) {
1274 chip->cs_control = chip_info->cs_control;
1278 if (gpio_is_valid(chip_info->gpio_cs)) {
1279 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1281 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1282 chip_info->gpio_cs);
1286 gpiod = gpio_to_desc(chip_info->gpio_cs);
1287 chip->gpiod_cs = gpiod;
1288 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1290 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1296 static int setup(struct spi_device *spi)
1298 struct pxa2xx_spi_chip *chip_info;
1299 struct chip_data *chip;
1300 const struct lpss_config *config;
1301 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1302 uint tx_thres, tx_hi_thres, rx_thres;
1304 switch (drv_data->ssp_type) {
1305 case QUARK_X1000_SSP:
1306 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1308 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1311 tx_thres = TX_THRESH_CE4100_DFLT;
1313 rx_thres = RX_THRESH_CE4100_DFLT;
1321 config = lpss_get_config(drv_data);
1322 tx_thres = config->tx_threshold_lo;
1323 tx_hi_thres = config->tx_threshold_hi;
1324 rx_thres = config->rx_threshold;
1327 tx_thres = TX_THRESH_DFLT;
1329 rx_thres = RX_THRESH_DFLT;
1333 /* Only alloc on first setup */
1334 chip = spi_get_ctldata(spi);
1336 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1340 if (drv_data->ssp_type == CE4100_SSP) {
1341 if (spi->chip_select > 4) {
1343 "failed setup: cs number must not be > 4.\n");
1348 chip->frm = spi->chip_select;
1350 chip->enable_dma = drv_data->master_info->enable_dma;
1351 chip->timeout = TIMOUT_DFLT;
1354 /* protocol drivers may change the chip settings, so...
1355 * if chip_info exists, use it */
1356 chip_info = spi->controller_data;
1358 /* chip_info isn't always needed */
1361 if (chip_info->timeout)
1362 chip->timeout = chip_info->timeout;
1363 if (chip_info->tx_threshold)
1364 tx_thres = chip_info->tx_threshold;
1365 if (chip_info->tx_hi_threshold)
1366 tx_hi_thres = chip_info->tx_hi_threshold;
1367 if (chip_info->rx_threshold)
1368 rx_thres = chip_info->rx_threshold;
1369 chip->dma_threshold = 0;
1370 if (chip_info->enable_loopback)
1371 chip->cr1 = SSCR1_LBM;
1374 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1375 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1376 | SSITF_TxHiThresh(tx_hi_thres);
1378 /* set dma burst and threshold outside of chip_info path so that if
1379 * chip_info goes away after setting chip->enable_dma, the
1380 * burst and threshold can still respond to changes in bits_per_word */
1381 if (chip->enable_dma) {
1382 /* set up legal burst and threshold for dma */
1383 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1385 &chip->dma_burst_size,
1386 &chip->dma_threshold)) {
1388 "in setup: DMA burst size reduced to match bits_per_word\n");
1392 switch (drv_data->ssp_type) {
1393 case QUARK_X1000_SSP:
1394 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1395 & QUARK_X1000_SSCR1_RFT)
1396 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1397 & QUARK_X1000_SSCR1_TFT);
1400 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1401 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1404 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1405 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1409 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1410 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1411 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1413 if (spi->mode & SPI_LOOP)
1414 chip->cr1 |= SSCR1_LBM;
1416 if (spi->bits_per_word <= 8) {
1418 chip->read = u8_reader;
1419 chip->write = u8_writer;
1420 } else if (spi->bits_per_word <= 16) {
1422 chip->read = u16_reader;
1423 chip->write = u16_writer;
1424 } else if (spi->bits_per_word <= 32) {
1426 chip->read = u32_reader;
1427 chip->write = u32_writer;
1430 spi_set_ctldata(spi, chip);
1432 if (drv_data->ssp_type == CE4100_SSP)
1435 return setup_cs(spi, chip, chip_info);
1438 static void cleanup(struct spi_device *spi)
1440 struct chip_data *chip = spi_get_ctldata(spi);
1441 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1446 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1448 gpio_free(desc_to_gpio(chip->gpiod_cs));
1456 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1457 { "INT33C0", LPSS_LPT_SSP },
1458 { "INT33C1", LPSS_LPT_SSP },
1459 { "INT3430", LPSS_LPT_SSP },
1460 { "INT3431", LPSS_LPT_SSP },
1461 { "80860F0E", LPSS_BYT_SSP },
1462 { "8086228E", LPSS_BSW_SSP },
1465 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1467 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1472 if (adev && adev->pnp.unique_id &&
1473 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1477 #else /* !CONFIG_ACPI */
1478 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1485 * PCI IDs of compound devices that integrate both host controller and private
1486 * integrated DMA engine. Please note these are not used in module
1487 * autoloading and probing in this module but matching the LPSS SSP type.
1489 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1491 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1492 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1494 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1495 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1497 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1498 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1500 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1501 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1502 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1504 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1505 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1506 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1508 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1509 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1510 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1512 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1513 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1514 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1516 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1517 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1518 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1520 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1521 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1522 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1524 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1525 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1526 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1530 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1532 return param == chan->device->dev;
1535 static struct pxa2xx_spi_master *
1536 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1538 struct pxa2xx_spi_master *pdata;
1539 struct acpi_device *adev;
1540 struct ssp_device *ssp;
1541 struct resource *res;
1542 const struct acpi_device_id *adev_id = NULL;
1543 const struct pci_device_id *pcidev_id = NULL;
1546 adev = ACPI_COMPANION(&pdev->dev);
1548 if (dev_is_pci(pdev->dev.parent))
1549 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1550 to_pci_dev(pdev->dev.parent));
1552 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1558 type = (int)adev_id->driver_data;
1560 type = (int)pcidev_id->driver_data;
1564 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1568 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1574 ssp->phys_base = res->start;
1575 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1576 if (IS_ERR(ssp->mmio_base))
1580 pdata->tx_param = pdev->dev.parent;
1581 pdata->rx_param = pdev->dev.parent;
1582 pdata->dma_filter = pxa2xx_spi_idma_filter;
1585 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1586 if (IS_ERR(ssp->clk))
1589 ssp->irq = platform_get_irq(pdev, 0);
1595 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1597 pdata->num_chipselect = 1;
1598 pdata->enable_dma = true;
1603 #else /* !CONFIG_PCI */
1604 static inline struct pxa2xx_spi_master *
1605 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1611 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1613 struct driver_data *drv_data = spi_master_get_devdata(master);
1615 if (has_acpi_companion(&drv_data->pdev->dev)) {
1616 switch (drv_data->ssp_type) {
1618 * For Atoms the ACPI DeviceSelection used by the Windows
1619 * driver starts from 1 instead of 0 so translate it here
1620 * to match what Linux expects.
1634 static int pxa2xx_spi_probe(struct platform_device *pdev)
1636 struct device *dev = &pdev->dev;
1637 struct pxa2xx_spi_master *platform_info;
1638 struct spi_master *master;
1639 struct driver_data *drv_data;
1640 struct ssp_device *ssp;
1641 const struct lpss_config *config;
1645 platform_info = dev_get_platdata(dev);
1646 if (!platform_info) {
1647 platform_info = pxa2xx_spi_init_pdata(pdev);
1648 if (!platform_info) {
1649 dev_err(&pdev->dev, "missing platform data\n");
1654 ssp = pxa_ssp_request(pdev->id, pdev->name);
1656 ssp = &platform_info->ssp;
1658 if (!ssp->mmio_base) {
1659 dev_err(&pdev->dev, "failed to get ssp\n");
1663 master = devm_spi_alloc_master(dev, sizeof(*drv_data));
1665 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1669 drv_data = spi_master_get_devdata(master);
1670 drv_data->master = master;
1671 drv_data->master_info = platform_info;
1672 drv_data->pdev = pdev;
1673 drv_data->ssp = ssp;
1675 master->dev.of_node = pdev->dev.of_node;
1676 /* the spi->mode bits understood by this driver: */
1677 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1679 master->bus_num = ssp->port_id;
1680 master->dma_alignment = DMA_ALIGNMENT;
1681 master->cleanup = cleanup;
1682 master->setup = setup;
1683 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1684 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1685 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1686 master->auto_runtime_pm = true;
1687 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
1689 drv_data->ssp_type = ssp->type;
1691 drv_data->ioaddr = ssp->mmio_base;
1692 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1693 if (pxa25x_ssp_comp(drv_data)) {
1694 switch (drv_data->ssp_type) {
1695 case QUARK_X1000_SSP:
1696 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1699 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1703 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1704 drv_data->dma_cr1 = 0;
1705 drv_data->clear_sr = SSSR_ROR;
1706 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1708 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1709 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1710 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1711 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1712 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1715 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1718 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1719 goto out_error_master_alloc;
1722 /* Setup DMA if requested */
1723 if (platform_info->enable_dma) {
1724 status = pxa2xx_spi_dma_setup(drv_data);
1726 dev_dbg(dev, "no DMA channels available, using PIO\n");
1727 platform_info->enable_dma = false;
1729 master->can_dma = pxa2xx_spi_can_dma;
1730 master->max_dma_len = MAX_DMA_LEN;
1734 /* Enable SOC clock */
1735 clk_prepare_enable(ssp->clk);
1737 master->max_speed_hz = clk_get_rate(ssp->clk);
1739 /* Load default SSP configuration */
1740 pxa2xx_spi_write(drv_data, SSCR0, 0);
1741 switch (drv_data->ssp_type) {
1742 case QUARK_X1000_SSP:
1743 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1744 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1745 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1747 /* using the Motorola SPI protocol and use 8 bit frame */
1748 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1749 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1752 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1753 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1754 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1755 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1756 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1759 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1760 SSCR1_TxTresh(TX_THRESH_DFLT);
1761 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1762 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1763 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1767 if (!pxa25x_ssp_comp(drv_data))
1768 pxa2xx_spi_write(drv_data, SSTO, 0);
1770 if (!is_quark_x1000_ssp(drv_data))
1771 pxa2xx_spi_write(drv_data, SSPSP, 0);
1773 if (is_lpss_ssp(drv_data)) {
1774 lpss_ssp_setup(drv_data);
1775 config = lpss_get_config(drv_data);
1776 if (config->reg_capabilities >= 0) {
1777 tmp = __lpss_ssp_read_priv(drv_data,
1778 config->reg_capabilities);
1779 tmp &= LPSS_CAPS_CS_EN_MASK;
1780 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1781 platform_info->num_chipselect = ffz(tmp);
1782 } else if (config->cs_num) {
1783 platform_info->num_chipselect = config->cs_num;
1786 master->num_chipselect = platform_info->num_chipselect;
1788 count = gpiod_count(&pdev->dev, "cs");
1792 master->num_chipselect = max_t(int, count,
1793 master->num_chipselect);
1795 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1796 master->num_chipselect, sizeof(struct gpio_desc *),
1798 if (!drv_data->cs_gpiods) {
1800 goto out_error_clock_enabled;
1803 for (i = 0; i < master->num_chipselect; i++) {
1804 struct gpio_desc *gpiod;
1806 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1807 if (IS_ERR(gpiod)) {
1808 /* Means use native chip select */
1809 if (PTR_ERR(gpiod) == -ENOENT)
1812 status = (int)PTR_ERR(gpiod);
1813 goto out_error_clock_enabled;
1815 drv_data->cs_gpiods[i] = gpiod;
1820 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1821 (unsigned long)drv_data);
1823 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1824 pm_runtime_use_autosuspend(&pdev->dev);
1825 pm_runtime_set_active(&pdev->dev);
1826 pm_runtime_enable(&pdev->dev);
1828 /* Register with the SPI framework */
1829 platform_set_drvdata(pdev, drv_data);
1830 status = spi_register_master(master);
1832 dev_err(&pdev->dev, "problem registering spi master\n");
1833 goto out_error_clock_enabled;
1838 out_error_clock_enabled:
1839 clk_disable_unprepare(ssp->clk);
1840 pxa2xx_spi_dma_release(drv_data);
1841 free_irq(ssp->irq, drv_data);
1843 out_error_master_alloc:
1848 static int pxa2xx_spi_remove(struct platform_device *pdev)
1850 struct driver_data *drv_data = platform_get_drvdata(pdev);
1851 struct ssp_device *ssp;
1855 ssp = drv_data->ssp;
1857 pm_runtime_get_sync(&pdev->dev);
1859 spi_unregister_master(drv_data->master);
1861 /* Disable the SSP at the peripheral and SOC level */
1862 pxa2xx_spi_write(drv_data, SSCR0, 0);
1863 clk_disable_unprepare(ssp->clk);
1866 if (drv_data->master_info->enable_dma)
1867 pxa2xx_spi_dma_release(drv_data);
1869 pm_runtime_put_noidle(&pdev->dev);
1870 pm_runtime_disable(&pdev->dev);
1873 free_irq(ssp->irq, drv_data);
1881 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1885 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1886 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1889 #ifdef CONFIG_PM_SLEEP
1890 static int pxa2xx_spi_suspend(struct device *dev)
1892 struct driver_data *drv_data = dev_get_drvdata(dev);
1893 struct ssp_device *ssp = drv_data->ssp;
1896 status = spi_master_suspend(drv_data->master);
1899 pxa2xx_spi_write(drv_data, SSCR0, 0);
1901 if (!pm_runtime_suspended(dev))
1902 clk_disable_unprepare(ssp->clk);
1907 static int pxa2xx_spi_resume(struct device *dev)
1909 struct driver_data *drv_data = dev_get_drvdata(dev);
1910 struct ssp_device *ssp = drv_data->ssp;
1913 /* Enable the SSP clock */
1914 if (!pm_runtime_suspended(dev))
1915 clk_prepare_enable(ssp->clk);
1917 /* Restore LPSS private register bits */
1918 if (is_lpss_ssp(drv_data))
1919 lpss_ssp_setup(drv_data);
1921 /* Start the queue running */
1922 status = spi_master_resume(drv_data->master);
1924 dev_err(dev, "problem starting queue (%d)\n", status);
1933 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1935 struct driver_data *drv_data = dev_get_drvdata(dev);
1937 clk_disable_unprepare(drv_data->ssp->clk);
1941 static int pxa2xx_spi_runtime_resume(struct device *dev)
1943 struct driver_data *drv_data = dev_get_drvdata(dev);
1945 clk_prepare_enable(drv_data->ssp->clk);
1950 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1951 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1952 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1953 pxa2xx_spi_runtime_resume, NULL)
1956 static struct platform_driver driver = {
1958 .name = "pxa2xx-spi",
1959 .pm = &pxa2xx_spi_pm_ops,
1960 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1962 .probe = pxa2xx_spi_probe,
1963 .remove = pxa2xx_spi_remove,
1964 .shutdown = pxa2xx_spi_shutdown,
1967 static int __init pxa2xx_spi_init(void)
1969 return platform_driver_register(&driver);
1971 subsys_initcall(pxa2xx_spi_init);
1973 static void __exit pxa2xx_spi_exit(void)
1975 platform_driver_unregister(&driver);
1977 module_exit(pxa2xx_spi_exit);