2 * Freescale QuadSPI driver.
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
30 #include <linux/pm_qos.h>
31 #include <linux/sizes.h>
33 /* Controller needs driver to swap endian */
34 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
35 /* Controller needs 4x internal clock */
36 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
38 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
39 * trigger data transfer even though extern data will not transferred.
41 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
42 /* Controller cannot wake up from wait mode, TKT245618 */
43 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
46 #define QUADSPI_MCR 0x00
47 #define QUADSPI_MCR_RESERVED_SHIFT 16
48 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
49 #define QUADSPI_MCR_MDIS_SHIFT 14
50 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
51 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
52 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
53 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
54 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
55 #define QUADSPI_MCR_DDR_EN_SHIFT 7
56 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
57 #define QUADSPI_MCR_END_CFG_SHIFT 2
58 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
59 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
60 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
61 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
62 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
64 #define QUADSPI_IPCR 0x08
65 #define QUADSPI_IPCR_SEQID_SHIFT 24
66 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
68 #define QUADSPI_BUF0CR 0x10
69 #define QUADSPI_BUF1CR 0x14
70 #define QUADSPI_BUF2CR 0x18
71 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
73 #define QUADSPI_BUF3CR 0x1c
74 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
75 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
76 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
77 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
79 #define QUADSPI_BFGENCR 0x20
80 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
81 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
82 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
83 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
85 #define QUADSPI_BUF0IND 0x30
86 #define QUADSPI_BUF1IND 0x34
87 #define QUADSPI_BUF2IND 0x38
88 #define QUADSPI_SFAR 0x100
90 #define QUADSPI_SMPR 0x108
91 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
92 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
93 #define QUADSPI_SMPR_FSDLY_SHIFT 6
94 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
95 #define QUADSPI_SMPR_FSPHS_SHIFT 5
96 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
97 #define QUADSPI_SMPR_HSENA_SHIFT 0
98 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
100 #define QUADSPI_RBSR 0x10c
101 #define QUADSPI_RBSR_RDBFL_SHIFT 8
102 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
104 #define QUADSPI_RBCT 0x110
105 #define QUADSPI_RBCT_WMRK_MASK 0x1F
106 #define QUADSPI_RBCT_RXBRD_SHIFT 8
107 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
109 #define QUADSPI_TBSR 0x150
110 #define QUADSPI_TBDR 0x154
111 #define QUADSPI_SR 0x15c
112 #define QUADSPI_SR_IP_ACC_SHIFT 1
113 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
114 #define QUADSPI_SR_AHB_ACC_SHIFT 2
115 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
117 #define QUADSPI_FR 0x160
118 #define QUADSPI_FR_TFF_MASK 0x1
120 #define QUADSPI_SFA1AD 0x180
121 #define QUADSPI_SFA2AD 0x184
122 #define QUADSPI_SFB1AD 0x188
123 #define QUADSPI_SFB2AD 0x18c
124 #define QUADSPI_RBDR 0x200
126 #define QUADSPI_LUTKEY 0x300
127 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
129 #define QUADSPI_LCKCR 0x304
130 #define QUADSPI_LCKER_LOCK 0x1
131 #define QUADSPI_LCKER_UNLOCK 0x2
133 #define QUADSPI_RSER 0x164
134 #define QUADSPI_RSER_TFIE (0x1 << 0)
136 #define QUADSPI_LUT_BASE 0x310
139 * The definition of the LUT register shows below:
141 * ---------------------------------------------------
142 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
143 * ---------------------------------------------------
145 #define OPRND0_SHIFT 0
147 #define INSTR0_SHIFT 10
148 #define OPRND1_SHIFT 16
150 /* Instruction set for the LUT register. */
158 #define LUT_FSL_READ 7
159 #define LUT_FSL_WRITE 8
160 #define LUT_JMP_ON_CS 9
161 #define LUT_ADDR_DDR 10
162 #define LUT_MODE_DDR 11
163 #define LUT_MODE2_DDR 12
164 #define LUT_MODE4_DDR 13
165 #define LUT_FSL_READ_DDR 14
166 #define LUT_FSL_WRITE_DDR 15
167 #define LUT_DATA_LEARN 16
170 * The PAD definitions for LUT register.
172 * The pad stands for the lines number of IO[0:3].
173 * For example, the Quad read need four IO lines, so you should
174 * set LUT_PAD4 which means we use four IO lines.
180 /* Oprands for the LUT register. */
181 #define ADDR24BIT 0x18
182 #define ADDR32BIT 0x20
184 /* Macros for constructing the LUT register. */
185 #define LUT0(ins, pad, opr) \
186 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
187 ((LUT_##ins) << INSTR0_SHIFT))
189 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
191 /* other macros for LUT register. */
192 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
193 #define QUADSPI_LUT_NUM 64
195 /* SEQID -- we can have 16 seqids at most. */
201 #define SEQID_CHIP_ERASE 5
206 #define SEQID_EN4B 10
207 #define SEQID_BRWR 11
209 #define QUADSPI_MIN_IOMAP SZ_4M
211 enum fsl_qspi_devtype {
219 struct fsl_qspi_devtype_data {
220 enum fsl_qspi_devtype devtype;
227 static const struct fsl_qspi_devtype_data vybrid_data = {
228 .devtype = FSL_QUADSPI_VYBRID,
231 .ahb_buf_size = 1024,
232 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
235 static const struct fsl_qspi_devtype_data imx6sx_data = {
236 .devtype = FSL_QUADSPI_IMX6SX,
239 .ahb_buf_size = 1024,
240 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
241 | QUADSPI_QUIRK_TKT245618,
244 static const struct fsl_qspi_devtype_data imx7d_data = {
245 .devtype = FSL_QUADSPI_IMX7D,
248 .ahb_buf_size = 1024,
249 .driver_data = QUADSPI_QUIRK_TKT253890
250 | QUADSPI_QUIRK_4X_INT_CLK,
253 static const struct fsl_qspi_devtype_data imx6ul_data = {
254 .devtype = FSL_QUADSPI_IMX6UL,
257 .ahb_buf_size = 1024,
258 .driver_data = QUADSPI_QUIRK_TKT253890
259 | QUADSPI_QUIRK_4X_INT_CLK,
262 static struct fsl_qspi_devtype_data ls1021a_data = {
263 .devtype = FSL_QUADSPI_LS1021A,
266 .ahb_buf_size = 1024,
270 #define FSL_QSPI_MAX_CHIP 4
272 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
273 void __iomem *iobase;
274 void __iomem *ahb_addr;
278 struct clk *clk, *clk_en;
281 const struct fsl_qspi_devtype_data *devtype_data;
285 unsigned int chip_base_addr; /* We may support two chips. */
286 bool has_second_chip;
289 struct pm_qos_request pm_qos_req;
292 static inline int needs_swap_endian(struct fsl_qspi *q)
294 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
297 static inline int needs_4x_clock(struct fsl_qspi *q)
299 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
302 static inline int needs_fill_txfifo(struct fsl_qspi *q)
304 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
307 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
309 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
313 * R/W functions for big- or little-endian registers:
314 * The qSPI controller's endian is independent of the CPU core's endian.
315 * So far, although the CPU core is little-endian but the qSPI have two
316 * versions for big-endian and little-endian.
318 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
321 iowrite32be(val, addr);
323 iowrite32(val, addr);
326 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
329 return ioread32be(addr);
331 return ioread32(addr);
335 * An IC bug makes us to re-arrange the 32-bit data.
336 * The following chips, such as IMX6SLX, have fixed this bug.
338 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
340 return needs_swap_endian(q) ? __swab32(a) : a;
343 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
345 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
346 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
349 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
351 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
352 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
355 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
357 struct fsl_qspi *q = dev_id;
360 /* clear interrupt */
361 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
362 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
364 if (reg & QUADSPI_FR_TFF_MASK)
367 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
371 static void fsl_qspi_init_lut(struct fsl_qspi *q)
373 void __iomem *base = q->iobase;
374 int rxfifo = q->devtype_data->rxfifo;
378 struct spi_nor *nor = &q->nor[0];
379 u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
380 u8 read_op = nor->read_opcode;
381 u8 read_dm = nor->read_dummy;
383 fsl_qspi_unlock_lut(q);
385 /* Clear all the LUT table */
386 for (i = 0; i < QUADSPI_LUT_NUM; i++)
387 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
390 lut_base = SEQID_READ * 4;
392 qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
393 base + QUADSPI_LUT(lut_base));
394 qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
395 LUT1(FSL_READ, PAD4, rxfifo),
396 base + QUADSPI_LUT(lut_base + 1));
399 lut_base = SEQID_WREN * 4;
400 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
401 base + QUADSPI_LUT(lut_base));
404 lut_base = SEQID_PP * 4;
406 qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
407 LUT1(ADDR, PAD1, addrlen),
408 base + QUADSPI_LUT(lut_base));
409 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
410 base + QUADSPI_LUT(lut_base + 1));
413 lut_base = SEQID_RDSR * 4;
414 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
415 LUT1(FSL_READ, PAD1, 0x1),
416 base + QUADSPI_LUT(lut_base));
419 lut_base = SEQID_SE * 4;
421 qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
422 LUT1(ADDR, PAD1, addrlen),
423 base + QUADSPI_LUT(lut_base));
425 /* Erase the whole chip */
426 lut_base = SEQID_CHIP_ERASE * 4;
427 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
428 base + QUADSPI_LUT(lut_base));
431 lut_base = SEQID_RDID * 4;
432 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
433 LUT1(FSL_READ, PAD1, 0x8),
434 base + QUADSPI_LUT(lut_base));
437 lut_base = SEQID_WRSR * 4;
438 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
439 LUT1(FSL_WRITE, PAD1, 0x2),
440 base + QUADSPI_LUT(lut_base));
442 /* Read Configuration Register */
443 lut_base = SEQID_RDCR * 4;
444 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
445 LUT1(FSL_READ, PAD1, 0x1),
446 base + QUADSPI_LUT(lut_base));
449 lut_base = SEQID_WRDI * 4;
450 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
451 base + QUADSPI_LUT(lut_base));
453 /* Enter 4 Byte Mode (Micron) */
454 lut_base = SEQID_EN4B * 4;
455 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
456 base + QUADSPI_LUT(lut_base));
458 /* Enter 4 Byte Mode (Spansion) */
459 lut_base = SEQID_BRWR * 4;
460 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
461 base + QUADSPI_LUT(lut_base));
463 fsl_qspi_lock_lut(q);
466 /* Get the SEQID for the command */
467 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
470 case SPINOR_OP_READ_1_1_4:
471 case SPINOR_OP_READ_1_1_4_4B:
481 case SPINOR_OP_CHIP_ERASE:
482 return SEQID_CHIP_ERASE;
496 if (cmd == q->nor[0].erase_opcode)
498 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
505 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
507 void __iomem *base = q->iobase;
512 init_completion(&q->c);
513 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
514 q->chip_base_addr, addr, len, cmd);
517 reg = qspi_readl(q, base + QUADSPI_MCR);
519 qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
520 base + QUADSPI_SFAR);
521 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
522 base + QUADSPI_RBCT);
523 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
526 reg2 = qspi_readl(q, base + QUADSPI_SR);
527 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
529 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
535 /* trigger the LUT now */
536 seqid = fsl_qspi_get_seqid(q, cmd);
537 qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
538 base + QUADSPI_IPCR);
540 /* Wait for the interrupt. */
541 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
543 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
544 cmd, addr, qspi_readl(q, base + QUADSPI_FR),
545 qspi_readl(q, base + QUADSPI_SR));
551 /* restore the MCR */
552 qspi_writel(q, reg, base + QUADSPI_MCR);
557 /* Read out the data from the QUADSPI_RBDR buffer registers. */
558 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
564 tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
565 tmp = fsl_qspi_endian_xchg(q, tmp);
566 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
567 q->chip_base_addr, tmp);
570 *((u32 *)rxbuf) = tmp;
573 memcpy(rxbuf, &tmp, len);
583 * If we have changed the content of the flash by writing or erasing,
584 * we need to invalidate the AHB buffer. If we do not do so, we may read out
585 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
586 * domain at the same time.
588 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
592 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
593 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
594 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
597 * The minimum delay : 1 AHB + 2 SFCK clocks.
598 * Delay 1 us is enough.
602 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
603 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
606 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
607 u8 opcode, unsigned int to, u32 *txbuf,
613 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
614 q->chip_base_addr, to, count);
616 /* clear the TX FIFO. */
617 tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
618 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
620 /* fill the TX data to the FIFO */
621 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
622 tmp = fsl_qspi_endian_xchg(q, *txbuf);
623 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
627 /* fill the TXFIFO upto 16 bytes for i.MX7d */
628 if (needs_fill_txfifo(q))
630 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
633 ret = fsl_qspi_runcmd(q, opcode, to, count);
641 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
643 int nor_size = q->nor_size;
644 void __iomem *base = q->iobase;
646 qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
647 qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
648 qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
649 qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
653 * There are two different ways to read out the data from the flash:
654 * the "IP Command Read" and the "AHB Command Read".
656 * The IC guy suggests we use the "AHB Command Read" which is faster
657 * then the "IP Command Read". (What's more is that there is a bug in
658 * the "IP Command Read" in the Vybrid.)
660 * After we set up the registers for the "AHB Command Read", we can use
661 * the memcpy to read the data directly. A "missed" access to the buffer
662 * causes the controller to clear the buffer, and use the sequence pointed
663 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
665 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
667 void __iomem *base = q->iobase;
670 /* AHB configuration for access buffer 0/1/2 .*/
671 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
672 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
673 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
675 * Set ADATSZ with the maximum AHB buffer size to improve the
678 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
679 ((q->devtype_data->ahb_buf_size / 8)
680 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
681 base + QUADSPI_BUF3CR);
683 /* We only use the buffer3 */
684 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
685 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
686 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
688 /* Set the default lut sequence for AHB Read. */
689 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
690 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
691 q->iobase + QUADSPI_BFGENCR);
694 /* This function was used to prepare and enable QSPI clock */
695 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
699 ret = clk_prepare_enable(q->clk_en);
703 ret = clk_prepare_enable(q->clk);
705 clk_disable_unprepare(q->clk_en);
709 if (needs_wakeup_wait_mode(q))
710 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
715 /* This function was used to disable and unprepare QSPI clock */
716 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
718 if (needs_wakeup_wait_mode(q))
719 pm_qos_remove_request(&q->pm_qos_req);
721 clk_disable_unprepare(q->clk);
722 clk_disable_unprepare(q->clk_en);
726 /* We use this function to do some basic init for spi_nor_scan(). */
727 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
729 void __iomem *base = q->iobase;
733 /* disable and unprepare clock to avoid glitch pass to controller */
734 fsl_qspi_clk_disable_unprep(q);
736 /* the default frequency, we will change it in the future. */
737 ret = clk_set_rate(q->clk, 66000000);
741 ret = fsl_qspi_clk_prep_enable(q);
745 /* Reset the module */
746 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
750 /* Init the LUT table. */
751 fsl_qspi_init_lut(q);
753 /* Disable the module */
754 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
757 reg = qspi_readl(q, base + QUADSPI_SMPR);
758 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
759 | QUADSPI_SMPR_FSPHS_MASK
760 | QUADSPI_SMPR_HSENA_MASK
761 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
763 /* Enable the module */
764 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
767 /* clear all interrupt status */
768 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
770 /* enable the interrupt */
771 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
776 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
778 unsigned long rate = q->clk_rate;
781 if (needs_4x_clock(q))
784 /* disable and unprepare clock to avoid glitch pass to controller */
785 fsl_qspi_clk_disable_unprep(q);
787 ret = clk_set_rate(q->clk, rate);
791 ret = fsl_qspi_clk_prep_enable(q);
795 /* Init the LUT table again. */
796 fsl_qspi_init_lut(q);
798 /* Init for AHB read */
799 fsl_qspi_init_abh_read(q);
804 static const struct of_device_id fsl_qspi_dt_ids[] = {
805 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
806 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
807 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
808 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
809 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
812 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
814 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
816 q->chip_base_addr = q->nor_size * (nor - q->nor);
819 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
822 struct fsl_qspi *q = nor->priv;
824 ret = fsl_qspi_runcmd(q, opcode, 0, len);
828 fsl_qspi_read_data(q, len, buf);
832 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
834 struct fsl_qspi *q = nor->priv;
838 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
842 if (opcode == SPINOR_OP_CHIP_ERASE)
845 } else if (len > 0) {
846 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
851 dev_err(q->dev, "invalid cmd %d\n", opcode);
858 static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
859 size_t len, const u_char *buf)
861 struct fsl_qspi *q = nor->priv;
862 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
865 /* invalid the data in the AHB buffer. */
870 static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
871 size_t len, u_char *buf)
873 struct fsl_qspi *q = nor->priv;
874 u8 cmd = nor->read_opcode;
876 /* if necessary,ioremap buffer before AHB read, */
878 q->memmap_offs = q->chip_base_addr + from;
879 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
881 q->ahb_addr = ioremap_nocache(
882 q->memmap_phy + q->memmap_offs,
885 dev_err(q->dev, "ioremap failed\n");
888 /* ioremap if the data requested is out of range */
889 } else if (q->chip_base_addr + from < q->memmap_offs
890 || q->chip_base_addr + from + len >
891 q->memmap_offs + q->memmap_len) {
892 iounmap(q->ahb_addr);
894 q->memmap_offs = q->chip_base_addr + from;
895 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
896 q->ahb_addr = ioremap_nocache(
897 q->memmap_phy + q->memmap_offs,
900 dev_err(q->dev, "ioremap failed\n");
905 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
906 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
909 /* Read out the data directly from the AHB buffer.*/
910 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
916 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
918 struct fsl_qspi *q = nor->priv;
921 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
922 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
924 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
932 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
934 struct fsl_qspi *q = nor->priv;
937 mutex_lock(&q->lock);
939 ret = fsl_qspi_clk_prep_enable(q);
943 fsl_qspi_set_base_addr(q, nor);
947 mutex_unlock(&q->lock);
951 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
953 struct fsl_qspi *q = nor->priv;
955 fsl_qspi_clk_disable_unprep(q);
956 mutex_unlock(&q->lock);
959 static int fsl_qspi_probe(struct platform_device *pdev)
961 const struct spi_nor_hwcaps hwcaps = {
962 .mask = SNOR_HWCAPS_READ_1_1_4 |
965 struct device_node *np = pdev->dev.of_node;
966 struct device *dev = &pdev->dev;
968 struct resource *res;
970 struct mtd_info *mtd;
973 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
977 q->nor_num = of_get_child_count(dev->of_node);
978 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
982 q->devtype_data = of_device_get_match_data(dev);
983 if (!q->devtype_data)
985 platform_set_drvdata(pdev, q);
987 /* find the resources */
988 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
989 q->iobase = devm_ioremap_resource(dev, res);
990 if (IS_ERR(q->iobase))
991 return PTR_ERR(q->iobase);
993 q->big_endian = of_property_read_bool(np, "big-endian");
994 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
996 if (!devm_request_mem_region(dev, res->start, resource_size(res),
998 dev_err(dev, "can't request region for resource %pR\n", res);
1002 q->memmap_phy = res->start;
1004 /* find the clocks */
1005 q->clk_en = devm_clk_get(dev, "qspi_en");
1006 if (IS_ERR(q->clk_en))
1007 return PTR_ERR(q->clk_en);
1009 q->clk = devm_clk_get(dev, "qspi");
1011 return PTR_ERR(q->clk);
1013 ret = fsl_qspi_clk_prep_enable(q);
1015 dev_err(dev, "can not enable the clock\n");
1020 ret = platform_get_irq(pdev, 0);
1022 dev_err(dev, "failed to get the irq: %d\n", ret);
1026 ret = devm_request_irq(dev, ret,
1027 fsl_qspi_irq_handler, 0, pdev->name, q);
1029 dev_err(dev, "failed to request irq: %d\n", ret);
1033 ret = fsl_qspi_nor_setup(q);
1037 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
1038 q->has_second_chip = true;
1040 mutex_init(&q->lock);
1042 /* iterate the subnodes. */
1043 for_each_available_child_of_node(dev->of_node, np) {
1044 /* skip the holes */
1045 if (!q->has_second_chip)
1052 spi_nor_set_flash_node(nor, np);
1055 /* fill the hooks */
1056 nor->read_reg = fsl_qspi_read_reg;
1057 nor->write_reg = fsl_qspi_write_reg;
1058 nor->read = fsl_qspi_read;
1059 nor->write = fsl_qspi_write;
1060 nor->erase = fsl_qspi_erase;
1062 nor->prepare = fsl_qspi_prep;
1063 nor->unprepare = fsl_qspi_unprep;
1065 ret = of_property_read_u32(np, "spi-max-frequency",
1070 /* set the chip address for READID */
1071 fsl_qspi_set_base_addr(q, nor);
1073 ret = spi_nor_scan(nor, NULL, &hwcaps);
1077 ret = mtd_device_register(mtd, NULL, 0);
1081 /* Set the correct NOR size now. */
1082 if (q->nor_size == 0) {
1083 q->nor_size = mtd->size;
1085 /* Map the SPI NOR to accessiable address */
1086 fsl_qspi_set_map_addr(q);
1090 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1091 * may writes 265 bytes per time. The write is working in the
1092 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1095 * So shrink the spi_nor->page_size if it is larger then the
1098 if (nor->page_size > q->devtype_data->txfifo)
1099 nor->page_size = q->devtype_data->txfifo;
1104 /* finish the rest init. */
1105 ret = fsl_qspi_nor_setup_last(q);
1107 goto last_init_failed;
1109 fsl_qspi_clk_disable_unprep(q);
1113 for (i = 0; i < q->nor_num; i++) {
1114 /* skip the holes */
1115 if (!q->has_second_chip)
1117 mtd_device_unregister(&q->nor[i].mtd);
1120 mutex_destroy(&q->lock);
1122 fsl_qspi_clk_disable_unprep(q);
1124 dev_err(dev, "Freescale QuadSPI probe failed\n");
1128 static int fsl_qspi_remove(struct platform_device *pdev)
1130 struct fsl_qspi *q = platform_get_drvdata(pdev);
1133 for (i = 0; i < q->nor_num; i++) {
1134 /* skip the holes */
1135 if (!q->has_second_chip)
1137 mtd_device_unregister(&q->nor[i].mtd);
1140 /* disable the hardware */
1141 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1142 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
1144 mutex_destroy(&q->lock);
1147 iounmap(q->ahb_addr);
1152 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1157 static int fsl_qspi_resume(struct platform_device *pdev)
1160 struct fsl_qspi *q = platform_get_drvdata(pdev);
1162 ret = fsl_qspi_clk_prep_enable(q);
1166 fsl_qspi_nor_setup(q);
1167 fsl_qspi_set_map_addr(q);
1168 fsl_qspi_nor_setup_last(q);
1170 fsl_qspi_clk_disable_unprep(q);
1175 static struct platform_driver fsl_qspi_driver = {
1177 .name = "fsl-quadspi",
1178 .bus = &platform_bus_type,
1179 .of_match_table = fsl_qspi_dt_ids,
1181 .probe = fsl_qspi_probe,
1182 .remove = fsl_qspi_remove,
1183 .suspend = fsl_qspi_suspend,
1184 .resume = fsl_qspi_resume,
1186 module_platform_driver(fsl_qspi_driver);
1188 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1189 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1190 MODULE_LICENSE("GPL v2");