2 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/sched.h>
18 #include <linux/completion.h>
19 #include <linux/spinlock.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/spi/spi.h>
26 #include <lantiq_soc.h>
29 #define LTQ_SPI_RX_IRQ_NAME "spi_rx"
30 #define LTQ_SPI_TX_IRQ_NAME "spi_tx"
31 #define LTQ_SPI_ERR_IRQ_NAME "spi_err"
32 #define LTQ_SPI_FRM_IRQ_NAME "spi_frm"
34 #define LTQ_SPI_CLC 0x00
35 #define LTQ_SPI_PISEL 0x04
36 #define LTQ_SPI_ID 0x08
37 #define LTQ_SPI_CON 0x10
38 #define LTQ_SPI_STAT 0x14
39 #define LTQ_SPI_WHBSTATE 0x18
40 #define LTQ_SPI_TB 0x20
41 #define LTQ_SPI_RB 0x24
42 #define LTQ_SPI_RXFCON 0x30
43 #define LTQ_SPI_TXFCON 0x34
44 #define LTQ_SPI_FSTAT 0x38
45 #define LTQ_SPI_BRT 0x40
46 #define LTQ_SPI_BRSTAT 0x44
47 #define LTQ_SPI_SFCON 0x60
48 #define LTQ_SPI_SFSTAT 0x64
49 #define LTQ_SPI_GPOCON 0x70
50 #define LTQ_SPI_GPOSTAT 0x74
51 #define LTQ_SPI_FPGO 0x78
52 #define LTQ_SPI_RXREQ 0x80
53 #define LTQ_SPI_RXCNT 0x84
54 #define LTQ_SPI_DMACON 0xec
55 #define LTQ_SPI_IRNEN 0xf4
56 #define LTQ_SPI_IRNICR 0xf8
57 #define LTQ_SPI_IRNCR 0xfc
59 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
60 #define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
61 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
62 #define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S)
63 #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
64 #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
66 #define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
67 #define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S)
68 #define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
69 #define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S)
70 #define LTQ_SPI_ID_MOD_S 8 /* Module ID */
71 #define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
72 #define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
73 #define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S)
74 #define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */
76 #define LTQ_SPI_CON_BM_S 16 /* Data width selection */
77 #define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S)
78 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
79 #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
80 #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
81 #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
82 #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
83 #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
84 #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
85 #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
86 #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
87 #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
88 #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
89 #define LTQ_SPI_CON_HB BIT(4) /* Heading control */
90 #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
91 #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
93 #define LTQ_SPI_STAT_RXBV_S 28
94 #define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S)
95 #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
96 #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
97 #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
98 #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
99 #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
100 #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
101 #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
102 #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
103 #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
104 #define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
105 LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
106 LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
108 #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
109 #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
110 #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
111 #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
112 #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
113 #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
114 #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
115 #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
116 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
117 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
118 #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
119 #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
120 #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
121 #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
122 #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
123 #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
124 #define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
125 LTQ_SPI_WHBSTATE_CLRME | \
126 LTQ_SPI_WHBSTATE_CLRTE | \
127 LTQ_SPI_WHBSTATE_CLRRE | \
128 LTQ_SPI_WHBSTATE_CLRAE | \
129 LTQ_SPI_WHBSTATE_CLRTUE)
131 #define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
132 #define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
133 #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
134 #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
136 #define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
137 #define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
138 #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
139 #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
141 #define LTQ_SPI_FSTAT_RXFFL_S 0
142 #define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
143 #define LTQ_SPI_FSTAT_TXFFL_S 8
144 #define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S)
146 #define LTQ_SPI_GPOCON_ISCSBN_S 8
147 #define LTQ_SPI_GPOCON_INVOUTN_S 0
149 #define LTQ_SPI_FGPO_SETOUTN_S 8
150 #define LTQ_SPI_FGPO_CLROUTN_S 0
152 #define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
153 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
155 #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
156 #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
157 #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
158 #define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
159 #define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
160 #define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
161 #define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
162 #define LTQ_SPI_IRNEN_ALL 0x1F
164 struct lantiq_ssc_hwcfg {
165 unsigned int irnen_r;
166 unsigned int irnen_t;
169 struct lantiq_ssc_spi {
170 struct spi_master *master;
172 void __iomem *regbase;
175 const struct lantiq_ssc_hwcfg *hwcfg;
178 struct workqueue_struct *wq;
179 struct work_struct work;
183 unsigned int tx_todo;
184 unsigned int rx_todo;
185 unsigned int bits_per_word;
186 unsigned int speed_hz;
187 unsigned int tx_fifo_size;
188 unsigned int rx_fifo_size;
189 unsigned int base_cs;
190 unsigned int fdx_tx_level;
193 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
195 return __raw_readl(spi->regbase + reg);
198 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
201 __raw_writel(val, spi->regbase + reg);
204 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
207 u32 val = __raw_readl(spi->regbase + reg);
211 __raw_writel(val, spi->regbase + reg);
214 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
216 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
218 return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
221 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
223 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
225 return fstat & LTQ_SPI_FSTAT_RXFFL_M;
228 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
230 return spi->tx_fifo_size - tx_fifo_level(spi);
233 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
235 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
237 val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
238 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
241 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
243 u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
245 val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
246 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
249 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
251 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
254 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
256 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
259 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
261 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
264 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
266 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
269 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
270 unsigned int max_speed_hz)
275 * SPI module clock is derived from FPI bus clock dependent on
276 * divider value in CLC.RMS which is always set to 1.
279 * baudrate = --------------
282 spi_clk = clk_get_rate(spi->fpi_clk) / 2;
284 if (max_speed_hz > spi_clk)
287 brt = spi_clk / max_speed_hz - 1;
292 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
293 spi_clk, max_speed_hz, brt);
295 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
298 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
299 unsigned int bits_per_word)
303 /* CON.BM value = bits_per_word - 1 */
304 bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
306 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
309 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
312 u32 con_set = 0, con_clr = 0;
315 * SPI mode mapping in CON register:
316 * Mode CPOL CPHA CON.PO CON.PH
323 con_clr |= LTQ_SPI_CON_PH;
325 con_set |= LTQ_SPI_CON_PH;
328 con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
330 con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
332 /* Set heading control */
333 if (mode & SPI_LSB_FIRST)
334 con_clr |= LTQ_SPI_CON_HB;
336 con_set |= LTQ_SPI_CON_HB;
338 /* Set loopback mode */
340 con_set |= LTQ_SPI_CON_LB;
342 con_clr |= LTQ_SPI_CON_LB;
344 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
347 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
349 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
352 * Set clock divider for run mode to 1 to
353 * run at same frequency as FPI bus
355 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
357 /* Put controller into config mode */
358 hw_enter_config_mode(spi);
360 /* Clear error flags */
361 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
363 /* Enable error checking, disable TX/RX */
364 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
365 LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
366 LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
368 /* Setup default SPI mode */
369 hw_setup_bits_per_word(spi, spi->bits_per_word);
370 hw_setup_clock_mode(spi, SPI_MODE_0);
372 /* Enable master mode and clear error flags */
373 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
374 LTQ_SPI_WHBSTATE_CLR_ERRORS,
377 /* Reset GPIO/CS registers */
378 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
379 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
381 /* Enable and flush FIFOs */
385 /* Enable interrupts */
386 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
387 LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
390 static int lantiq_ssc_setup(struct spi_device *spidev)
392 struct spi_master *master = spidev->master;
393 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
394 unsigned int cs = spidev->chip_select;
397 /* GPIOs are used for CS */
398 if (gpio_is_valid(spidev->cs_gpio))
401 dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
403 if (cs < spi->base_cs) {
405 "chipselect %i too small (min %i)\n", cs, spi->base_cs);
409 /* set GPO pin to CS mode */
410 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
413 if (spidev->mode & SPI_CS_HIGH)
414 gpocon |= 1 << (cs - spi->base_cs);
416 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
421 static int lantiq_ssc_prepare_message(struct spi_master *master,
422 struct spi_message *message)
424 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
426 hw_enter_config_mode(spi);
427 hw_setup_clock_mode(spi, message->spi->mode);
428 hw_enter_active_mode(spi);
433 static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
434 struct spi_device *spidev, struct spi_transfer *t)
436 unsigned int speed_hz = t->speed_hz;
437 unsigned int bits_per_word = t->bits_per_word;
440 if (bits_per_word != spi->bits_per_word ||
441 speed_hz != spi->speed_hz) {
442 hw_enter_config_mode(spi);
443 hw_setup_speed_hz(spi, speed_hz);
444 hw_setup_bits_per_word(spi, bits_per_word);
445 hw_enter_active_mode(spi);
447 spi->speed_hz = speed_hz;
448 spi->bits_per_word = bits_per_word;
451 /* Configure transmitter and receiver */
452 con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
454 con &= ~LTQ_SPI_CON_TXOFF;
456 con |= LTQ_SPI_CON_TXOFF;
459 con &= ~LTQ_SPI_CON_RXOFF;
461 con |= LTQ_SPI_CON_RXOFF;
463 lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
466 static int lantiq_ssc_unprepare_message(struct spi_master *master,
467 struct spi_message *message)
469 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
471 flush_workqueue(spi->wq);
473 /* Disable transmitter and receiver while idle */
474 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
480 static void tx_fifo_write(struct lantiq_ssc_spi *spi)
486 unsigned int tx_free = tx_fifo_free(spi);
488 spi->fdx_tx_level = 0;
489 while (spi->tx_todo && tx_free) {
490 switch (spi->bits_per_word) {
498 tx16 = (u16 *) spi->tx;
504 tx32 = (u32 *) spi->tx;
515 lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
521 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
527 unsigned int rx_fill = rx_fifo_level(spi);
530 * Wait until all expected data to be shifted in.
531 * Otherwise, rx overrun may occur.
533 while (rx_fill != spi->fdx_tx_level)
534 rx_fill = rx_fifo_level(spi);
537 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
539 switch (spi->bits_per_word) {
547 rx16 = (u16 *) spi->rx;
553 rx32 = (u32 *) spi->rx;
567 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
571 unsigned int rxbv, shift;
572 unsigned int rx_fill = rx_fifo_level(spi);
575 * In RX-only mode the bits per word value is ignored by HW. A value
576 * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
577 * If remaining RX bytes are less than 4, the FIFO must be read
578 * differently. The amount of received and valid bytes is indicated
579 * by STAT.RXBV register value.
582 if (spi->rx_todo < 4) {
583 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
584 LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
585 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
587 shift = (rxbv - 1) * 8;
591 *rx8++ = (data >> shift) & 0xFF;
598 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
599 rx32 = (u32 *) spi->rx;
609 static void rx_request(struct lantiq_ssc_spi *spi)
611 unsigned int rxreq, rxreq_max;
614 * To avoid receive overflows at high clocks it is better to request
615 * only the amount of bytes that fits into all FIFOs. This value
616 * depends on the FIFO size implemented in hardware.
618 rxreq = spi->rx_todo;
619 rxreq_max = spi->rx_fifo_size * 4;
620 if (rxreq > rxreq_max)
623 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
626 static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
628 struct lantiq_ssc_spi *spi = data;
631 if (spi->rx && spi->rx_todo)
632 rx_fifo_read_full_duplex(spi);
636 else if (!tx_fifo_level(spi))
638 } else if (spi->rx) {
640 rx_fifo_read_half_duplex(spi);
654 queue_work(spi->wq, &spi->work);
659 static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
661 struct lantiq_ssc_spi *spi = data;
662 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
664 if (!(stat & LTQ_SPI_STAT_ERRORS))
667 if (stat & LTQ_SPI_STAT_RUE)
668 dev_err(spi->dev, "receive underflow error\n");
669 if (stat & LTQ_SPI_STAT_TUE)
670 dev_err(spi->dev, "transmit underflow error\n");
671 if (stat & LTQ_SPI_STAT_AE)
672 dev_err(spi->dev, "abort error\n");
673 if (stat & LTQ_SPI_STAT_RE)
674 dev_err(spi->dev, "receive overflow error\n");
675 if (stat & LTQ_SPI_STAT_TE)
676 dev_err(spi->dev, "transmit overflow error\n");
677 if (stat & LTQ_SPI_STAT_ME)
678 dev_err(spi->dev, "mode error\n");
680 /* Clear error flags */
681 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
683 /* set bad status so it can be retried */
684 if (spi->master->cur_msg)
685 spi->master->cur_msg->status = -EIO;
686 queue_work(spi->wq, &spi->work);
691 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
692 struct spi_transfer *t)
696 spin_lock_irqsave(&spi->lock, flags);
702 spi->tx_todo = t->len;
704 /* initially fill TX FIFO */
709 spi->rx_todo = t->len;
711 /* start shift clock in RX-only mode */
716 spin_unlock_irqrestore(&spi->lock, flags);
722 * The driver only gets an interrupt when the FIFO is empty, but there
723 * is an additional shift register from which the data is written to
724 * the wire. We get the last interrupt when the controller starts to
725 * write the last word to the wire, not when it is finished. Do busy
726 * waiting till it finishes.
728 static void lantiq_ssc_bussy_work(struct work_struct *work)
730 struct lantiq_ssc_spi *spi;
731 unsigned long long timeout = 8LL * 1000LL;
734 spi = container_of(work, typeof(*spi), work);
736 do_div(timeout, spi->speed_hz);
737 timeout += timeout + 100; /* some tolerance */
739 end = jiffies + msecs_to_jiffies(timeout);
741 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
743 if (!(stat & LTQ_SPI_STAT_BSY)) {
744 spi_finalize_current_transfer(spi->master);
749 } while (!time_after_eq(jiffies, end));
751 if (spi->master->cur_msg)
752 spi->master->cur_msg->status = -EIO;
753 spi_finalize_current_transfer(spi->master);
756 static void lantiq_ssc_handle_err(struct spi_master *master,
757 struct spi_message *message)
759 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
761 /* flush FIFOs on timeout */
766 static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
768 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
769 unsigned int cs = spidev->chip_select;
772 if (!!(spidev->mode & SPI_CS_HIGH) == enable)
773 fgpo = (1 << (cs - spi->base_cs));
775 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
777 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
780 static int lantiq_ssc_transfer_one(struct spi_master *master,
781 struct spi_device *spidev,
782 struct spi_transfer *t)
784 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
786 hw_setup_transfer(spi, spidev, t);
788 return transfer_start(spi, spidev, t);
791 static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
792 .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
793 .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
796 static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
797 .irnen_r = LTQ_SPI_IRNEN_R_XRX,
798 .irnen_t = LTQ_SPI_IRNEN_T_XRX,
801 static const struct of_device_id lantiq_ssc_match[] = {
802 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
803 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
804 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
807 MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
809 static int lantiq_ssc_probe(struct platform_device *pdev)
811 struct device *dev = &pdev->dev;
812 struct spi_master *master;
813 struct resource *res;
814 struct lantiq_ssc_spi *spi;
815 const struct lantiq_ssc_hwcfg *hwcfg;
816 const struct of_device_id *match;
817 int err, rx_irq, tx_irq, err_irq;
818 u32 id, supports_dma, revision;
821 match = of_match_device(lantiq_ssc_match, dev);
823 dev_err(dev, "no device match\n");
828 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 dev_err(dev, "failed to get resources\n");
834 rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
836 dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME);
840 tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
842 dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME);
846 err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
848 dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME);
852 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
856 spi = spi_master_get_devdata(master);
857 spi->master = master;
860 platform_set_drvdata(pdev, spi);
862 spi->regbase = devm_ioremap_resource(dev, res);
863 if (IS_ERR(spi->regbase)) {
864 err = PTR_ERR(spi->regbase);
868 err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
869 0, LTQ_SPI_RX_IRQ_NAME, spi);
873 err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
874 0, LTQ_SPI_TX_IRQ_NAME, spi);
878 err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
879 0, LTQ_SPI_ERR_IRQ_NAME, spi);
883 spi->spi_clk = devm_clk_get(dev, "gate");
884 if (IS_ERR(spi->spi_clk)) {
885 err = PTR_ERR(spi->spi_clk);
888 err = clk_prepare_enable(spi->spi_clk);
893 * Use the old clk_get_fpi() function on Lantiq platform, till it
894 * supports common clk.
896 #if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
897 spi->fpi_clk = clk_get_fpi();
899 spi->fpi_clk = clk_get(dev, "freq");
901 if (IS_ERR(spi->fpi_clk)) {
902 err = PTR_ERR(spi->fpi_clk);
903 goto err_clk_disable;
907 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
910 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
912 spin_lock_init(&spi->lock);
913 spi->bits_per_word = 8;
916 master->dev.of_node = pdev->dev.of_node;
917 master->num_chipselect = num_cs;
918 master->setup = lantiq_ssc_setup;
919 master->set_cs = lantiq_ssc_set_cs;
920 master->handle_err = lantiq_ssc_handle_err;
921 master->prepare_message = lantiq_ssc_prepare_message;
922 master->unprepare_message = lantiq_ssc_unprepare_message;
923 master->transfer_one = lantiq_ssc_transfer_one;
924 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
926 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
927 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
929 spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
934 INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
936 id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
937 spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
938 spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
939 supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
940 revision = id & LTQ_SPI_ID_REV_M;
942 lantiq_ssc_hw_init(spi);
945 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
946 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
948 err = devm_spi_register_master(dev, master);
950 dev_err(dev, "failed to register spi_master\n");
957 destroy_workqueue(spi->wq);
959 clk_put(spi->fpi_clk);
961 clk_disable_unprepare(spi->spi_clk);
963 spi_master_put(master);
968 static int lantiq_ssc_remove(struct platform_device *pdev)
970 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
972 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
973 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
976 hw_enter_config_mode(spi);
978 destroy_workqueue(spi->wq);
979 clk_disable_unprepare(spi->spi_clk);
980 clk_put(spi->fpi_clk);
985 static struct platform_driver lantiq_ssc_driver = {
986 .probe = lantiq_ssc_probe,
987 .remove = lantiq_ssc_remove,
989 .name = "spi-lantiq-ssc",
990 .of_match_table = lantiq_ssc_match,
993 module_platform_driver(lantiq_ssc_driver);
995 MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
996 MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
997 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
998 MODULE_LICENSE("GPL");
999 MODULE_ALIAS("platform:spi-lantiq-ssc");