2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
37 #include <linux/types.h>
39 #include <linux/of_device.h>
40 #include <linux/of_gpio.h>
42 #include <linux/platform_data/dma-imx.h>
43 #include <linux/platform_data/spi-imx.h>
45 #define DRIVER_NAME "spi_imx"
47 #define MXC_CSPIRXDATA 0x00
48 #define MXC_CSPITXDATA 0x04
49 #define MXC_CSPICTRL 0x08
50 #define MXC_CSPIINT 0x0c
51 #define MXC_RESET 0x1c
53 /* generic defines to abstract from the different register layouts */
54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
57 /* The maximum bytes that a sdma BD can transfer.*/
58 #define MAX_SDMA_BD_BYTES (1 << 15)
59 #define MX51_ECSPI_CTRL_MAX_BURST 512
61 enum spi_imx_devtype {
66 IMX35_CSPI, /* CSPI on all i.mx except above */
67 IMX51_ECSPI, /* ECSPI on i.mx51 */
68 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
73 struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
76 int (*config)(struct spi_device *);
77 void (*trigger)(struct spi_imx_data *);
78 int (*rx_available)(struct spi_imx_data *);
79 void (*reset)(struct spi_imx_data *);
81 unsigned int fifo_size;
83 enum spi_imx_devtype devtype;
87 struct spi_bitbang bitbang;
90 struct completion xfer_done;
92 unsigned long base_phys;
96 unsigned long spi_clk;
97 unsigned int spi_bus_clk;
99 unsigned int speed_hz;
100 unsigned int bits_per_word;
101 unsigned int spi_drctl;
103 unsigned int count, remainder;
104 void (*tx)(struct spi_imx_data *);
105 void (*rx)(struct spi_imx_data *);
108 unsigned int txfifo; /* number of words pushed in tx FIFO */
109 unsigned int dynamic_burst, read_u32;
110 unsigned int word_mask;
115 struct completion dma_rx_completion;
116 struct completion dma_tx_completion;
118 const struct spi_imx_devtype_data *devtype_data;
121 static inline int is_imx27_cspi(struct spi_imx_data *d)
123 return d->devtype_data->devtype == IMX27_CSPI;
126 static inline int is_imx35_cspi(struct spi_imx_data *d)
128 return d->devtype_data->devtype == IMX35_CSPI;
131 static inline int is_imx51_ecspi(struct spi_imx_data *d)
133 return d->devtype_data->devtype == IMX51_ECSPI;
136 static inline int is_imx53_ecspi(struct spi_imx_data *d)
138 return d->devtype_data->devtype == IMX53_ECSPI;
141 #define MXC_SPI_BUF_RX(type) \
142 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
146 if (spi_imx->rx_buf) { \
147 *(type *)spi_imx->rx_buf = val; \
148 spi_imx->rx_buf += sizeof(type); \
152 #define MXC_SPI_BUF_TX(type) \
153 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
157 if (spi_imx->tx_buf) { \
158 val = *(type *)spi_imx->tx_buf; \
159 spi_imx->tx_buf += sizeof(type); \
162 spi_imx->count -= sizeof(type); \
164 writel(val, spi_imx->base + MXC_CSPITXDATA); \
174 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
175 * (which is currently not the case in this driver)
177 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
178 256, 384, 512, 768, 1024};
181 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
182 unsigned int fspi, unsigned int max, unsigned int *fres)
186 for (i = 2; i < max; i++)
187 if (fspi * mxc_clkdivs[i] >= fin)
190 *fres = fin / mxc_clkdivs[i];
194 /* MX1, MX31, MX35, MX51 CSPI */
195 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
196 unsigned int fspi, unsigned int *fres)
200 for (i = 0; i < 7; i++) {
201 if (fspi * div >= fin)
211 static int spi_imx_bytes_per_word(const int bits_per_word)
213 return DIV_ROUND_UP(bits_per_word, BITS_PER_BYTE);
216 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
217 struct spi_transfer *transfer)
219 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
220 unsigned int bytes_per_word, i;
225 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
227 if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4)
230 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
231 if (!(transfer->len % (i * bytes_per_word)))
239 spi_imx->dynamic_burst = 0;
244 #define MX51_ECSPI_CTRL 0x08
245 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
246 #define MX51_ECSPI_CTRL_XCH (1 << 2)
247 #define MX51_ECSPI_CTRL_SMC (1 << 3)
248 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
249 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
250 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
251 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
252 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
253 #define MX51_ECSPI_CTRL_BL_OFFSET 20
254 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
256 #define MX51_ECSPI_CONFIG 0x0c
257 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
258 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
259 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
260 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
261 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
263 #define MX51_ECSPI_INT 0x10
264 #define MX51_ECSPI_INT_TEEN (1 << 0)
265 #define MX51_ECSPI_INT_RREN (1 << 3)
267 #define MX51_ECSPI_DMA 0x14
268 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
269 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
270 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
272 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
273 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
274 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
276 #define MX51_ECSPI_STAT 0x18
277 #define MX51_ECSPI_STAT_RR (1 << 3)
279 #define MX51_ECSPI_TESTREG 0x20
280 #define MX51_ECSPI_TESTREG_LBC BIT(31)
282 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
284 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
285 #ifdef __LITTLE_ENDIAN
286 unsigned int bytes_per_word;
289 if (spi_imx->rx_buf) {
290 #ifdef __LITTLE_ENDIAN
291 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
292 if (bytes_per_word == 1)
293 val = cpu_to_be32(val);
294 else if (bytes_per_word == 2)
295 val = (val << 16) | (val >> 16);
297 val &= spi_imx->word_mask;
298 *(u32 *)spi_imx->rx_buf = val;
299 spi_imx->rx_buf += sizeof(u32);
303 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
305 unsigned int bytes_per_word;
307 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
308 if (spi_imx->read_u32) {
309 spi_imx_buf_rx_swap_u32(spi_imx);
313 if (bytes_per_word == 1)
314 spi_imx_buf_rx_u8(spi_imx);
315 else if (bytes_per_word == 2)
316 spi_imx_buf_rx_u16(spi_imx);
319 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
322 #ifdef __LITTLE_ENDIAN
323 unsigned int bytes_per_word;
326 if (spi_imx->tx_buf) {
327 val = *(u32 *)spi_imx->tx_buf;
328 val &= spi_imx->word_mask;
329 spi_imx->tx_buf += sizeof(u32);
332 spi_imx->count -= sizeof(u32);
333 #ifdef __LITTLE_ENDIAN
334 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
336 if (bytes_per_word == 1)
337 val = cpu_to_be32(val);
338 else if (bytes_per_word == 2)
339 val = (val << 16) | (val >> 16);
341 writel(val, spi_imx->base + MXC_CSPITXDATA);
344 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
347 unsigned int bytes_per_word;
349 if (spi_imx->count == spi_imx->remainder) {
350 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
351 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
352 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) {
353 spi_imx->remainder = spi_imx->count %
354 MX51_ECSPI_CTRL_MAX_BURST;
355 val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1;
356 } else if (spi_imx->count >= sizeof(u32)) {
357 spi_imx->remainder = spi_imx->count % sizeof(u32);
358 val = (spi_imx->count - spi_imx->remainder) * 8 - 1;
360 spi_imx->remainder = 0;
361 val = spi_imx->bits_per_word - 1;
362 spi_imx->read_u32 = 0;
365 ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET);
366 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
369 if (spi_imx->count >= sizeof(u32)) {
370 spi_imx_buf_tx_swap_u32(spi_imx);
374 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
376 if (bytes_per_word == 1)
377 spi_imx_buf_tx_u8(spi_imx);
378 else if (bytes_per_word == 2)
379 spi_imx_buf_tx_u16(spi_imx);
383 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
384 unsigned int fspi, unsigned int *fres)
387 * there are two 4-bit dividers, the pre-divider divides by
388 * $pre, the post-divider by 2^$post
390 unsigned int pre, post;
391 unsigned int fin = spi_imx->spi_clk;
393 if (unlikely(fspi > fin))
396 post = fls(fin) - fls(fspi);
397 if (fin > fspi << post)
400 /* now we have: (fin <= fspi << post) with post being minimal */
402 post = max(4U, post) - 4;
403 if (unlikely(post > 0xf)) {
404 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
409 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
411 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
412 __func__, fin, fspi, post, pre);
414 /* Resulting frequency for the SCLK line. */
415 *fres = (fin / (pre + 1)) >> post;
417 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
418 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
421 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
425 if (enable & MXC_INT_TE)
426 val |= MX51_ECSPI_INT_TEEN;
428 if (enable & MXC_INT_RR)
429 val |= MX51_ECSPI_INT_RREN;
431 writel(val, spi_imx->base + MX51_ECSPI_INT);
434 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
438 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
439 reg |= MX51_ECSPI_CTRL_XCH;
440 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
443 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
444 struct spi_message *msg)
446 struct spi_device *spi = msg->spi;
447 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
449 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
452 * The hardware seems to have a race condition when changing modes. The
453 * current assumption is that the selection of the channel arrives
454 * earlier in the hardware than the mode bits when they are written at
456 * So set master mode for all channels as we do not support slave mode.
458 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
461 * Enable SPI_RDY handling (falling edge/level triggered).
463 if (spi->mode & SPI_READY)
464 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
466 /* set chip select to use */
467 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
470 * The ctrl register must be written first, with the EN bit set other
471 * registers must not be written to.
473 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
475 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
476 if (spi->mode & SPI_LOOP)
477 testreg |= MX51_ECSPI_TESTREG_LBC;
479 testreg &= ~MX51_ECSPI_TESTREG_LBC;
480 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
482 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
484 if (spi->mode & SPI_CPHA)
485 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
487 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
489 if (spi->mode & SPI_CPOL) {
490 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
491 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
493 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
494 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
497 if (spi->mode & SPI_CS_HIGH)
498 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
500 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
502 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
507 static int mx51_ecspi_config(struct spi_device *spi)
509 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
510 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
511 u32 clk = spi_imx->speed_hz, delay;
513 /* Clear BL field and set the right value */
514 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
515 ctrl |= (spi_imx->bits_per_word - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
517 /* set clock speed */
518 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
519 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
520 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
521 spi_imx->spi_bus_clk = clk;
524 ctrl |= MX51_ECSPI_CTRL_SMC;
526 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
529 * Wait until the changes in the configuration register CONFIGREG
530 * propagate into the hardware. It takes exactly one tick of the
531 * SCLK clock, but we will wait two SCLK clock just to be sure. The
532 * effect of the delay it takes for the hardware to apply changes
533 * is noticable if the SCLK clock run very slow. In such a case, if
534 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
535 * be asserted before the SCLK polarity changes, which would disrupt
536 * the SPI communication as the device on the other end would consider
537 * the change of SCLK polarity as a clock tick already.
539 delay = (2 * 1000000) / clk;
540 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
542 else /* SCLK is _very_ slow */
543 usleep_range(delay, delay + 10);
546 * Configure the DMA register: setup the watermark
547 * and enable DMA request.
549 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
550 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
551 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
552 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
553 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
558 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
560 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
563 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
565 /* drain receive buffer */
566 while (mx51_ecspi_rx_available(spi_imx))
567 readl(spi_imx->base + MXC_CSPIRXDATA);
570 #define MX31_INTREG_TEEN (1 << 0)
571 #define MX31_INTREG_RREN (1 << 3)
573 #define MX31_CSPICTRL_ENABLE (1 << 0)
574 #define MX31_CSPICTRL_MASTER (1 << 1)
575 #define MX31_CSPICTRL_XCH (1 << 2)
576 #define MX31_CSPICTRL_SMC (1 << 3)
577 #define MX31_CSPICTRL_POL (1 << 4)
578 #define MX31_CSPICTRL_PHA (1 << 5)
579 #define MX31_CSPICTRL_SSCTL (1 << 6)
580 #define MX31_CSPICTRL_SSPOL (1 << 7)
581 #define MX31_CSPICTRL_BC_SHIFT 8
582 #define MX35_CSPICTRL_BL_SHIFT 20
583 #define MX31_CSPICTRL_CS_SHIFT 24
584 #define MX35_CSPICTRL_CS_SHIFT 12
585 #define MX31_CSPICTRL_DR_SHIFT 16
587 #define MX31_CSPI_DMAREG 0x10
588 #define MX31_DMAREG_RH_DEN (1<<4)
589 #define MX31_DMAREG_TH_DEN (1<<1)
591 #define MX31_CSPISTATUS 0x14
592 #define MX31_STATUS_RR (1 << 3)
594 #define MX31_CSPI_TESTREG 0x1C
595 #define MX31_TEST_LBC (1 << 14)
597 /* These functions also work for the i.MX35, but be aware that
598 * the i.MX35 has a slightly different register layout for bits
599 * we do not use here.
601 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
603 unsigned int val = 0;
605 if (enable & MXC_INT_TE)
606 val |= MX31_INTREG_TEEN;
607 if (enable & MXC_INT_RR)
608 val |= MX31_INTREG_RREN;
610 writel(val, spi_imx->base + MXC_CSPIINT);
613 static void mx31_trigger(struct spi_imx_data *spi_imx)
617 reg = readl(spi_imx->base + MXC_CSPICTRL);
618 reg |= MX31_CSPICTRL_XCH;
619 writel(reg, spi_imx->base + MXC_CSPICTRL);
622 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
623 struct spi_message *msg)
628 static int mx31_config(struct spi_device *spi)
630 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
631 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
634 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
635 MX31_CSPICTRL_DR_SHIFT;
636 spi_imx->spi_bus_clk = clk;
638 if (is_imx35_cspi(spi_imx)) {
639 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
640 reg |= MX31_CSPICTRL_SSCTL;
642 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
645 if (spi->mode & SPI_CPHA)
646 reg |= MX31_CSPICTRL_PHA;
647 if (spi->mode & SPI_CPOL)
648 reg |= MX31_CSPICTRL_POL;
649 if (spi->mode & SPI_CS_HIGH)
650 reg |= MX31_CSPICTRL_SSPOL;
651 if (!gpio_is_valid(spi->cs_gpio))
652 reg |= (spi->chip_select) <<
653 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
654 MX31_CSPICTRL_CS_SHIFT);
657 reg |= MX31_CSPICTRL_SMC;
659 writel(reg, spi_imx->base + MXC_CSPICTRL);
661 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
662 if (spi->mode & SPI_LOOP)
663 reg |= MX31_TEST_LBC;
665 reg &= ~MX31_TEST_LBC;
666 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
668 if (spi_imx->usedma) {
669 /* configure DMA requests when RXFIFO is half full and
670 when TXFIFO is half empty */
671 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
672 spi_imx->base + MX31_CSPI_DMAREG);
678 static int mx31_rx_available(struct spi_imx_data *spi_imx)
680 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
683 static void mx31_reset(struct spi_imx_data *spi_imx)
685 /* drain receive buffer */
686 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
687 readl(spi_imx->base + MXC_CSPIRXDATA);
690 #define MX21_INTREG_RR (1 << 4)
691 #define MX21_INTREG_TEEN (1 << 9)
692 #define MX21_INTREG_RREN (1 << 13)
694 #define MX21_CSPICTRL_POL (1 << 5)
695 #define MX21_CSPICTRL_PHA (1 << 6)
696 #define MX21_CSPICTRL_SSPOL (1 << 8)
697 #define MX21_CSPICTRL_XCH (1 << 9)
698 #define MX21_CSPICTRL_ENABLE (1 << 10)
699 #define MX21_CSPICTRL_MASTER (1 << 11)
700 #define MX21_CSPICTRL_DR_SHIFT 14
701 #define MX21_CSPICTRL_CS_SHIFT 19
703 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
705 unsigned int val = 0;
707 if (enable & MXC_INT_TE)
708 val |= MX21_INTREG_TEEN;
709 if (enable & MXC_INT_RR)
710 val |= MX21_INTREG_RREN;
712 writel(val, spi_imx->base + MXC_CSPIINT);
715 static void mx21_trigger(struct spi_imx_data *spi_imx)
719 reg = readl(spi_imx->base + MXC_CSPICTRL);
720 reg |= MX21_CSPICTRL_XCH;
721 writel(reg, spi_imx->base + MXC_CSPICTRL);
724 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
725 struct spi_message *msg)
730 static int mx21_config(struct spi_device *spi)
732 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
733 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
734 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
737 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
738 << MX21_CSPICTRL_DR_SHIFT;
739 spi_imx->spi_bus_clk = clk;
741 reg |= spi_imx->bits_per_word - 1;
743 if (spi->mode & SPI_CPHA)
744 reg |= MX21_CSPICTRL_PHA;
745 if (spi->mode & SPI_CPOL)
746 reg |= MX21_CSPICTRL_POL;
747 if (spi->mode & SPI_CS_HIGH)
748 reg |= MX21_CSPICTRL_SSPOL;
749 if (!gpio_is_valid(spi->cs_gpio))
750 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
752 writel(reg, spi_imx->base + MXC_CSPICTRL);
757 static int mx21_rx_available(struct spi_imx_data *spi_imx)
759 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
762 static void mx21_reset(struct spi_imx_data *spi_imx)
764 writel(1, spi_imx->base + MXC_RESET);
767 #define MX1_INTREG_RR (1 << 3)
768 #define MX1_INTREG_TEEN (1 << 8)
769 #define MX1_INTREG_RREN (1 << 11)
771 #define MX1_CSPICTRL_POL (1 << 4)
772 #define MX1_CSPICTRL_PHA (1 << 5)
773 #define MX1_CSPICTRL_XCH (1 << 8)
774 #define MX1_CSPICTRL_ENABLE (1 << 9)
775 #define MX1_CSPICTRL_MASTER (1 << 10)
776 #define MX1_CSPICTRL_DR_SHIFT 13
778 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
780 unsigned int val = 0;
782 if (enable & MXC_INT_TE)
783 val |= MX1_INTREG_TEEN;
784 if (enable & MXC_INT_RR)
785 val |= MX1_INTREG_RREN;
787 writel(val, spi_imx->base + MXC_CSPIINT);
790 static void mx1_trigger(struct spi_imx_data *spi_imx)
794 reg = readl(spi_imx->base + MXC_CSPICTRL);
795 reg |= MX1_CSPICTRL_XCH;
796 writel(reg, spi_imx->base + MXC_CSPICTRL);
799 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
800 struct spi_message *msg)
805 static int mx1_config(struct spi_device *spi)
807 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
808 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
811 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
812 MX1_CSPICTRL_DR_SHIFT;
813 spi_imx->spi_bus_clk = clk;
815 reg |= spi_imx->bits_per_word - 1;
817 if (spi->mode & SPI_CPHA)
818 reg |= MX1_CSPICTRL_PHA;
819 if (spi->mode & SPI_CPOL)
820 reg |= MX1_CSPICTRL_POL;
822 writel(reg, spi_imx->base + MXC_CSPICTRL);
827 static int mx1_rx_available(struct spi_imx_data *spi_imx)
829 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
832 static void mx1_reset(struct spi_imx_data *spi_imx)
834 writel(1, spi_imx->base + MXC_RESET);
837 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
838 .intctrl = mx1_intctrl,
839 .prepare_message = mx1_prepare_message,
840 .config = mx1_config,
841 .trigger = mx1_trigger,
842 .rx_available = mx1_rx_available,
845 .has_dmamode = false,
846 .dynamic_burst = false,
847 .devtype = IMX1_CSPI,
850 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
851 .intctrl = mx21_intctrl,
852 .prepare_message = mx21_prepare_message,
853 .config = mx21_config,
854 .trigger = mx21_trigger,
855 .rx_available = mx21_rx_available,
858 .has_dmamode = false,
859 .dynamic_burst = false,
860 .devtype = IMX21_CSPI,
863 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
864 /* i.mx27 cspi shares the functions with i.mx21 one */
865 .intctrl = mx21_intctrl,
866 .prepare_message = mx21_prepare_message,
867 .config = mx21_config,
868 .trigger = mx21_trigger,
869 .rx_available = mx21_rx_available,
872 .has_dmamode = false,
873 .dynamic_burst = false,
874 .devtype = IMX27_CSPI,
877 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
878 .intctrl = mx31_intctrl,
879 .prepare_message = mx31_prepare_message,
880 .config = mx31_config,
881 .trigger = mx31_trigger,
882 .rx_available = mx31_rx_available,
885 .has_dmamode = false,
886 .dynamic_burst = false,
887 .devtype = IMX31_CSPI,
890 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
891 /* i.mx35 and later cspi shares the functions with i.mx31 one */
892 .intctrl = mx31_intctrl,
893 .prepare_message = mx31_prepare_message,
894 .config = mx31_config,
895 .trigger = mx31_trigger,
896 .rx_available = mx31_rx_available,
900 .dynamic_burst = false,
901 .devtype = IMX35_CSPI,
904 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
905 .intctrl = mx51_ecspi_intctrl,
906 .prepare_message = mx51_ecspi_prepare_message,
907 .config = mx51_ecspi_config,
908 .trigger = mx51_ecspi_trigger,
909 .rx_available = mx51_ecspi_rx_available,
910 .reset = mx51_ecspi_reset,
913 .dynamic_burst = true,
914 .devtype = IMX51_ECSPI,
917 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
918 .intctrl = mx51_ecspi_intctrl,
919 .prepare_message = mx51_ecspi_prepare_message,
920 .config = mx51_ecspi_config,
921 .trigger = mx51_ecspi_trigger,
922 .rx_available = mx51_ecspi_rx_available,
923 .reset = mx51_ecspi_reset,
926 .devtype = IMX53_ECSPI,
929 static const struct platform_device_id spi_imx_devtype[] = {
932 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
934 .name = "imx21-cspi",
935 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
937 .name = "imx27-cspi",
938 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
940 .name = "imx31-cspi",
941 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
943 .name = "imx35-cspi",
944 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
946 .name = "imx51-ecspi",
947 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
949 .name = "imx53-ecspi",
950 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
956 static const struct of_device_id spi_imx_dt_ids[] = {
957 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
958 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
959 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
960 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
961 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
962 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
963 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
966 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
968 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
970 int active = is_active != BITBANG_CS_INACTIVE;
971 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
973 if (spi->mode & SPI_NO_CS)
976 if (!gpio_is_valid(spi->cs_gpio))
979 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
982 static void spi_imx_push(struct spi_imx_data *spi_imx)
984 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
987 if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder))
989 spi_imx->tx(spi_imx);
993 spi_imx->devtype_data->trigger(spi_imx);
996 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
998 struct spi_imx_data *spi_imx = dev_id;
1000 while (spi_imx->devtype_data->rx_available(spi_imx)) {
1001 spi_imx->rx(spi_imx);
1005 if (spi_imx->count) {
1006 spi_imx_push(spi_imx);
1010 if (spi_imx->txfifo) {
1011 /* No data left to push, but still waiting for rx data,
1012 * enable receive data available interrupt.
1014 spi_imx->devtype_data->intctrl(
1015 spi_imx, MXC_INT_RR);
1019 spi_imx->devtype_data->intctrl(spi_imx, 0);
1020 complete(&spi_imx->xfer_done);
1025 static int spi_imx_dma_configure(struct spi_master *master)
1028 enum dma_slave_buswidth buswidth;
1029 struct dma_slave_config rx = {}, tx = {};
1030 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1032 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1034 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1037 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1040 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1046 tx.direction = DMA_MEM_TO_DEV;
1047 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1048 tx.dst_addr_width = buswidth;
1049 tx.dst_maxburst = spi_imx->wml;
1050 ret = dmaengine_slave_config(master->dma_tx, &tx);
1052 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1056 rx.direction = DMA_DEV_TO_MEM;
1057 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1058 rx.src_addr_width = buswidth;
1059 rx.src_maxburst = spi_imx->wml;
1060 ret = dmaengine_slave_config(master->dma_rx, &rx);
1062 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1069 static int spi_imx_setupxfer(struct spi_device *spi,
1070 struct spi_transfer *t)
1072 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1078 spi_imx->bits_per_word = t->bits_per_word;
1079 spi_imx->speed_hz = t->speed_hz;
1081 /* Initialize the functions for transfer */
1082 if (spi_imx->devtype_data->dynamic_burst) {
1085 spi_imx->dynamic_burst = 0;
1086 spi_imx->remainder = 0;
1087 spi_imx->read_u32 = 1;
1089 mask = (1 << spi_imx->bits_per_word) - 1;
1090 spi_imx->rx = spi_imx_buf_rx_swap;
1091 spi_imx->tx = spi_imx_buf_tx_swap;
1092 spi_imx->dynamic_burst = 1;
1093 spi_imx->remainder = t->len;
1095 if (spi_imx->bits_per_word <= 8)
1096 spi_imx->word_mask = mask << 24 | mask << 16
1098 else if (spi_imx->bits_per_word <= 16)
1099 spi_imx->word_mask = mask << 16 | mask;
1101 spi_imx->word_mask = mask;
1103 if (spi_imx->bits_per_word <= 8) {
1104 spi_imx->rx = spi_imx_buf_rx_u8;
1105 spi_imx->tx = spi_imx_buf_tx_u8;
1106 } else if (spi_imx->bits_per_word <= 16) {
1107 spi_imx->rx = spi_imx_buf_rx_u16;
1108 spi_imx->tx = spi_imx_buf_tx_u16;
1110 spi_imx->rx = spi_imx_buf_rx_u32;
1111 spi_imx->tx = spi_imx_buf_tx_u32;
1115 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1116 spi_imx->usedma = 1;
1118 spi_imx->usedma = 0;
1120 if (spi_imx->usedma) {
1121 ret = spi_imx_dma_configure(spi->master);
1126 spi_imx->devtype_data->config(spi);
1131 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1133 struct spi_master *master = spi_imx->bitbang.master;
1135 if (master->dma_rx) {
1136 dma_release_channel(master->dma_rx);
1137 master->dma_rx = NULL;
1140 if (master->dma_tx) {
1141 dma_release_channel(master->dma_tx);
1142 master->dma_tx = NULL;
1146 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1147 struct spi_master *master)
1151 /* use pio mode for i.mx6dl chip TKT238285 */
1152 if (of_machine_is_compatible("fsl,imx6dl"))
1155 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1157 /* Prepare for TX DMA: */
1158 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1159 if (IS_ERR(master->dma_tx)) {
1160 ret = PTR_ERR(master->dma_tx);
1161 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1162 master->dma_tx = NULL;
1166 /* Prepare for RX : */
1167 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1168 if (IS_ERR(master->dma_rx)) {
1169 ret = PTR_ERR(master->dma_rx);
1170 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1171 master->dma_rx = NULL;
1175 init_completion(&spi_imx->dma_rx_completion);
1176 init_completion(&spi_imx->dma_tx_completion);
1177 master->can_dma = spi_imx_can_dma;
1178 master->max_dma_len = MAX_SDMA_BD_BYTES;
1179 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1184 spi_imx_sdma_exit(spi_imx);
1188 static void spi_imx_dma_rx_callback(void *cookie)
1190 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1192 complete(&spi_imx->dma_rx_completion);
1195 static void spi_imx_dma_tx_callback(void *cookie)
1197 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1199 complete(&spi_imx->dma_tx_completion);
1202 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1204 unsigned long timeout = 0;
1206 /* Time with actual data transfer and CS change delay related to HW */
1207 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1209 /* Add extra second for scheduler related activities */
1212 /* Double calculated timeout */
1213 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1216 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1217 struct spi_transfer *transfer)
1219 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1220 unsigned long transfer_timeout;
1221 unsigned long timeout;
1222 struct spi_master *master = spi_imx->bitbang.master;
1223 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1226 * The TX DMA setup starts the transfer, so make sure RX is configured
1229 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1230 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1231 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1235 desc_rx->callback = spi_imx_dma_rx_callback;
1236 desc_rx->callback_param = (void *)spi_imx;
1237 dmaengine_submit(desc_rx);
1238 reinit_completion(&spi_imx->dma_rx_completion);
1239 dma_async_issue_pending(master->dma_rx);
1241 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1242 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1243 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1245 dmaengine_terminate_all(master->dma_tx);
1249 desc_tx->callback = spi_imx_dma_tx_callback;
1250 desc_tx->callback_param = (void *)spi_imx;
1251 dmaengine_submit(desc_tx);
1252 reinit_completion(&spi_imx->dma_tx_completion);
1253 dma_async_issue_pending(master->dma_tx);
1255 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1257 /* Wait SDMA to finish the data transfer.*/
1258 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1261 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1262 dmaengine_terminate_all(master->dma_tx);
1263 dmaengine_terminate_all(master->dma_rx);
1267 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1270 dev_err(&master->dev, "I/O Error in DMA RX\n");
1271 spi_imx->devtype_data->reset(spi_imx);
1272 dmaengine_terminate_all(master->dma_rx);
1276 return transfer->len;
1279 static int spi_imx_pio_transfer(struct spi_device *spi,
1280 struct spi_transfer *transfer)
1282 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1283 unsigned long transfer_timeout;
1284 unsigned long timeout;
1286 spi_imx->tx_buf = transfer->tx_buf;
1287 spi_imx->rx_buf = transfer->rx_buf;
1288 spi_imx->count = transfer->len;
1289 spi_imx->txfifo = 0;
1291 reinit_completion(&spi_imx->xfer_done);
1293 spi_imx_push(spi_imx);
1295 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1297 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1299 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1302 dev_err(&spi->dev, "I/O Error in PIO\n");
1303 spi_imx->devtype_data->reset(spi_imx);
1307 return transfer->len;
1310 static int spi_imx_transfer(struct spi_device *spi,
1311 struct spi_transfer *transfer)
1313 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1315 if (spi_imx->usedma)
1316 return spi_imx_dma_transfer(spi_imx, transfer);
1318 return spi_imx_pio_transfer(spi, transfer);
1321 static int spi_imx_setup(struct spi_device *spi)
1323 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1324 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1326 if (spi->mode & SPI_NO_CS)
1329 if (gpio_is_valid(spi->cs_gpio))
1330 gpio_direction_output(spi->cs_gpio,
1331 spi->mode & SPI_CS_HIGH ? 0 : 1);
1333 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1338 static void spi_imx_cleanup(struct spi_device *spi)
1343 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1345 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1348 ret = clk_enable(spi_imx->clk_per);
1352 ret = clk_enable(spi_imx->clk_ipg);
1354 clk_disable(spi_imx->clk_per);
1358 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1360 clk_disable(spi_imx->clk_ipg);
1361 clk_disable(spi_imx->clk_per);
1368 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1370 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1372 clk_disable(spi_imx->clk_ipg);
1373 clk_disable(spi_imx->clk_per);
1377 static int spi_imx_probe(struct platform_device *pdev)
1379 struct device_node *np = pdev->dev.of_node;
1380 const struct of_device_id *of_id =
1381 of_match_device(spi_imx_dt_ids, &pdev->dev);
1382 struct spi_imx_master *mxc_platform_info =
1383 dev_get_platdata(&pdev->dev);
1384 struct spi_master *master;
1385 struct spi_imx_data *spi_imx;
1386 struct resource *res;
1387 int i, ret, irq, spi_drctl;
1389 if (!np && !mxc_platform_info) {
1390 dev_err(&pdev->dev, "can't get the platform data\n");
1394 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
1398 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1399 if ((ret < 0) || (spi_drctl >= 0x3)) {
1400 /* '11' is reserved */
1404 platform_set_drvdata(pdev, master);
1406 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1407 master->bus_num = np ? -1 : pdev->id;
1409 spi_imx = spi_master_get_devdata(master);
1410 spi_imx->bitbang.master = master;
1411 spi_imx->dev = &pdev->dev;
1413 spi_imx->devtype_data = of_id ? of_id->data :
1414 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1416 if (mxc_platform_info) {
1417 master->num_chipselect = mxc_platform_info->num_chipselect;
1418 master->cs_gpios = devm_kzalloc(&master->dev,
1419 sizeof(int) * master->num_chipselect, GFP_KERNEL);
1420 if (!master->cs_gpios)
1423 for (i = 0; i < master->num_chipselect; i++)
1424 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1427 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1428 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1429 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1430 spi_imx->bitbang.master->setup = spi_imx_setup;
1431 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1432 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1433 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1434 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1436 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1437 is_imx53_ecspi(spi_imx))
1438 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1440 spi_imx->spi_drctl = spi_drctl;
1442 init_completion(&spi_imx->xfer_done);
1444 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1445 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1446 if (IS_ERR(spi_imx->base)) {
1447 ret = PTR_ERR(spi_imx->base);
1448 goto out_master_put;
1450 spi_imx->base_phys = res->start;
1452 irq = platform_get_irq(pdev, 0);
1455 goto out_master_put;
1458 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1459 dev_name(&pdev->dev), spi_imx);
1461 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1462 goto out_master_put;
1465 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1466 if (IS_ERR(spi_imx->clk_ipg)) {
1467 ret = PTR_ERR(spi_imx->clk_ipg);
1468 goto out_master_put;
1471 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1472 if (IS_ERR(spi_imx->clk_per)) {
1473 ret = PTR_ERR(spi_imx->clk_per);
1474 goto out_master_put;
1477 ret = clk_prepare_enable(spi_imx->clk_per);
1479 goto out_master_put;
1481 ret = clk_prepare_enable(spi_imx->clk_ipg);
1485 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1487 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1488 * if validated on other chips.
1490 if (spi_imx->devtype_data->has_dmamode) {
1491 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1492 if (ret == -EPROBE_DEFER)
1496 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1500 spi_imx->devtype_data->reset(spi_imx);
1502 spi_imx->devtype_data->intctrl(spi_imx, 0);
1504 master->dev.of_node = pdev->dev.of_node;
1505 ret = spi_bitbang_start(&spi_imx->bitbang);
1507 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1511 if (!master->cs_gpios) {
1512 dev_err(&pdev->dev, "No CS GPIOs available\n");
1517 for (i = 0; i < master->num_chipselect; i++) {
1518 if (!gpio_is_valid(master->cs_gpios[i]))
1521 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1524 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1525 master->cs_gpios[i]);
1530 dev_info(&pdev->dev, "probed\n");
1532 clk_disable(spi_imx->clk_ipg);
1533 clk_disable(spi_imx->clk_per);
1537 clk_disable_unprepare(spi_imx->clk_ipg);
1539 clk_disable_unprepare(spi_imx->clk_per);
1541 spi_master_put(master);
1546 static int spi_imx_remove(struct platform_device *pdev)
1548 struct spi_master *master = platform_get_drvdata(pdev);
1549 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1552 spi_bitbang_stop(&spi_imx->bitbang);
1554 ret = clk_enable(spi_imx->clk_per);
1558 ret = clk_enable(spi_imx->clk_ipg);
1560 clk_disable(spi_imx->clk_per);
1564 writel(0, spi_imx->base + MXC_CSPICTRL);
1565 clk_disable_unprepare(spi_imx->clk_ipg);
1566 clk_disable_unprepare(spi_imx->clk_per);
1567 spi_imx_sdma_exit(spi_imx);
1568 spi_master_put(master);
1573 static struct platform_driver spi_imx_driver = {
1575 .name = DRIVER_NAME,
1576 .of_match_table = spi_imx_dt_ids,
1578 .id_table = spi_imx_devtype,
1579 .probe = spi_imx_probe,
1580 .remove = spi_imx_remove,
1582 module_platform_driver(spi_imx_driver);
1584 MODULE_DESCRIPTION("SPI Master Controller driver");
1585 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1586 MODULE_LICENSE("GPL");
1587 MODULE_ALIAS("platform:" DRIVER_NAME);