1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/types.h>
24 #include <linux/of_device.h>
25 #include <linux/property.h>
27 #include <linux/platform_data/dma-imx.h>
29 #define DRIVER_NAME "spi_imx"
31 static bool use_dma = true;
32 module_param(use_dma, bool, 0644);
33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
35 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
37 #define MXC_CSPIRXDATA 0x00
38 #define MXC_CSPITXDATA 0x04
39 #define MXC_CSPICTRL 0x08
40 #define MXC_CSPIINT 0x0c
41 #define MXC_RESET 0x1c
43 /* generic defines to abstract from the different register layouts */
44 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
45 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
46 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
48 /* The maximum bytes that a sdma BD can transfer. */
49 #define MAX_SDMA_BD_BYTES (1 << 15)
50 #define MX51_ECSPI_CTRL_MAX_BURST 512
51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
52 #define MX53_MAX_TRANSFER_BYTES 512
54 enum spi_imx_devtype {
59 IMX35_CSPI, /* CSPI on all i.mx except above */
60 IMX51_ECSPI, /* ECSPI on i.mx51 */
61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
66 struct spi_imx_devtype_data {
67 void (*intctrl)(struct spi_imx_data *, int);
68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
70 void (*trigger)(struct spi_imx_data *);
71 int (*rx_available)(struct spi_imx_data *);
72 void (*reset)(struct spi_imx_data *);
73 void (*setup_wml)(struct spi_imx_data *);
74 void (*disable)(struct spi_imx_data *);
75 void (*disable_dma)(struct spi_imx_data *);
78 unsigned int fifo_size;
80 enum spi_imx_devtype devtype;
84 struct spi_bitbang bitbang;
87 struct completion xfer_done;
89 unsigned long base_phys;
93 unsigned long spi_clk;
94 unsigned int spi_bus_clk;
96 unsigned int bits_per_word;
97 unsigned int spi_drctl;
99 unsigned int count, remainder;
100 void (*tx)(struct spi_imx_data *);
101 void (*rx)(struct spi_imx_data *);
104 unsigned int txfifo; /* number of words pushed in tx FIFO */
105 unsigned int dynamic_burst;
110 unsigned int slave_burst;
115 struct completion dma_rx_completion;
116 struct completion dma_tx_completion;
118 const struct spi_imx_devtype_data *devtype_data;
121 static inline int is_imx27_cspi(struct spi_imx_data *d)
123 return d->devtype_data->devtype == IMX27_CSPI;
126 static inline int is_imx35_cspi(struct spi_imx_data *d)
128 return d->devtype_data->devtype == IMX35_CSPI;
131 static inline int is_imx51_ecspi(struct spi_imx_data *d)
133 return d->devtype_data->devtype == IMX51_ECSPI;
136 static inline int is_imx53_ecspi(struct spi_imx_data *d)
138 return d->devtype_data->devtype == IMX53_ECSPI;
141 #define MXC_SPI_BUF_RX(type) \
142 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
146 if (spi_imx->rx_buf) { \
147 *(type *)spi_imx->rx_buf = val; \
148 spi_imx->rx_buf += sizeof(type); \
151 spi_imx->remainder -= sizeof(type); \
154 #define MXC_SPI_BUF_TX(type) \
155 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
159 if (spi_imx->tx_buf) { \
160 val = *(type *)spi_imx->tx_buf; \
161 spi_imx->tx_buf += sizeof(type); \
164 spi_imx->count -= sizeof(type); \
166 writel(val, spi_imx->base + MXC_CSPITXDATA); \
176 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
177 * (which is currently not the case in this driver)
179 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
180 256, 384, 512, 768, 1024};
183 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
184 unsigned int fspi, unsigned int max, unsigned int *fres)
188 for (i = 2; i < max; i++)
189 if (fspi * mxc_clkdivs[i] >= fin)
192 *fres = fin / mxc_clkdivs[i];
196 /* MX1, MX31, MX35, MX51 CSPI */
197 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
198 unsigned int fspi, unsigned int *fres)
202 for (i = 0; i < 7; i++) {
203 if (fspi * div >= fin)
213 static int spi_imx_bytes_per_word(const int bits_per_word)
215 if (bits_per_word <= 8)
217 else if (bits_per_word <= 16)
223 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
224 struct spi_transfer *transfer)
226 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
228 if (!use_dma || master->fallback)
234 if (spi_imx->slave_mode)
237 if (transfer->len < spi_imx->devtype_data->fifo_size)
240 spi_imx->dynamic_burst = 0;
245 #define MX51_ECSPI_CTRL 0x08
246 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
247 #define MX51_ECSPI_CTRL_XCH (1 << 2)
248 #define MX51_ECSPI_CTRL_SMC (1 << 3)
249 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
250 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
251 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
252 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
253 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
254 #define MX51_ECSPI_CTRL_BL_OFFSET 20
255 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
257 #define MX51_ECSPI_CONFIG 0x0c
258 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
259 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
260 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
261 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
262 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
264 #define MX51_ECSPI_INT 0x10
265 #define MX51_ECSPI_INT_TEEN (1 << 0)
266 #define MX51_ECSPI_INT_RREN (1 << 3)
267 #define MX51_ECSPI_INT_RDREN (1 << 4)
269 #define MX51_ECSPI_DMA 0x14
270 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
271 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
272 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
274 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
275 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
276 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
278 #define MX51_ECSPI_STAT 0x18
279 #define MX51_ECSPI_STAT_RR (1 << 3)
281 #define MX51_ECSPI_TESTREG 0x20
282 #define MX51_ECSPI_TESTREG_LBC BIT(31)
284 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
286 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
287 #ifdef __LITTLE_ENDIAN
288 unsigned int bytes_per_word;
291 if (spi_imx->rx_buf) {
292 #ifdef __LITTLE_ENDIAN
293 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
294 if (bytes_per_word == 1)
295 val = cpu_to_be32(val);
296 else if (bytes_per_word == 2)
297 val = (val << 16) | (val >> 16);
299 *(u32 *)spi_imx->rx_buf = val;
300 spi_imx->rx_buf += sizeof(u32);
303 spi_imx->remainder -= sizeof(u32);
306 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
311 unaligned = spi_imx->remainder % 4;
314 spi_imx_buf_rx_swap_u32(spi_imx);
318 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
319 spi_imx_buf_rx_u16(spi_imx);
323 val = readl(spi_imx->base + MXC_CSPIRXDATA);
325 while (unaligned--) {
326 if (spi_imx->rx_buf) {
327 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
330 spi_imx->remainder--;
334 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
337 #ifdef __LITTLE_ENDIAN
338 unsigned int bytes_per_word;
341 if (spi_imx->tx_buf) {
342 val = *(u32 *)spi_imx->tx_buf;
343 spi_imx->tx_buf += sizeof(u32);
346 spi_imx->count -= sizeof(u32);
347 #ifdef __LITTLE_ENDIAN
348 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
350 if (bytes_per_word == 1)
351 val = cpu_to_be32(val);
352 else if (bytes_per_word == 2)
353 val = (val << 16) | (val >> 16);
355 writel(val, spi_imx->base + MXC_CSPITXDATA);
358 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
363 unaligned = spi_imx->count % 4;
366 spi_imx_buf_tx_swap_u32(spi_imx);
370 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
371 spi_imx_buf_tx_u16(spi_imx);
375 while (unaligned--) {
376 if (spi_imx->tx_buf) {
377 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
383 writel(val, spi_imx->base + MXC_CSPITXDATA);
386 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
388 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
390 if (spi_imx->rx_buf) {
391 int n_bytes = spi_imx->slave_burst % sizeof(val);
394 n_bytes = sizeof(val);
396 memcpy(spi_imx->rx_buf,
397 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
399 spi_imx->rx_buf += n_bytes;
400 spi_imx->slave_burst -= n_bytes;
403 spi_imx->remainder -= sizeof(u32);
406 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
409 int n_bytes = spi_imx->count % sizeof(val);
412 n_bytes = sizeof(val);
414 if (spi_imx->tx_buf) {
415 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
416 spi_imx->tx_buf, n_bytes);
417 val = cpu_to_be32(val);
418 spi_imx->tx_buf += n_bytes;
421 spi_imx->count -= n_bytes;
423 writel(val, spi_imx->base + MXC_CSPITXDATA);
427 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
428 unsigned int fspi, unsigned int *fres)
431 * there are two 4-bit dividers, the pre-divider divides by
432 * $pre, the post-divider by 2^$post
434 unsigned int pre, post;
435 unsigned int fin = spi_imx->spi_clk;
437 if (unlikely(fspi > fin))
440 post = fls(fin) - fls(fspi);
441 if (fin > fspi << post)
444 /* now we have: (fin <= fspi << post) with post being minimal */
446 post = max(4U, post) - 4;
447 if (unlikely(post > 0xf)) {
448 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
453 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
455 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
456 __func__, fin, fspi, post, pre);
458 /* Resulting frequency for the SCLK line. */
459 *fres = (fin / (pre + 1)) >> post;
461 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
462 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
465 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
469 if (enable & MXC_INT_TE)
470 val |= MX51_ECSPI_INT_TEEN;
472 if (enable & MXC_INT_RR)
473 val |= MX51_ECSPI_INT_RREN;
475 if (enable & MXC_INT_RDR)
476 val |= MX51_ECSPI_INT_RDREN;
478 writel(val, spi_imx->base + MX51_ECSPI_INT);
481 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
485 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
486 reg |= MX51_ECSPI_CTRL_XCH;
487 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
490 static void mx51_disable_dma(struct spi_imx_data *spi_imx)
492 writel(0, spi_imx->base + MX51_ECSPI_DMA);
495 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
499 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
500 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
501 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
504 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
505 struct spi_message *msg)
507 struct spi_device *spi = msg->spi;
508 struct spi_transfer *xfer;
509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
510 u32 min_speed_hz = ~0U;
512 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
514 /* set Master or Slave mode */
515 if (spi_imx->slave_mode)
516 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
518 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
521 * Enable SPI_RDY handling (falling edge/level triggered).
523 if (spi->mode & SPI_READY)
524 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
526 /* set chip select to use */
527 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
530 * The ctrl register must be written first, with the EN bit set other
531 * registers must not be written to.
533 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
535 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
536 if (spi->mode & SPI_LOOP)
537 testreg |= MX51_ECSPI_TESTREG_LBC;
539 testreg &= ~MX51_ECSPI_TESTREG_LBC;
540 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
543 * eCSPI burst completion by Chip Select signal in Slave mode
544 * is not functional for imx53 Soc, config SPI burst completed when
545 * BURST_LENGTH + 1 bits are received
547 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
548 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
550 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
552 if (spi->mode & SPI_CPHA)
553 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
555 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
557 if (spi->mode & SPI_CPOL) {
558 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
559 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
561 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
562 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
565 if (spi->mode & SPI_CS_HIGH)
566 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
568 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
570 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
573 * Wait until the changes in the configuration register CONFIGREG
574 * propagate into the hardware. It takes exactly one tick of the
575 * SCLK clock, but we will wait two SCLK clock just to be sure. The
576 * effect of the delay it takes for the hardware to apply changes
577 * is noticable if the SCLK clock run very slow. In such a case, if
578 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
579 * be asserted before the SCLK polarity changes, which would disrupt
580 * the SPI communication as the device on the other end would consider
581 * the change of SCLK polarity as a clock tick already.
583 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
584 * callback, iterate over all the transfers in spi_message, find the
585 * one with lowest bus frequency, and use that bus frequency for the
586 * delay calculation. In case all transfers have speed_hz == 0, then
587 * min_speed_hz is ~0 and the resulting delay is zero.
589 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
592 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
595 delay = (2 * 1000000) / min_speed_hz;
596 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
598 else /* SCLK is _very_ slow */
599 usleep_range(delay, delay + 10);
604 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
605 struct spi_device *spi)
607 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
610 /* Clear BL field and set the right value */
611 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
612 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
613 ctrl |= (spi_imx->slave_burst * 8 - 1)
614 << MX51_ECSPI_CTRL_BL_OFFSET;
616 ctrl |= (spi_imx->bits_per_word - 1)
617 << MX51_ECSPI_CTRL_BL_OFFSET;
619 /* set clock speed */
620 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
621 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
622 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
623 spi_imx->spi_bus_clk = clk;
626 ctrl |= MX51_ECSPI_CTRL_SMC;
628 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
633 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
636 * Configure the DMA register: setup the watermark
637 * and enable DMA request.
639 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
640 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
641 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
642 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
643 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
646 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
648 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
651 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
653 /* drain receive buffer */
654 while (mx51_ecspi_rx_available(spi_imx))
655 readl(spi_imx->base + MXC_CSPIRXDATA);
658 #define MX31_INTREG_TEEN (1 << 0)
659 #define MX31_INTREG_RREN (1 << 3)
661 #define MX31_CSPICTRL_ENABLE (1 << 0)
662 #define MX31_CSPICTRL_MASTER (1 << 1)
663 #define MX31_CSPICTRL_XCH (1 << 2)
664 #define MX31_CSPICTRL_SMC (1 << 3)
665 #define MX31_CSPICTRL_POL (1 << 4)
666 #define MX31_CSPICTRL_PHA (1 << 5)
667 #define MX31_CSPICTRL_SSCTL (1 << 6)
668 #define MX31_CSPICTRL_SSPOL (1 << 7)
669 #define MX31_CSPICTRL_BC_SHIFT 8
670 #define MX35_CSPICTRL_BL_SHIFT 20
671 #define MX31_CSPICTRL_CS_SHIFT 24
672 #define MX35_CSPICTRL_CS_SHIFT 12
673 #define MX31_CSPICTRL_DR_SHIFT 16
675 #define MX31_CSPI_DMAREG 0x10
676 #define MX31_DMAREG_RH_DEN (1<<4)
677 #define MX31_DMAREG_TH_DEN (1<<1)
679 #define MX31_CSPISTATUS 0x14
680 #define MX31_STATUS_RR (1 << 3)
682 #define MX31_CSPI_TESTREG 0x1C
683 #define MX31_TEST_LBC (1 << 14)
685 /* These functions also work for the i.MX35, but be aware that
686 * the i.MX35 has a slightly different register layout for bits
687 * we do not use here.
689 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
691 unsigned int val = 0;
693 if (enable & MXC_INT_TE)
694 val |= MX31_INTREG_TEEN;
695 if (enable & MXC_INT_RR)
696 val |= MX31_INTREG_RREN;
698 writel(val, spi_imx->base + MXC_CSPIINT);
701 static void mx31_trigger(struct spi_imx_data *spi_imx)
705 reg = readl(spi_imx->base + MXC_CSPICTRL);
706 reg |= MX31_CSPICTRL_XCH;
707 writel(reg, spi_imx->base + MXC_CSPICTRL);
710 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
711 struct spi_message *msg)
716 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
717 struct spi_device *spi)
719 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
722 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
723 MX31_CSPICTRL_DR_SHIFT;
724 spi_imx->spi_bus_clk = clk;
726 if (is_imx35_cspi(spi_imx)) {
727 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
728 reg |= MX31_CSPICTRL_SSCTL;
730 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
733 if (spi->mode & SPI_CPHA)
734 reg |= MX31_CSPICTRL_PHA;
735 if (spi->mode & SPI_CPOL)
736 reg |= MX31_CSPICTRL_POL;
737 if (spi->mode & SPI_CS_HIGH)
738 reg |= MX31_CSPICTRL_SSPOL;
740 reg |= (spi->chip_select) <<
741 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
742 MX31_CSPICTRL_CS_SHIFT);
745 reg |= MX31_CSPICTRL_SMC;
747 writel(reg, spi_imx->base + MXC_CSPICTRL);
749 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
750 if (spi->mode & SPI_LOOP)
751 reg |= MX31_TEST_LBC;
753 reg &= ~MX31_TEST_LBC;
754 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
756 if (spi_imx->usedma) {
758 * configure DMA requests when RXFIFO is half full and
759 * when TXFIFO is half empty
761 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
762 spi_imx->base + MX31_CSPI_DMAREG);
768 static int mx31_rx_available(struct spi_imx_data *spi_imx)
770 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
773 static void mx31_reset(struct spi_imx_data *spi_imx)
775 /* drain receive buffer */
776 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
777 readl(spi_imx->base + MXC_CSPIRXDATA);
780 #define MX21_INTREG_RR (1 << 4)
781 #define MX21_INTREG_TEEN (1 << 9)
782 #define MX21_INTREG_RREN (1 << 13)
784 #define MX21_CSPICTRL_POL (1 << 5)
785 #define MX21_CSPICTRL_PHA (1 << 6)
786 #define MX21_CSPICTRL_SSPOL (1 << 8)
787 #define MX21_CSPICTRL_XCH (1 << 9)
788 #define MX21_CSPICTRL_ENABLE (1 << 10)
789 #define MX21_CSPICTRL_MASTER (1 << 11)
790 #define MX21_CSPICTRL_DR_SHIFT 14
791 #define MX21_CSPICTRL_CS_SHIFT 19
793 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
795 unsigned int val = 0;
797 if (enable & MXC_INT_TE)
798 val |= MX21_INTREG_TEEN;
799 if (enable & MXC_INT_RR)
800 val |= MX21_INTREG_RREN;
802 writel(val, spi_imx->base + MXC_CSPIINT);
805 static void mx21_trigger(struct spi_imx_data *spi_imx)
809 reg = readl(spi_imx->base + MXC_CSPICTRL);
810 reg |= MX21_CSPICTRL_XCH;
811 writel(reg, spi_imx->base + MXC_CSPICTRL);
814 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
815 struct spi_message *msg)
820 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
821 struct spi_device *spi)
823 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
824 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
827 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
828 << MX21_CSPICTRL_DR_SHIFT;
829 spi_imx->spi_bus_clk = clk;
831 reg |= spi_imx->bits_per_word - 1;
833 if (spi->mode & SPI_CPHA)
834 reg |= MX21_CSPICTRL_PHA;
835 if (spi->mode & SPI_CPOL)
836 reg |= MX21_CSPICTRL_POL;
837 if (spi->mode & SPI_CS_HIGH)
838 reg |= MX21_CSPICTRL_SSPOL;
840 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
842 writel(reg, spi_imx->base + MXC_CSPICTRL);
847 static int mx21_rx_available(struct spi_imx_data *spi_imx)
849 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
852 static void mx21_reset(struct spi_imx_data *spi_imx)
854 writel(1, spi_imx->base + MXC_RESET);
857 #define MX1_INTREG_RR (1 << 3)
858 #define MX1_INTREG_TEEN (1 << 8)
859 #define MX1_INTREG_RREN (1 << 11)
861 #define MX1_CSPICTRL_POL (1 << 4)
862 #define MX1_CSPICTRL_PHA (1 << 5)
863 #define MX1_CSPICTRL_XCH (1 << 8)
864 #define MX1_CSPICTRL_ENABLE (1 << 9)
865 #define MX1_CSPICTRL_MASTER (1 << 10)
866 #define MX1_CSPICTRL_DR_SHIFT 13
868 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
870 unsigned int val = 0;
872 if (enable & MXC_INT_TE)
873 val |= MX1_INTREG_TEEN;
874 if (enable & MXC_INT_RR)
875 val |= MX1_INTREG_RREN;
877 writel(val, spi_imx->base + MXC_CSPIINT);
880 static void mx1_trigger(struct spi_imx_data *spi_imx)
884 reg = readl(spi_imx->base + MXC_CSPICTRL);
885 reg |= MX1_CSPICTRL_XCH;
886 writel(reg, spi_imx->base + MXC_CSPICTRL);
889 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
890 struct spi_message *msg)
895 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
896 struct spi_device *spi)
898 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
901 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
902 MX1_CSPICTRL_DR_SHIFT;
903 spi_imx->spi_bus_clk = clk;
905 reg |= spi_imx->bits_per_word - 1;
907 if (spi->mode & SPI_CPHA)
908 reg |= MX1_CSPICTRL_PHA;
909 if (spi->mode & SPI_CPOL)
910 reg |= MX1_CSPICTRL_POL;
912 writel(reg, spi_imx->base + MXC_CSPICTRL);
917 static int mx1_rx_available(struct spi_imx_data *spi_imx)
919 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
922 static void mx1_reset(struct spi_imx_data *spi_imx)
924 writel(1, spi_imx->base + MXC_RESET);
927 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
928 .intctrl = mx1_intctrl,
929 .prepare_message = mx1_prepare_message,
930 .prepare_transfer = mx1_prepare_transfer,
931 .trigger = mx1_trigger,
932 .rx_available = mx1_rx_available,
935 .has_dmamode = false,
936 .dynamic_burst = false,
937 .has_slavemode = false,
938 .devtype = IMX1_CSPI,
941 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
942 .intctrl = mx21_intctrl,
943 .prepare_message = mx21_prepare_message,
944 .prepare_transfer = mx21_prepare_transfer,
945 .trigger = mx21_trigger,
946 .rx_available = mx21_rx_available,
949 .has_dmamode = false,
950 .dynamic_burst = false,
951 .has_slavemode = false,
952 .devtype = IMX21_CSPI,
955 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
956 /* i.mx27 cspi shares the functions with i.mx21 one */
957 .intctrl = mx21_intctrl,
958 .prepare_message = mx21_prepare_message,
959 .prepare_transfer = mx21_prepare_transfer,
960 .trigger = mx21_trigger,
961 .rx_available = mx21_rx_available,
964 .has_dmamode = false,
965 .dynamic_burst = false,
966 .has_slavemode = false,
967 .devtype = IMX27_CSPI,
970 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
971 .intctrl = mx31_intctrl,
972 .prepare_message = mx31_prepare_message,
973 .prepare_transfer = mx31_prepare_transfer,
974 .trigger = mx31_trigger,
975 .rx_available = mx31_rx_available,
978 .has_dmamode = false,
979 .dynamic_burst = false,
980 .has_slavemode = false,
981 .devtype = IMX31_CSPI,
984 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
985 /* i.mx35 and later cspi shares the functions with i.mx31 one */
986 .intctrl = mx31_intctrl,
987 .prepare_message = mx31_prepare_message,
988 .prepare_transfer = mx31_prepare_transfer,
989 .trigger = mx31_trigger,
990 .rx_available = mx31_rx_available,
994 .dynamic_burst = false,
995 .has_slavemode = false,
996 .devtype = IMX35_CSPI,
999 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1000 .intctrl = mx51_ecspi_intctrl,
1001 .prepare_message = mx51_ecspi_prepare_message,
1002 .prepare_transfer = mx51_ecspi_prepare_transfer,
1003 .trigger = mx51_ecspi_trigger,
1004 .rx_available = mx51_ecspi_rx_available,
1005 .reset = mx51_ecspi_reset,
1006 .setup_wml = mx51_setup_wml,
1007 .disable_dma = mx51_disable_dma,
1009 .has_dmamode = true,
1010 .dynamic_burst = true,
1011 .has_slavemode = true,
1012 .disable = mx51_ecspi_disable,
1013 .devtype = IMX51_ECSPI,
1016 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1017 .intctrl = mx51_ecspi_intctrl,
1018 .prepare_message = mx51_ecspi_prepare_message,
1019 .prepare_transfer = mx51_ecspi_prepare_transfer,
1020 .trigger = mx51_ecspi_trigger,
1021 .rx_available = mx51_ecspi_rx_available,
1022 .disable_dma = mx51_disable_dma,
1023 .reset = mx51_ecspi_reset,
1025 .has_dmamode = true,
1026 .has_slavemode = true,
1027 .disable = mx51_ecspi_disable,
1028 .devtype = IMX53_ECSPI,
1031 static const struct platform_device_id spi_imx_devtype[] = {
1033 .name = "imx1-cspi",
1034 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1036 .name = "imx21-cspi",
1037 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1039 .name = "imx27-cspi",
1040 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1042 .name = "imx31-cspi",
1043 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1045 .name = "imx35-cspi",
1046 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1048 .name = "imx51-ecspi",
1049 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1051 .name = "imx53-ecspi",
1052 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1058 static const struct of_device_id spi_imx_dt_ids[] = {
1059 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1060 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1061 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1062 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1063 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1064 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1065 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1068 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1070 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1074 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1075 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1076 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1077 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1080 static void spi_imx_push(struct spi_imx_data *spi_imx)
1082 unsigned int burst_len, fifo_words;
1084 if (spi_imx->dynamic_burst)
1087 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1089 * Reload the FIFO when the remaining bytes to be transferred in the
1090 * current burst is 0. This only applies when bits_per_word is a
1093 if (!spi_imx->remainder) {
1094 if (spi_imx->dynamic_burst) {
1096 /* We need to deal unaligned data first */
1097 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1100 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1102 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1104 spi_imx->remainder = burst_len;
1106 spi_imx->remainder = fifo_words;
1110 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1111 if (!spi_imx->count)
1113 if (spi_imx->dynamic_burst &&
1114 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1117 spi_imx->tx(spi_imx);
1121 if (!spi_imx->slave_mode)
1122 spi_imx->devtype_data->trigger(spi_imx);
1125 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1127 struct spi_imx_data *spi_imx = dev_id;
1129 while (spi_imx->txfifo &&
1130 spi_imx->devtype_data->rx_available(spi_imx)) {
1131 spi_imx->rx(spi_imx);
1135 if (spi_imx->count) {
1136 spi_imx_push(spi_imx);
1140 if (spi_imx->txfifo) {
1141 /* No data left to push, but still waiting for rx data,
1142 * enable receive data available interrupt.
1144 spi_imx->devtype_data->intctrl(
1145 spi_imx, MXC_INT_RR);
1149 spi_imx->devtype_data->intctrl(spi_imx, 0);
1150 complete(&spi_imx->xfer_done);
1155 static int spi_imx_dma_configure(struct spi_master *master)
1158 enum dma_slave_buswidth buswidth;
1159 struct dma_slave_config rx = {}, tx = {};
1160 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1162 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1164 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1167 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1170 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1176 tx.direction = DMA_MEM_TO_DEV;
1177 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1178 tx.dst_addr_width = buswidth;
1179 tx.dst_maxburst = spi_imx->wml;
1180 ret = dmaengine_slave_config(master->dma_tx, &tx);
1182 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1186 rx.direction = DMA_DEV_TO_MEM;
1187 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1188 rx.src_addr_width = buswidth;
1189 rx.src_maxburst = spi_imx->wml;
1190 ret = dmaengine_slave_config(master->dma_rx, &rx);
1192 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1199 static int spi_imx_setupxfer(struct spi_device *spi,
1200 struct spi_transfer *t)
1202 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1208 if (!spi->max_speed_hz) {
1209 dev_err(&spi->dev, "no speed_hz provided!\n");
1212 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1213 spi_imx->spi_bus_clk = spi->max_speed_hz;
1215 spi_imx->spi_bus_clk = t->speed_hz;
1217 spi_imx->bits_per_word = t->bits_per_word;
1220 * Initialize the functions for transfer. To transfer non byte-aligned
1221 * words, we have to use multiple word-size bursts, we can't use
1222 * dynamic_burst in that case.
1224 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1225 (spi_imx->bits_per_word == 8 ||
1226 spi_imx->bits_per_word == 16 ||
1227 spi_imx->bits_per_word == 32)) {
1229 spi_imx->rx = spi_imx_buf_rx_swap;
1230 spi_imx->tx = spi_imx_buf_tx_swap;
1231 spi_imx->dynamic_burst = 1;
1234 if (spi_imx->bits_per_word <= 8) {
1235 spi_imx->rx = spi_imx_buf_rx_u8;
1236 spi_imx->tx = spi_imx_buf_tx_u8;
1237 } else if (spi_imx->bits_per_word <= 16) {
1238 spi_imx->rx = spi_imx_buf_rx_u16;
1239 spi_imx->tx = spi_imx_buf_tx_u16;
1241 spi_imx->rx = spi_imx_buf_rx_u32;
1242 spi_imx->tx = spi_imx_buf_tx_u32;
1244 spi_imx->dynamic_burst = 0;
1247 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1248 spi_imx->usedma = true;
1250 spi_imx->usedma = false;
1252 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1253 spi_imx->rx = mx53_ecspi_rx_slave;
1254 spi_imx->tx = mx53_ecspi_tx_slave;
1255 spi_imx->slave_burst = t->len;
1258 spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1263 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1265 struct spi_master *master = spi_imx->bitbang.master;
1267 if (master->dma_rx) {
1268 dma_release_channel(master->dma_rx);
1269 master->dma_rx = NULL;
1272 if (master->dma_tx) {
1273 dma_release_channel(master->dma_tx);
1274 master->dma_tx = NULL;
1278 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1279 struct spi_master *master)
1283 /* use pio mode for i.mx6dl chip TKT238285 */
1284 if (of_machine_is_compatible("fsl,imx6dl"))
1287 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1289 /* Prepare for TX DMA: */
1290 master->dma_tx = dma_request_chan(dev, "tx");
1291 if (IS_ERR(master->dma_tx)) {
1292 ret = PTR_ERR(master->dma_tx);
1293 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1294 master->dma_tx = NULL;
1298 /* Prepare for RX : */
1299 master->dma_rx = dma_request_chan(dev, "rx");
1300 if (IS_ERR(master->dma_rx)) {
1301 ret = PTR_ERR(master->dma_rx);
1302 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1303 master->dma_rx = NULL;
1307 init_completion(&spi_imx->dma_rx_completion);
1308 init_completion(&spi_imx->dma_tx_completion);
1309 master->can_dma = spi_imx_can_dma;
1310 master->max_dma_len = MAX_SDMA_BD_BYTES;
1311 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1316 spi_imx_sdma_exit(spi_imx);
1320 static void spi_imx_dma_rx_callback(void *cookie)
1322 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1324 complete(&spi_imx->dma_rx_completion);
1327 static void spi_imx_dma_tx_callback(void *cookie)
1329 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1331 complete(&spi_imx->dma_tx_completion);
1334 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1336 unsigned long timeout = 0;
1338 /* Time with actual data transfer and CS change delay related to HW */
1339 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1341 /* Add extra second for scheduler related activities */
1344 /* Double calculated timeout */
1345 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1348 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1349 struct spi_transfer *transfer)
1351 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1352 unsigned long transfer_timeout;
1353 unsigned long timeout;
1354 struct spi_master *master = spi_imx->bitbang.master;
1355 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1356 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1357 unsigned int bytes_per_word, i;
1360 /* Get the right burst length from the last sg to ensure no tail data */
1361 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1362 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1363 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1366 /* Use 1 as wml in case no available burst length got */
1372 ret = spi_imx_dma_configure(master);
1374 goto dma_failure_no_start;
1376 if (!spi_imx->devtype_data->setup_wml) {
1377 dev_err(spi_imx->dev, "No setup_wml()?\n");
1379 goto dma_failure_no_start;
1381 spi_imx->devtype_data->setup_wml(spi_imx);
1384 * The TX DMA setup starts the transfer, so make sure RX is configured
1387 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1388 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1389 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1392 goto dma_failure_no_start;
1395 desc_rx->callback = spi_imx_dma_rx_callback;
1396 desc_rx->callback_param = (void *)spi_imx;
1397 dmaengine_submit(desc_rx);
1398 reinit_completion(&spi_imx->dma_rx_completion);
1399 dma_async_issue_pending(master->dma_rx);
1401 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1402 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1403 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1405 dmaengine_terminate_all(master->dma_tx);
1406 dmaengine_terminate_all(master->dma_rx);
1410 desc_tx->callback = spi_imx_dma_tx_callback;
1411 desc_tx->callback_param = (void *)spi_imx;
1412 dmaengine_submit(desc_tx);
1413 reinit_completion(&spi_imx->dma_tx_completion);
1414 dma_async_issue_pending(master->dma_tx);
1416 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1418 /* Wait SDMA to finish the data transfer.*/
1419 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1422 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1423 dmaengine_terminate_all(master->dma_tx);
1424 dmaengine_terminate_all(master->dma_rx);
1428 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1431 dev_err(&master->dev, "I/O Error in DMA RX\n");
1432 spi_imx->devtype_data->reset(spi_imx);
1433 dmaengine_terminate_all(master->dma_rx);
1437 return transfer->len;
1438 /* fallback to pio */
1439 dma_failure_no_start:
1440 transfer->error |= SPI_TRANS_FAIL_NO_START;
1444 static int spi_imx_pio_transfer(struct spi_device *spi,
1445 struct spi_transfer *transfer)
1447 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1448 unsigned long transfer_timeout;
1449 unsigned long timeout;
1451 spi_imx->tx_buf = transfer->tx_buf;
1452 spi_imx->rx_buf = transfer->rx_buf;
1453 spi_imx->count = transfer->len;
1454 spi_imx->txfifo = 0;
1455 spi_imx->remainder = 0;
1457 reinit_completion(&spi_imx->xfer_done);
1459 spi_imx_push(spi_imx);
1461 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1463 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1465 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1468 dev_err(&spi->dev, "I/O Error in PIO\n");
1469 spi_imx->devtype_data->reset(spi_imx);
1473 return transfer->len;
1476 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1477 struct spi_transfer *transfer)
1479 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1480 int ret = transfer->len;
1482 if (is_imx53_ecspi(spi_imx) &&
1483 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1484 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1485 MX53_MAX_TRANSFER_BYTES);
1489 spi_imx->tx_buf = transfer->tx_buf;
1490 spi_imx->rx_buf = transfer->rx_buf;
1491 spi_imx->count = transfer->len;
1492 spi_imx->txfifo = 0;
1493 spi_imx->remainder = 0;
1495 reinit_completion(&spi_imx->xfer_done);
1496 spi_imx->slave_aborted = false;
1498 spi_imx_push(spi_imx);
1500 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1502 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1503 spi_imx->slave_aborted) {
1504 dev_dbg(&spi->dev, "interrupted\n");
1508 /* ecspi has a HW issue when works in Slave mode,
1509 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1510 * ECSPI_TXDATA keeps shift out the last word data,
1511 * so we have to disable ECSPI when in slave mode after the
1512 * transfer completes
1514 if (spi_imx->devtype_data->disable)
1515 spi_imx->devtype_data->disable(spi_imx);
1520 static int spi_imx_transfer(struct spi_device *spi,
1521 struct spi_transfer *transfer)
1523 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1525 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1527 /* flush rxfifo before transfer */
1528 while (spi_imx->devtype_data->rx_available(spi_imx))
1529 readl(spi_imx->base + MXC_CSPIRXDATA);
1531 if (spi_imx->slave_mode)
1532 return spi_imx_pio_transfer_slave(spi, transfer);
1534 if (spi_imx->usedma)
1535 return spi_imx_dma_transfer(spi_imx, transfer);
1537 return spi_imx_pio_transfer(spi, transfer);
1540 static int spi_imx_setup(struct spi_device *spi)
1542 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1543 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1548 static void spi_imx_cleanup(struct spi_device *spi)
1553 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1555 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1558 ret = pm_runtime_get_sync(spi_imx->dev);
1560 pm_runtime_put_noidle(spi_imx->dev);
1561 dev_err(spi_imx->dev, "failed to enable clock\n");
1565 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1567 pm_runtime_mark_last_busy(spi_imx->dev);
1568 pm_runtime_put_autosuspend(spi_imx->dev);
1575 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1577 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1579 pm_runtime_mark_last_busy(spi_imx->dev);
1580 pm_runtime_put_autosuspend(spi_imx->dev);
1584 static int spi_imx_slave_abort(struct spi_master *master)
1586 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1588 spi_imx->slave_aborted = true;
1589 complete(&spi_imx->xfer_done);
1594 static int spi_imx_probe(struct platform_device *pdev)
1596 struct device_node *np = pdev->dev.of_node;
1597 const struct of_device_id *of_id =
1598 of_match_device(spi_imx_dt_ids, &pdev->dev);
1599 struct spi_master *master;
1600 struct spi_imx_data *spi_imx;
1601 struct resource *res;
1602 int ret, irq, spi_drctl;
1603 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1604 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1608 slave_mode = devtype_data->has_slavemode &&
1609 of_property_read_bool(np, "spi-slave");
1611 master = spi_alloc_slave(&pdev->dev,
1612 sizeof(struct spi_imx_data));
1614 master = spi_alloc_master(&pdev->dev,
1615 sizeof(struct spi_imx_data));
1619 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1620 if ((ret < 0) || (spi_drctl >= 0x3)) {
1621 /* '11' is reserved */
1625 platform_set_drvdata(pdev, master);
1627 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1628 master->bus_num = np ? -1 : pdev->id;
1629 master->use_gpio_descriptors = true;
1631 spi_imx = spi_master_get_devdata(master);
1632 spi_imx->bitbang.master = master;
1633 spi_imx->dev = &pdev->dev;
1634 spi_imx->slave_mode = slave_mode;
1636 spi_imx->devtype_data = devtype_data;
1639 * Get number of chip selects from device properties. This can be
1640 * coming from device tree or boardfiles, if it is not defined,
1641 * a default value of 3 chip selects will be used, as all the legacy
1642 * board files have <= 3 chip selects.
1644 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1645 master->num_chipselect = val;
1647 master->num_chipselect = 3;
1649 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1650 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1651 spi_imx->bitbang.master->setup = spi_imx_setup;
1652 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1653 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1654 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1655 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1656 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1658 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1659 is_imx53_ecspi(spi_imx))
1660 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1662 spi_imx->spi_drctl = spi_drctl;
1664 init_completion(&spi_imx->xfer_done);
1666 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1667 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1668 if (IS_ERR(spi_imx->base)) {
1669 ret = PTR_ERR(spi_imx->base);
1670 goto out_master_put;
1672 spi_imx->base_phys = res->start;
1674 irq = platform_get_irq(pdev, 0);
1677 goto out_master_put;
1680 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1681 dev_name(&pdev->dev), spi_imx);
1683 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1684 goto out_master_put;
1687 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1688 if (IS_ERR(spi_imx->clk_ipg)) {
1689 ret = PTR_ERR(spi_imx->clk_ipg);
1690 goto out_master_put;
1693 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1694 if (IS_ERR(spi_imx->clk_per)) {
1695 ret = PTR_ERR(spi_imx->clk_per);
1696 goto out_master_put;
1699 ret = clk_prepare_enable(spi_imx->clk_per);
1701 goto out_master_put;
1703 ret = clk_prepare_enable(spi_imx->clk_ipg);
1707 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1708 pm_runtime_use_autosuspend(spi_imx->dev);
1709 pm_runtime_get_noresume(spi_imx->dev);
1710 pm_runtime_set_active(spi_imx->dev);
1711 pm_runtime_enable(spi_imx->dev);
1713 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1715 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1716 * if validated on other chips.
1718 if (spi_imx->devtype_data->has_dmamode) {
1719 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1720 if (ret == -EPROBE_DEFER)
1721 goto out_runtime_pm_put;
1724 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1728 spi_imx->devtype_data->reset(spi_imx);
1730 spi_imx->devtype_data->intctrl(spi_imx, 0);
1732 master->dev.of_node = pdev->dev.of_node;
1733 ret = spi_bitbang_start(&spi_imx->bitbang);
1735 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1736 goto out_bitbang_start;
1739 pm_runtime_mark_last_busy(spi_imx->dev);
1740 pm_runtime_put_autosuspend(spi_imx->dev);
1745 if (spi_imx->devtype_data->has_dmamode)
1746 spi_imx_sdma_exit(spi_imx);
1748 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1749 pm_runtime_set_suspended(&pdev->dev);
1750 pm_runtime_disable(spi_imx->dev);
1752 clk_disable_unprepare(spi_imx->clk_ipg);
1754 clk_disable_unprepare(spi_imx->clk_per);
1756 spi_master_put(master);
1761 static int spi_imx_remove(struct platform_device *pdev)
1763 struct spi_master *master = platform_get_drvdata(pdev);
1764 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1767 spi_bitbang_stop(&spi_imx->bitbang);
1769 ret = pm_runtime_get_sync(spi_imx->dev);
1771 pm_runtime_put_noidle(spi_imx->dev);
1772 dev_err(spi_imx->dev, "failed to enable clock\n");
1776 writel(0, spi_imx->base + MXC_CSPICTRL);
1778 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1779 pm_runtime_put_sync(spi_imx->dev);
1780 pm_runtime_disable(spi_imx->dev);
1782 spi_imx_sdma_exit(spi_imx);
1783 spi_master_put(master);
1788 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1790 struct spi_master *master = dev_get_drvdata(dev);
1791 struct spi_imx_data *spi_imx;
1794 spi_imx = spi_master_get_devdata(master);
1796 ret = clk_prepare_enable(spi_imx->clk_per);
1800 ret = clk_prepare_enable(spi_imx->clk_ipg);
1802 clk_disable_unprepare(spi_imx->clk_per);
1809 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1811 struct spi_master *master = dev_get_drvdata(dev);
1812 struct spi_imx_data *spi_imx;
1814 spi_imx = spi_master_get_devdata(master);
1816 clk_disable_unprepare(spi_imx->clk_per);
1817 clk_disable_unprepare(spi_imx->clk_ipg);
1822 static int __maybe_unused spi_imx_suspend(struct device *dev)
1824 pinctrl_pm_select_sleep_state(dev);
1828 static int __maybe_unused spi_imx_resume(struct device *dev)
1830 pinctrl_pm_select_default_state(dev);
1834 static const struct dev_pm_ops imx_spi_pm = {
1835 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1836 spi_imx_runtime_resume, NULL)
1837 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1840 static struct platform_driver spi_imx_driver = {
1842 .name = DRIVER_NAME,
1843 .of_match_table = spi_imx_dt_ids,
1846 .id_table = spi_imx_devtype,
1847 .probe = spi_imx_probe,
1848 .remove = spi_imx_remove,
1850 module_platform_driver(spi_imx_driver);
1852 MODULE_DESCRIPTION("SPI Controller driver");
1853 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1854 MODULE_LICENSE("GPL");
1855 MODULE_ALIAS("platform:" DRIVER_NAME);