sound/soc/xilinx/xlnx_formatter_pcm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Xilinx ASoC audio formatter support
   4 //
   5 // Copyright (C) 2018 Xilinx, Inc.
   6 //
   7 // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
   8
   9 #include <linux/clk.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/sizes.h>
  15
  16 #include <sound/asoundef.h>
  17 #include <sound/soc.h>
  18 #include <sound/pcm_params.h>
  19
  20 #define DRV_NAME "xlnx_formatter_pcm"
  21
  22 #define XLNX_S2MM_OFFSET        0
  23 #define XLNX_MM2S_OFFSET        0x100
  24
  25 #define XLNX_AUD_CORE_CONFIG    0x4
  26 #define XLNX_AUD_CTRL           0x10
  27 #define XLNX_AUD_STS            0x14
  28
  29 #define AUD_CTRL_RESET_MASK     BIT(1)
  30 #define AUD_CFG_MM2S_MASK       BIT(15)
  31 #define AUD_CFG_S2MM_MASK       BIT(31)
  32
  33 #define XLNX_AUD_FS_MULTIPLIER  0x18
  34 #define XLNX_AUD_PERIOD_CONFIG  0x1C
  35 #define XLNX_AUD_BUFF_ADDR_LSB  0x20
  36 #define XLNX_AUD_BUFF_ADDR_MSB  0x24
  37 #define XLNX_AUD_XFER_COUNT     0x28
  38 #define XLNX_AUD_CH_STS_START   0x2C
  39 #define XLNX_BYTES_PER_CH       0x44
  40 #define XLNX_AUD_ALIGN_BYTES    64
  41
  42 #define AUD_STS_IOC_IRQ_MASK    BIT(31)
  43 #define AUD_STS_CH_STS_MASK     BIT(29)
  44 #define AUD_CTRL_IOC_IRQ_MASK   BIT(13)
  45 #define AUD_CTRL_TOUT_IRQ_MASK  BIT(14)
  46 #define AUD_CTRL_DMA_EN_MASK    BIT(0)
  47
  48 #define CFG_MM2S_CH_MASK        GENMASK(11, 8)
  49 #define CFG_MM2S_CH_SHIFT       8
  50 #define CFG_MM2S_XFER_MASK      GENMASK(14, 13)
  51 #define CFG_MM2S_XFER_SHIFT     13
  52 #define CFG_MM2S_PKG_MASK       BIT(12)
  53
  54 #define CFG_S2MM_CH_MASK        GENMASK(27, 24)
  55 #define CFG_S2MM_CH_SHIFT       24
  56 #define CFG_S2MM_XFER_MASK      GENMASK(30, 29)
  57 #define CFG_S2MM_XFER_SHIFT     29
  58 #define CFG_S2MM_PKG_MASK       BIT(28)
  59
  60 #define AUD_CTRL_DATA_WIDTH_SHIFT       16
  61 #define AUD_CTRL_ACTIVE_CH_SHIFT        19
  62 #define PERIOD_CFG_PERIODS_SHIFT        16
  63
  64 #define PERIODS_MIN             2
  65 #define PERIODS_MAX             6
  66 #define PERIOD_BYTES_MIN        192
  67 #define PERIOD_BYTES_MAX        (50 * 1024)
  68 #define XLNX_PARAM_UNKNOWN      0
  69
  70 enum bit_depth {
  71         BIT_DEPTH_8,
  72         BIT_DEPTH_16,
  73         BIT_DEPTH_20,
  74         BIT_DEPTH_24,
  75         BIT_DEPTH_32,
  76 };
  77
  78 struct xlnx_pcm_drv_data {
  79         void __iomem *mmio;
  80         bool s2mm_presence;
  81         bool mm2s_presence;
  82         int s2mm_irq;
  83         int mm2s_irq;
  84         struct snd_pcm_substream *play_stream;
  85         struct snd_pcm_substream *capture_stream;
  86         struct clk *axi_clk;
  87 };
  88
  89 /*
  90  * struct xlnx_pcm_stream_param - stream configuration
  91  * @mmio: base address offset
  92  * @interleaved: audio channels arrangement in buffer
  93  * @xfer_mode: data formatting mode during transfer
  94  * @ch_limit: Maximum channels supported
  95  * @buffer_size: stream ring buffer size
  96  */
  97 struct xlnx_pcm_stream_param {
  98         void __iomem *mmio;
  99         bool interleaved;
 100         u32 xfer_mode;
 101         u32 ch_limit;
 102         u64 buffer_size;
 103 };
 104
 105 static const struct snd_pcm_hardware xlnx_pcm_hardware = {
 106         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
 107                 SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_PAUSE |
 108                 SNDRV_PCM_INFO_RESUME,
 109         .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
 110                    SNDRV_PCM_FMTBIT_S24_LE,
 111         .channels_min = 2,
 112         .channels_max = 2,
 113         .rates = SNDRV_PCM_RATE_8000_192000,
 114         .rate_min = 8000,
 115         .rate_max = 192000,
 116         .buffer_bytes_max = PERIODS_MAX * PERIOD_BYTES_MAX,
 117         .period_bytes_min = PERIOD_BYTES_MIN,
 118         .period_bytes_max = PERIOD_BYTES_MAX,
 119         .periods_min = PERIODS_MIN,
 120         .periods_max = PERIODS_MAX,
 121 };
 122
 123 enum {
 124         AES_TO_AES,
 125         AES_TO_PCM,
 126         PCM_TO_PCM,
 127         PCM_TO_AES
 128 };
 129
 130 static void xlnx_parse_aes_params(u32 chsts_reg1_val, u32 chsts_reg2_val,
 131                                   struct device *dev)
 132 {
 133         u32 padded, srate, bit_depth, status[2];
 134
 135         if (chsts_reg1_val & IEC958_AES0_PROFESSIONAL) {
 136                 status[0] = chsts_reg1_val & 0xff;
 137                 status[1] = (chsts_reg1_val >> 16) & 0xff;
 138
 139                 switch (status[0] & IEC958_AES0_PRO_FS) {
 140                 case IEC958_AES0_PRO_FS_44100:
 141                         srate = 44100;
 142                         break;
 143                 case IEC958_AES0_PRO_FS_48000:
 144                         srate = 48000;
 145                         break;
 146                 case IEC958_AES0_PRO_FS_32000:
 147                         srate = 32000;
 148                         break;
 149                 case IEC958_AES0_PRO_FS_NOTID:
 150                 default:
 151                         srate = XLNX_PARAM_UNKNOWN;
 152                         break;
 153                 }
 154
 155                 switch (status[1] & IEC958_AES2_PRO_SBITS) {
 156                 case IEC958_AES2_PRO_WORDLEN_NOTID:
 157                 case IEC958_AES2_PRO_SBITS_20:
 158                         padded = 0;
 159                         break;
 160                 case IEC958_AES2_PRO_SBITS_24:
 161                         padded = 4;
 162                         break;
 163                 default:
 164                         bit_depth = XLNX_PARAM_UNKNOWN;
 165                         goto log_params;
 166                 }
 167
 168                 switch (status[1] & IEC958_AES2_PRO_WORDLEN) {
 169                 case IEC958_AES2_PRO_WORDLEN_20_16:
 170                         bit_depth = 16 + padded;
 171                         break;
 172                 case IEC958_AES2_PRO_WORDLEN_22_18:
 173                         bit_depth = 18 + padded;
 174                         break;
 175                 case IEC958_AES2_PRO_WORDLEN_23_19:
 176                         bit_depth = 19 + padded;
 177                         break;
 178                 case IEC958_AES2_PRO_WORDLEN_24_20:
 179                         bit_depth = 20 + padded;
 180                         break;
 181                 case IEC958_AES2_PRO_WORDLEN_NOTID:
 182                 default:
 183                         bit_depth = XLNX_PARAM_UNKNOWN;
 184                         break;
 185                 }
 186
 187         } else {
 188                 status[0] = (chsts_reg1_val >> 24) & 0xff;
 189                 status[1] = chsts_reg2_val & 0xff;
 190
 191                 switch (status[0] & IEC958_AES3_CON_FS) {
 192                 case IEC958_AES3_CON_FS_44100:
 193                         srate = 44100;
 194                         break;
 195                 case IEC958_AES3_CON_FS_48000:
 196                         srate = 48000;
 197                         break;
 198                 case IEC958_AES3_CON_FS_32000:
 199                         srate = 32000;
 200                         break;
 201                 default:
 202                         srate = XLNX_PARAM_UNKNOWN;
 203                         break;
 204                 }
 205
 206                 if (status[1] & IEC958_AES4_CON_MAX_WORDLEN_24)
 207                         padded = 4;
 208                 else
 209                         padded = 0;
 210
 211                 switch (status[1] & IEC958_AES4_CON_WORDLEN) {
 212                 case IEC958_AES4_CON_WORDLEN_20_16:
 213                         bit_depth = 16 + padded;
 214                         break;
 215                 case IEC958_AES4_CON_WORDLEN_22_18:
 216                         bit_depth = 18 + padded;
 217                         break;
 218                 case IEC958_AES4_CON_WORDLEN_23_19:
 219                         bit_depth = 19 + padded;
 220                         break;
 221                 case IEC958_AES4_CON_WORDLEN_24_20:
 222                         bit_depth = 20 + padded;
 223                         break;
 224                 case IEC958_AES4_CON_WORDLEN_21_17:
 225                         bit_depth = 17 + padded;
 226                         break;
 227                 case IEC958_AES4_CON_WORDLEN_NOTID:
 228                 default:
 229                         bit_depth = XLNX_PARAM_UNKNOWN;
 230                         break;
 231                 }
 232         }
 233
 234 log_params:
 235         if (srate != XLNX_PARAM_UNKNOWN)
 236                 dev_info(dev, "sample rate = %d\n", srate);
 237         else
 238                 dev_info(dev, "sample rate = unknown\n");
 239
 240         if (bit_depth != XLNX_PARAM_UNKNOWN)
 241                 dev_info(dev, "bit_depth = %d\n", bit_depth);
 242         else
 243                 dev_info(dev, "bit_depth = unknown\n");
 244 }
 245
 246 static int xlnx_formatter_pcm_reset(void __iomem *mmio_base)
 247 {
 248         u32 val, retries = 0;
 249
 250         val = readl(mmio_base + XLNX_AUD_CTRL);
 251         val |= AUD_CTRL_RESET_MASK;
 252         writel(val, mmio_base + XLNX_AUD_CTRL);
 253
 254         val = readl(mmio_base + XLNX_AUD_CTRL);
 255         /* Poll for maximum timeout of approximately 100ms (1 * 100)*/
 256         while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) {
 257                 mdelay(1);
 258                 retries++;
 259                 val = readl(mmio_base + XLNX_AUD_CTRL);
 260         }
 261         if (val & AUD_CTRL_RESET_MASK)
 262                 return -ENODEV;
 263
 264         return 0;
 265 }
 266
 267 static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream)
 268 {
 269         u32 val;
 270
 271         val = readl(mmio_base + XLNX_AUD_CTRL);
 272         val &= ~AUD_CTRL_IOC_IRQ_MASK;
 273         if (stream == SNDRV_PCM_STREAM_CAPTURE)
 274                 val &= ~AUD_CTRL_TOUT_IRQ_MASK;
 275
 276         writel(val, mmio_base + XLNX_AUD_CTRL);
 277 }
 278
 279 static irqreturn_t xlnx_mm2s_irq_handler(int irq, void *arg)
 280 {
 281         u32 val;
 282         void __iomem *reg;
 283         struct device *dev = arg;
 284         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev);
 285
 286         reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS;
 287         val = readl(reg);
 288         if (val & AUD_STS_IOC_IRQ_MASK) {
 289                 writel(val & AUD_STS_IOC_IRQ_MASK, reg);
 290                 if (adata->play_stream)
 291                         snd_pcm_period_elapsed(adata->play_stream);
 292                 return IRQ_HANDLED;
 293         }
 294
 295         return IRQ_NONE;
 296 }
 297
 298 static irqreturn_t xlnx_s2mm_irq_handler(int irq, void *arg)
 299 {
 300         u32 val;
 301         void __iomem *reg;
 302         struct device *dev = arg;
 303         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev);
 304
 305         reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS;
 306         val = readl(reg);
 307         if (val & AUD_STS_IOC_IRQ_MASK) {
 308                 writel(val & AUD_STS_IOC_IRQ_MASK, reg);
 309                 if (adata->capture_stream)
 310                         snd_pcm_period_elapsed(adata->capture_stream);
 311                 return IRQ_HANDLED;
 312         }
 313
 314         return IRQ_NONE;
 315 }
 316
 317 static int xlnx_formatter_pcm_open(struct snd_pcm_substream *substream)
 318 {
 319         int err;
 320         u32 val, data_format_mode;
 321         u32 ch_count_mask, ch_count_shift, data_xfer_mode, data_xfer_shift;
 322         struct xlnx_pcm_stream_param *stream_data;
 323         struct snd_pcm_runtime *runtime = substream->runtime;
 324         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 325         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 326                                                                     DRV_NAME);
 327         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev);
 328
 329         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
 330             !adata->mm2s_presence)
 331                 return -ENODEV;
 332         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
 333                  !adata->s2mm_presence)
 334                 return -ENODEV;
 335
 336         stream_data = kzalloc(sizeof(*stream_data), GFP_KERNEL);
 337         if (!stream_data)
 338                 return -ENOMEM;
 339
 340         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 341                 ch_count_mask = CFG_MM2S_CH_MASK;
 342                 ch_count_shift = CFG_MM2S_CH_SHIFT;
 343                 data_xfer_mode = CFG_MM2S_XFER_MASK;
 344                 data_xfer_shift = CFG_MM2S_XFER_SHIFT;
 345                 data_format_mode = CFG_MM2S_PKG_MASK;
 346                 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET;
 347                 adata->play_stream = substream;
 348
 349         } else {
 350                 ch_count_mask = CFG_S2MM_CH_MASK;
 351                 ch_count_shift = CFG_S2MM_CH_SHIFT;
 352                 data_xfer_mode = CFG_S2MM_XFER_MASK;
 353                 data_xfer_shift = CFG_S2MM_XFER_SHIFT;
 354                 data_format_mode = CFG_S2MM_PKG_MASK;
 355                 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET;
 356                 adata->capture_stream = substream;
 357         }
 358
 359         val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG);
 360
 361         if (!(val & data_format_mode))
 362                 stream_data->interleaved = true;
 363
 364         stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift;
 365         stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift;
 366         dev_info(component->dev,
 367                  "stream %d : format = %d mode = %d ch_limit = %d\n",
 368                  substream->stream, stream_data->interleaved,
 369                  stream_data->xfer_mode, stream_data->ch_limit);
 370
 371         snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware);
 372         runtime->private_data = stream_data;
 373
 374         /* Resize the period bytes as divisible by 64 */
 375         err = snd_pcm_hw_constraint_step(runtime, 0,
 376                                          SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 377                                          XLNX_AUD_ALIGN_BYTES);
 378         if (err) {
 379                 dev_err(component->dev,
 380                         "Unable to set constraint on period bytes\n");
 381                 return err;
 382         }
 383
 384         /* Resize the buffer bytes as divisible by 64 */
 385         err = snd_pcm_hw_constraint_step(runtime, 0,
 386                                          SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 387                                          XLNX_AUD_ALIGN_BYTES);
 388         if (err) {
 389                 dev_err(component->dev,
 390                         "Unable to set constraint on buffer bytes\n");
 391                 return err;
 392         }
 393
 394         /* Set periods as integer multiple */
 395         err = snd_pcm_hw_constraint_integer(runtime,
 396                                             SNDRV_PCM_HW_PARAM_PERIODS);
 397         if (err < 0) {
 398                 dev_err(component->dev,
 399                         "Unable to set constraint on periods to be integer\n");
 400                 return err;
 401         }
 402
 403         /* enable DMA IOC irq */
 404         val = readl(stream_data->mmio + XLNX_AUD_CTRL);
 405         val |= AUD_CTRL_IOC_IRQ_MASK;
 406         writel(val, stream_data->mmio + XLNX_AUD_CTRL);
 407
 408         return 0;
 409 }
 410
 411 static int xlnx_formatter_pcm_close(struct snd_pcm_substream *substream)
 412 {
 413         int ret;
 414         struct xlnx_pcm_stream_param *stream_data =
 415                         substream->runtime->private_data;
 416         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 417         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 418                                                                     DRV_NAME);
 419
 420         ret = xlnx_formatter_pcm_reset(stream_data->mmio);
 421         if (ret) {
 422                 dev_err(component->dev, "audio formatter reset failed\n");
 423                 goto err_reset;
 424         }
 425         xlnx_formatter_disable_irqs(stream_data->mmio, substream->stream);
 426
 427 err_reset:
 428         kfree(stream_data);
 429         return 0;
 430 }
 431
 432 static snd_pcm_uframes_t
 433 xlnx_formatter_pcm_pointer(struct snd_pcm_substream *substream)
 434 {
 435         u32 pos;
 436         struct snd_pcm_runtime *runtime = substream->runtime;
 437         struct xlnx_pcm_stream_param *stream_data = runtime->private_data;
 438
 439         pos = readl(stream_data->mmio + XLNX_AUD_XFER_COUNT);
 440
 441         if (pos >= stream_data->buffer_size)
 442                 pos = 0;
 443
 444         return bytes_to_frames(runtime, pos);
 445 }
 446
 447 static int xlnx_formatter_pcm_hw_params(struct snd_pcm_substream *substream,
 448                                         struct snd_pcm_hw_params *params)
 449 {
 450         u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample;
 451         u32 aes_reg1_val, aes_reg2_val;
 452         int status;
 453         u64 size;
 454         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 455         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 456                                                                     DRV_NAME);
 457         struct snd_pcm_runtime *runtime = substream->runtime;
 458         struct xlnx_pcm_stream_param *stream_data = runtime->private_data;
 459
 460         active_ch = params_channels(params);
 461         if (active_ch > stream_data->ch_limit)
 462                 return -EINVAL;
 463
 464         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
 465             stream_data->xfer_mode == AES_TO_PCM) {
 466                 val = readl(stream_data->mmio + XLNX_AUD_STS);
 467                 if (val & AUD_STS_CH_STS_MASK) {
 468                         aes_reg1_val = readl(stream_data->mmio +
 469                                              XLNX_AUD_CH_STS_START);
 470                         aes_reg2_val = readl(stream_data->mmio +
 471                                              XLNX_AUD_CH_STS_START + 0x4);
 472
 473                         xlnx_parse_aes_params(aes_reg1_val, aes_reg2_val,
 474                                               component->dev);
 475                 }
 476         }
 477
 478         size = params_buffer_bytes(params);
 479         status = snd_pcm_lib_malloc_pages(substream, size);
 480         if (status < 0)
 481                 return status;
 482
 483         stream_data->buffer_size = size;
 484
 485         low = lower_32_bits(runtime->dma_addr);
 486         high = upper_32_bits(runtime->dma_addr);
 487         writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB);
 488         writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB);
 489
 490         val = readl(stream_data->mmio + XLNX_AUD_CTRL);
 491         bits_per_sample = params_width(params);
 492         switch (bits_per_sample) {
 493         case 8:
 494                 val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT);
 495                 break;
 496         case 16:
 497                 val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT);
 498                 break;
 499         case 20:
 500                 val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT);
 501                 break;
 502         case 24:
 503                 val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT);
 504                 break;
 505         case 32:
 506                 val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT);
 507                 break;
 508         default:
 509                 return -EINVAL;
 510         }
 511
 512         val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT;
 513         writel(val, stream_data->mmio + XLNX_AUD_CTRL);
 514
 515         val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT)
 516                 | params_period_bytes(params);
 517         writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG);
 518         bytes_per_ch = DIV_ROUND_UP(params_period_bytes(params), active_ch);
 519         writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH);
 520
 521         return 0;
 522 }
 523
 524 static int xlnx_formatter_pcm_hw_free(struct snd_pcm_substream *substream)
 525 {
 526         return snd_pcm_lib_free_pages(substream);
 527 }
 528
 529 static int xlnx_formatter_pcm_trigger(struct snd_pcm_substream *substream,
 530                                       int cmd)
 531 {
 532         u32 val;
 533         struct xlnx_pcm_stream_param *stream_data =
 534                         substream->runtime->private_data;
 535
 536         switch (cmd) {
 537         case SNDRV_PCM_TRIGGER_START:
 538         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 539         case SNDRV_PCM_TRIGGER_RESUME:
 540                 val = readl(stream_data->mmio + XLNX_AUD_CTRL);
 541                 val |= AUD_CTRL_DMA_EN_MASK;
 542                 writel(val, stream_data->mmio + XLNX_AUD_CTRL);
 543                 break;
 544         case SNDRV_PCM_TRIGGER_STOP:
 545         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 546         case SNDRV_PCM_TRIGGER_SUSPEND:
 547                 val = readl(stream_data->mmio + XLNX_AUD_CTRL);
 548                 val &= ~AUD_CTRL_DMA_EN_MASK;
 549                 writel(val, stream_data->mmio + XLNX_AUD_CTRL);
 550                 break;
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int xlnx_formatter_pcm_new(struct snd_soc_pcm_runtime *rtd)
 557 {
 558         struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
 559                                                                     DRV_NAME);
 560         snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
 561                         SNDRV_DMA_TYPE_DEV, component->dev,
 562                         xlnx_pcm_hardware.buffer_bytes_max,
 563                         xlnx_pcm_hardware.buffer_bytes_max);
 564         return 0;
 565 }
 566
 567 static const struct snd_pcm_ops xlnx_formatter_pcm_ops = {
 568         .open = xlnx_formatter_pcm_open,
 569         .close = xlnx_formatter_pcm_close,
 570         .ioctl = snd_pcm_lib_ioctl,
 571         .hw_params = xlnx_formatter_pcm_hw_params,
 572         .hw_free = xlnx_formatter_pcm_hw_free,
 573         .trigger = xlnx_formatter_pcm_trigger,
 574         .pointer = xlnx_formatter_pcm_pointer,
 575 };
 576
 577 static const struct snd_soc_component_driver xlnx_asoc_component = {
 578         .name = DRV_NAME,
 579         .ops = &xlnx_formatter_pcm_ops,
 580         .pcm_new = xlnx_formatter_pcm_new,
 581 };
 582
 583 static int xlnx_formatter_pcm_probe(struct platform_device *pdev)
 584 {
 585         int ret;
 586         u32 val;
 587         struct xlnx_pcm_drv_data *aud_drv_data;
 588         struct resource *res;
 589         struct device *dev = &pdev->dev;
 590
 591         aud_drv_data = devm_kzalloc(dev, sizeof(*aud_drv_data), GFP_KERNEL);
 592         if (!aud_drv_data)
 593                 return -ENOMEM;
 594
 595         aud_drv_data->axi_clk = devm_clk_get(dev, "s_axi_lite_aclk");
 596         if (IS_ERR(aud_drv_data->axi_clk)) {
 597                 ret = PTR_ERR(aud_drv_data->axi_clk);
 598                 dev_err(dev, "failed to get s_axi_lite_aclk(%d)\n", ret);
 599                 return ret;
 600         }
 601         ret = clk_prepare_enable(aud_drv_data->axi_clk);
 602         if (ret) {
 603                 dev_err(dev,
 604                         "failed to enable s_axi_lite_aclk(%d)\n", ret);
 605                 return ret;
 606         }
 607
 608         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 609         if (!res) {
 610                 dev_err(dev, "audio formatter node:addr to resource failed\n");
 611                 ret = -ENXIO;
 612                 goto clk_err;
 613         }
 614         aud_drv_data->mmio = devm_ioremap_resource(dev, res);
 615         if (IS_ERR(aud_drv_data->mmio)) {
 616                 dev_err(dev, "audio formatter ioremap failed\n");
 617                 ret = PTR_ERR(aud_drv_data->mmio);
 618                 goto clk_err;
 619         }
 620
 621         val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG);
 622         if (val & AUD_CFG_MM2S_MASK) {
 623                 aud_drv_data->mm2s_presence = true;
 624                 ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio +
 625                                                XLNX_MM2S_OFFSET);
 626                 if (ret) {
 627                         dev_err(dev, "audio formatter reset failed\n");
 628                         goto clk_err;
 629                 }
 630                 xlnx_formatter_disable_irqs(aud_drv_data->mmio +
 631                                             XLNX_MM2S_OFFSET,
 632                                             SNDRV_PCM_STREAM_PLAYBACK);
 633
 634                 aud_drv_data->mm2s_irq = platform_get_irq_byname(pdev,
 635                                                                  "irq_mm2s");
 636                 if (aud_drv_data->mm2s_irq < 0) {
 637                         ret = aud_drv_data->mm2s_irq;
 638                         goto clk_err;
 639                 }
 640                 ret = devm_request_irq(dev, aud_drv_data->mm2s_irq,
 641                                        xlnx_mm2s_irq_handler, 0,
 642                                        "xlnx_formatter_pcm_mm2s_irq", dev);
 643                 if (ret) {
 644                         dev_err(dev, "xlnx audio mm2s irq request failed\n");
 645                         goto clk_err;
 646                 }
 647         }
 648         if (val & AUD_CFG_S2MM_MASK) {
 649                 aud_drv_data->s2mm_presence = true;
 650                 ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio +
 651                                                XLNX_S2MM_OFFSET);
 652                 if (ret) {
 653                         dev_err(dev, "audio formatter reset failed\n");
 654                         goto clk_err;
 655                 }
 656                 xlnx_formatter_disable_irqs(aud_drv_data->mmio +
 657                                             XLNX_S2MM_OFFSET,
 658                                             SNDRV_PCM_STREAM_CAPTURE);
 659
 660                 aud_drv_data->s2mm_irq = platform_get_irq_byname(pdev,
 661                                                                  "irq_s2mm");
 662                 if (aud_drv_data->s2mm_irq < 0) {
 663                         ret = aud_drv_data->s2mm_irq;
 664                         goto clk_err;
 665                 }
 666                 ret = devm_request_irq(dev, aud_drv_data->s2mm_irq,
 667                                        xlnx_s2mm_irq_handler, 0,
 668                                        "xlnx_formatter_pcm_s2mm_irq",
 669                                        dev);
 670                 if (ret) {
 671                         dev_err(dev, "xlnx audio s2mm irq request failed\n");
 672                         goto clk_err;
 673                 }
 674         }
 675
 676         dev_set_drvdata(dev, aud_drv_data);
 677
 678         ret = devm_snd_soc_register_component(dev, &xlnx_asoc_component,
 679                                               NULL, 0);
 680         if (ret) {
 681                 dev_err(dev, "pcm platform device register failed\n");
 682                 goto clk_err;
 683         }
 684
 685         return 0;
 686
 687 clk_err:
 688         clk_disable_unprepare(aud_drv_data->axi_clk);
 689         return ret;
 690 }
 691
 692 static int xlnx_formatter_pcm_remove(struct platform_device *pdev)
 693 {
 694         int ret = 0;
 695         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(&pdev->dev);
 696
 697         if (adata->s2mm_presence)
 698                 ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_S2MM_OFFSET);
 699
 700         /* Try MM2S reset, even if S2MM  reset fails */
 701         if (adata->mm2s_presence)
 702                 ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_MM2S_OFFSET);
 703
 704         if (ret)
 705                 dev_err(&pdev->dev, "audio formatter reset failed\n");
 706
 707         clk_disable_unprepare(adata->axi_clk);
 708         return ret;
 709 }
 710
 711 static const struct of_device_id xlnx_formatter_pcm_of_match[] = {
 712         { .compatible = "xlnx,audio-formatter-1.0"},
 713         {},
 714 };
 715 MODULE_DEVICE_TABLE(of, xlnx_formatter_pcm_of_match);
 716
 717 static struct platform_driver xlnx_formatter_pcm_driver = {
 718         .probe  = xlnx_formatter_pcm_probe,
 719         .remove = xlnx_formatter_pcm_remove,
 720         .driver = {
 721                 .name   = DRV_NAME,
 722                 .of_match_table = xlnx_formatter_pcm_of_match,
 723         },
 724 };
 725
 726 module_platform_driver(xlnx_formatter_pcm_driver);
 727 MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
 728 MODULE_LICENSE("GPL v2");