sound/soc/ti/omap-mcbsp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  *
   7  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <sound/core.h>
  18 #include <sound/pcm.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/initval.h>
  21 #include <sound/soc.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "omap-mcbsp-priv.h"
  25 #include "omap-mcbsp.h"
  26 #include "sdma-pcm.h"
  27
  28 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  29
  30 enum {
  31         OMAP_MCBSP_WORD_8 = 0,
  32         OMAP_MCBSP_WORD_12,
  33         OMAP_MCBSP_WORD_16,
  34         OMAP_MCBSP_WORD_20,
  35         OMAP_MCBSP_WORD_24,
  36         OMAP_MCBSP_WORD_32,
  37 };
  38
  39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  40 {
  41         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  42         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n", MCBSP_READ(mcbsp, DRR2));
  43         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n", MCBSP_READ(mcbsp, DRR1));
  44         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n", MCBSP_READ(mcbsp, DXR2));
  45         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n", MCBSP_READ(mcbsp, DXR1));
  46         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
  47         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
  48         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n", MCBSP_READ(mcbsp, RCR2));
  49         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n", MCBSP_READ(mcbsp, RCR1));
  50         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n", MCBSP_READ(mcbsp, XCR2));
  51         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n", MCBSP_READ(mcbsp, XCR1));
  52         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
  53         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
  54         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n", MCBSP_READ(mcbsp, PCR0));
  55         dev_dbg(mcbsp->dev, "***********************\n");
  56 }
  57
  58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
  59 {
  60         struct clk *fck_src;
  61         const char *src;
  62         int r;
  63
  64         if (fck_src_id == MCBSP_CLKS_PAD_SRC)
  65                 src = "pad_fck";
  66         else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
  67                 src = "prcm_fck";
  68         else
  69                 return -EINVAL;
  70
  71         fck_src = clk_get(mcbsp->dev, src);
  72         if (IS_ERR(fck_src)) {
  73                 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
  74                 return -EINVAL;
  75         }
  76
  77         pm_runtime_put_sync(mcbsp->dev);
  78
  79         r = clk_set_parent(mcbsp->fclk, fck_src);
  80         if (r) {
  81                 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
  82                         src);
  83                 clk_put(fck_src);
  84                 return r;
  85         }
  86
  87         pm_runtime_get_sync(mcbsp->dev);
  88
  89         clk_put(fck_src);
  90
  91         return 0;
  92 }
  93
  94 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
  95 {
  96         struct omap_mcbsp *mcbsp = data;
  97         u16 irqst;
  98
  99         irqst = MCBSP_READ(mcbsp, IRQST);
 100         dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
 101
 102         if (irqst & RSYNCERREN)
 103                 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
 104         if (irqst & RFSREN)
 105                 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
 106         if (irqst & REOFEN)
 107                 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
 108         if (irqst & RRDYEN)
 109                 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
 110         if (irqst & RUNDFLEN)
 111                 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
 112         if (irqst & ROVFLEN)
 113                 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
 114
 115         if (irqst & XSYNCERREN)
 116                 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
 117         if (irqst & XFSXEN)
 118                 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
 119         if (irqst & XEOFEN)
 120                 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
 121         if (irqst & XRDYEN)
 122                 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
 123         if (irqst & XUNDFLEN)
 124                 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
 125         if (irqst & XOVFLEN)
 126                 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
 127         if (irqst & XEMPTYEOFEN)
 128                 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
 129
 130         MCBSP_WRITE(mcbsp, IRQST, irqst);
 131
 132         return IRQ_HANDLED;
 133 }
 134
 135 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
 136 {
 137         struct omap_mcbsp *mcbsp = data;
 138         u16 irqst_spcr2;
 139
 140         irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
 141         dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 142
 143         if (irqst_spcr2 & XSYNC_ERR) {
 144                 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
 145                         irqst_spcr2);
 146                 /* Writing zero to XSYNC_ERR clears the IRQ */
 147                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
 148         }
 149
 150         return IRQ_HANDLED;
 151 }
 152
 153 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
 154 {
 155         struct omap_mcbsp *mcbsp = data;
 156         u16 irqst_spcr1;
 157
 158         irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
 159         dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 160
 161         if (irqst_spcr1 & RSYNC_ERR) {
 162                 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
 163                         irqst_spcr1);
 164                 /* Writing zero to RSYNC_ERR clears the IRQ */
 165                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
 166         }
 167
 168         return IRQ_HANDLED;
 169 }
 170
 171 /*
 172  * omap_mcbsp_config simply write a config to the
 173  * appropriate McBSP.
 174  * You either call this function or set the McBSP registers
 175  * by yourself before calling omap_mcbsp_start().
 176  */
 177 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 178                               const struct omap_mcbsp_reg_cfg *config)
 179 {
 180         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 181                 mcbsp->id, mcbsp->phys_base);
 182
 183         /* We write the given config */
 184         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 185         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 186         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 187         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 188         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 189         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 190         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 191         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 192         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 193         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 194         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 195         if (mcbsp->pdata->has_ccr) {
 196                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 197                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 198         }
 199         /* Enable wakeup behavior */
 200         if (mcbsp->pdata->has_wakeup)
 201                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 202
 203         /* Enable TX/RX sync error interrupts by default */
 204         if (mcbsp->irq)
 205                 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
 206                             RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
 207 }
 208
 209 /**
 210  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 211  * @mcbsp: omap_mcbsp struct for the McBSP instance
 212  * @stream: Stream direction (playback/capture)
 213  *
 214  * Returns the address of mcbsp data transmit register or data receive register
 215  * to be used by DMA for transferring/receiving data
 216  */
 217 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 218                                      unsigned int stream)
 219 {
 220         int data_reg;
 221
 222         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 223                 if (mcbsp->pdata->reg_size == 2)
 224                         data_reg = OMAP_MCBSP_REG_DXR1;
 225                 else
 226                         data_reg = OMAP_MCBSP_REG_DXR;
 227         } else {
 228                 if (mcbsp->pdata->reg_size == 2)
 229                         data_reg = OMAP_MCBSP_REG_DRR1;
 230                 else
 231                         data_reg = OMAP_MCBSP_REG_DRR;
 232         }
 233
 234         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 235 }
 236
 237 /*
 238  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 239  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 240  * for the THRSH2 register.
 241  */
 242 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 243 {
 244         if (threshold && threshold <= mcbsp->max_tx_thres)
 245                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 246 }
 247
 248 /*
 249  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 250  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 251  * for the THRSH1 register.
 252  */
 253 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 254 {
 255         if (threshold && threshold <= mcbsp->max_rx_thres)
 256                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 257 }
 258
 259 /*
 260  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 261  */
 262 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 263 {
 264         u16 buffstat;
 265
 266         /* Returns the number of free locations in the buffer */
 267         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 268
 269         /* Number of slots are different in McBSP ports */
 270         return mcbsp->pdata->buffer_size - buffstat;
 271 }
 272
 273 /*
 274  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 275  * to reach the threshold value (when the DMA will be triggered to read it)
 276  */
 277 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 278 {
 279         u16 buffstat, threshold;
 280
 281         /* Returns the number of used locations in the buffer */
 282         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 283         /* RX threshold */
 284         threshold = MCBSP_READ(mcbsp, THRSH1);
 285
 286         /* Return the number of location till we reach the threshold limit */
 287         if (threshold <= buffstat)
 288                 return 0;
 289         else
 290                 return threshold - buffstat;
 291 }
 292
 293 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 294 {
 295         void *reg_cache;
 296         int err;
 297
 298         reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 299         if (!reg_cache)
 300                 return -ENOMEM;
 301
 302         spin_lock(&mcbsp->lock);
 303         if (!mcbsp->free) {
 304                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
 305                 err = -EBUSY;
 306                 goto err_kfree;
 307         }
 308
 309         mcbsp->free = false;
 310         mcbsp->reg_cache = reg_cache;
 311         spin_unlock(&mcbsp->lock);
 312
 313         if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 314                 mcbsp->pdata->ops->request(mcbsp->id - 1);
 315
 316         /*
 317          * Make sure that transmitter, receiver and sample-rate generator are
 318          * not running before activating IRQs.
 319          */
 320         MCBSP_WRITE(mcbsp, SPCR1, 0);
 321         MCBSP_WRITE(mcbsp, SPCR2, 0);
 322
 323         if (mcbsp->irq) {
 324                 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
 325                                   "McBSP", (void *)mcbsp);
 326                 if (err != 0) {
 327                         dev_err(mcbsp->dev, "Unable to request IRQ\n");
 328                         goto err_clk_disable;
 329                 }
 330         } else {
 331                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
 332                                   "McBSP TX", (void *)mcbsp);
 333                 if (err != 0) {
 334                         dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
 335                         goto err_clk_disable;
 336                 }
 337
 338                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
 339                                   "McBSP RX", (void *)mcbsp);
 340                 if (err != 0) {
 341                         dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
 342                         goto err_free_irq;
 343                 }
 344         }
 345
 346         return 0;
 347 err_free_irq:
 348         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 349 err_clk_disable:
 350         if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 351                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 352
 353         /* Disable wakeup behavior */
 354         if (mcbsp->pdata->has_wakeup)
 355                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 356
 357         spin_lock(&mcbsp->lock);
 358         mcbsp->free = true;
 359         mcbsp->reg_cache = NULL;
 360 err_kfree:
 361         spin_unlock(&mcbsp->lock);
 362         kfree(reg_cache);
 363
 364         return err;
 365 }
 366
 367 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 368 {
 369         void *reg_cache;
 370
 371         if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 372                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 373
 374         /* Disable wakeup behavior */
 375         if (mcbsp->pdata->has_wakeup)
 376                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 377
 378         /* Disable interrupt requests */
 379         if (mcbsp->irq)
 380                 MCBSP_WRITE(mcbsp, IRQEN, 0);
 381
 382         if (mcbsp->irq) {
 383                 free_irq(mcbsp->irq, (void *)mcbsp);
 384         } else {
 385                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 386                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 387         }
 388
 389         reg_cache = mcbsp->reg_cache;
 390
 391         /*
 392          * Select CLKS source from internal source unconditionally before
 393          * marking the McBSP port as free.
 394          * If the external clock source via MCBSP_CLKS pin has been selected the
 395          * system will refuse to enter idle if the CLKS pin source is not reset
 396          * back to internal source.
 397          */
 398         if (!mcbsp_omap1())
 399                 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 400
 401         spin_lock(&mcbsp->lock);
 402         if (mcbsp->free)
 403                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 404         else
 405                 mcbsp->free = true;
 406         mcbsp->reg_cache = NULL;
 407         spin_unlock(&mcbsp->lock);
 408
 409         kfree(reg_cache);
 410 }
 411
 412 /*
 413  * Here we start the McBSP, by enabling transmitter, receiver or both.
 414  * If no transmitter or receiver is active prior calling, then sample-rate
 415  * generator and frame sync are started.
 416  */
 417 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
 418 {
 419         int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
 420         int rx = !tx;
 421         int enable_srg = 0;
 422         u16 w;
 423
 424         if (mcbsp->st_data)
 425                 omap_mcbsp_st_start(mcbsp);
 426
 427         /* Only enable SRG, if McBSP is master */
 428         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 429         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 430                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 431                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 432
 433         if (enable_srg) {
 434                 /* Start the sample generator */
 435                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 436                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 437         }
 438
 439         /* Enable transmitter and receiver */
 440         tx &= 1;
 441         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 442         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 443
 444         rx &= 1;
 445         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 446         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 447
 448         /*
 449          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 450          * REVISIT: 100us may give enough time for two CLKSRG, however
 451          * due to some unknown PM related, clock gating etc. reason it
 452          * is now at 500us.
 453          */
 454         udelay(500);
 455
 456         if (enable_srg) {
 457                 /* Start frame sync */
 458                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 459                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 460         }
 461
 462         if (mcbsp->pdata->has_ccr) {
 463                 /* Release the transmitter and receiver */
 464                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 465                 w &= ~(tx ? XDISABLE : 0);
 466                 MCBSP_WRITE(mcbsp, XCCR, w);
 467                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 468                 w &= ~(rx ? RDISABLE : 0);
 469                 MCBSP_WRITE(mcbsp, RCCR, w);
 470         }
 471
 472         /* Dump McBSP Regs */
 473         omap_mcbsp_dump_reg(mcbsp);
 474 }
 475
 476 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
 477 {
 478         int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
 479         int rx = !tx;
 480         int idle;
 481         u16 w;
 482
 483         /* Reset transmitter */
 484         tx &= 1;
 485         if (mcbsp->pdata->has_ccr) {
 486                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 487                 w |= (tx ? XDISABLE : 0);
 488                 MCBSP_WRITE(mcbsp, XCCR, w);
 489         }
 490         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 491         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 492
 493         /* Reset receiver */
 494         rx &= 1;
 495         if (mcbsp->pdata->has_ccr) {
 496                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 497                 w |= (rx ? RDISABLE : 0);
 498                 MCBSP_WRITE(mcbsp, RCCR, w);
 499         }
 500         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 501         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 502
 503         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 504                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 505
 506         if (idle) {
 507                 /* Reset the sample rate generator */
 508                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 509                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 510         }
 511
 512         if (mcbsp->st_data)
 513                 omap_mcbsp_st_stop(mcbsp);
 514 }
 515
 516 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 517 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 518 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 519 static ssize_t prop##_show(struct device *dev,                          \
 520                         struct device_attribute *attr, char *buf)       \
 521 {                                                                       \
 522         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 523                                                                         \
 524         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 525 }                                                                       \
 526                                                                         \
 527 static ssize_t prop##_store(struct device *dev,                         \
 528                                 struct device_attribute *attr,          \
 529                                 const char *buf, size_t size)           \
 530 {                                                                       \
 531         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 532         unsigned long val;                                              \
 533         int status;                                                     \
 534                                                                         \
 535         status = kstrtoul(buf, 0, &val);                                \
 536         if (status)                                                     \
 537                 return status;                                          \
 538                                                                         \
 539         if (!valid_threshold(mcbsp, val))                               \
 540                 return -EDOM;                                           \
 541                                                                         \
 542         mcbsp->prop = val;                                              \
 543         return size;                                                    \
 544 }                                                                       \
 545                                                                         \
 546 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store)
 547
 548 THRESHOLD_PROP_BUILDER(max_tx_thres);
 549 THRESHOLD_PROP_BUILDER(max_rx_thres);
 550
 551 static const char * const dma_op_modes[] = {
 552         "element", "threshold",
 553 };
 554
 555 static ssize_t dma_op_mode_show(struct device *dev,
 556                                 struct device_attribute *attr, char *buf)
 557 {
 558         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 559         int dma_op_mode, i = 0;
 560         ssize_t len = 0;
 561         const char * const *s;
 562
 563         dma_op_mode = mcbsp->dma_op_mode;
 564
 565         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 566                 if (dma_op_mode == i)
 567                         len += sprintf(buf + len, "[%s] ", *s);
 568                 else
 569                         len += sprintf(buf + len, "%s ", *s);
 570         }
 571         len += sprintf(buf + len, "\n");
 572
 573         return len;
 574 }
 575
 576 static ssize_t dma_op_mode_store(struct device *dev,
 577                                  struct device_attribute *attr, const char *buf,
 578                                  size_t size)
 579 {
 580         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 581         int i;
 582
 583         i = sysfs_match_string(dma_op_modes, buf);
 584         if (i < 0)
 585                 return i;
 586
 587         spin_lock_irq(&mcbsp->lock);
 588         if (!mcbsp->free) {
 589                 size = -EBUSY;
 590                 goto unlock;
 591         }
 592         mcbsp->dma_op_mode = i;
 593
 594 unlock:
 595         spin_unlock_irq(&mcbsp->lock);
 596
 597         return size;
 598 }
 599
 600 static DEVICE_ATTR_RW(dma_op_mode);
 601
 602 static const struct attribute *additional_attrs[] = {
 603         &dev_attr_max_tx_thres.attr,
 604         &dev_attr_max_rx_thres.attr,
 605         &dev_attr_dma_op_mode.attr,
 606         NULL,
 607 };
 608
 609 static const struct attribute_group additional_attr_group = {
 610         .attrs = (struct attribute **)additional_attrs,
 611 };
 612
 613 /*
 614  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 615  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 616  */
 617 static int omap_mcbsp_init(struct platform_device *pdev)
 618 {
 619         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 620         struct resource *res;
 621         int ret = 0;
 622
 623         spin_lock_init(&mcbsp->lock);
 624         mcbsp->free = true;
 625
 626         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 627         if (!res)
 628                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 629
 630         mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
 631         if (IS_ERR(mcbsp->io_base))
 632                 return PTR_ERR(mcbsp->io_base);
 633
 634         mcbsp->phys_base = res->start;
 635         mcbsp->reg_cache_size = resource_size(res);
 636
 637         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 638         if (!res)
 639                 mcbsp->phys_dma_base = mcbsp->phys_base;
 640         else
 641                 mcbsp->phys_dma_base = res->start;
 642
 643         /*
 644          * OMAP1, 2 uses two interrupt lines: TX, RX
 645          * OMAP2430, OMAP3 SoC have combined IRQ line as well.
 646          * OMAP4 and newer SoC only have the combined IRQ line.
 647          * Use the combined IRQ if available since it gives better debugging
 648          * possibilities.
 649          */
 650         mcbsp->irq = platform_get_irq_byname(pdev, "common");
 651         if (mcbsp->irq == -ENXIO) {
 652                 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
 653
 654                 if (mcbsp->tx_irq == -ENXIO) {
 655                         mcbsp->irq = platform_get_irq(pdev, 0);
 656                         mcbsp->tx_irq = 0;
 657                 } else {
 658                         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
 659                         mcbsp->irq = 0;
 660                 }
 661         }
 662
 663         if (!pdev->dev.of_node) {
 664                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
 665                 if (!res) {
 666                         dev_err(&pdev->dev, "invalid tx DMA channel\n");
 667                         return -ENODEV;
 668                 }
 669                 mcbsp->dma_req[0] = res->start;
 670                 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
 671
 672                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
 673                 if (!res) {
 674                         dev_err(&pdev->dev, "invalid rx DMA channel\n");
 675                         return -ENODEV;
 676                 }
 677                 mcbsp->dma_req[1] = res->start;
 678                 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
 679         } else {
 680                 mcbsp->dma_data[0].filter_data = "tx";
 681                 mcbsp->dma_data[1].filter_data = "rx";
 682         }
 683
 684         mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
 685                                                 SNDRV_PCM_STREAM_PLAYBACK);
 686         mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
 687                                                 SNDRV_PCM_STREAM_CAPTURE);
 688
 689         mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
 690         if (IS_ERR(mcbsp->fclk)) {
 691                 ret = PTR_ERR(mcbsp->fclk);
 692                 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
 693                 return ret;
 694         }
 695
 696         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
 697         if (mcbsp->pdata->buffer_size) {
 698                 /*
 699                  * Initially configure the maximum thresholds to a safe value.
 700                  * The McBSP FIFO usage with these values should not go under
 701                  * 16 locations.
 702                  * If the whole FIFO without safety buffer is used, than there
 703                  * is a possibility that the DMA will be not able to push the
 704                  * new data on time, causing channel shifts in runtime.
 705                  */
 706                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
 707                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
 708
 709                 ret = sysfs_create_group(&mcbsp->dev->kobj,
 710                                          &additional_attr_group);
 711                 if (ret) {
 712                         dev_err(mcbsp->dev,
 713                                 "Unable to create additional controls\n");
 714                         return ret;
 715                 }
 716         }
 717
 718         ret = omap_mcbsp_st_init(pdev);
 719         if (ret)
 720                 goto err_st;
 721
 722         return 0;
 723
 724 err_st:
 725         if (mcbsp->pdata->buffer_size)
 726                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
 727         return ret;
 728 }
 729
 730 /*
 731  * Stream DMA parameters. DMA request line and port address are set runtime
 732  * since they are different between OMAP1 and later OMAPs
 733  */
 734 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
 735                 unsigned int packet_size)
 736 {
 737         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 738         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 739         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 740         int words;
 741
 742         /* No need to proceed further if McBSP does not have FIFO */
 743         if (mcbsp->pdata->buffer_size == 0)
 744                 return;
 745
 746         /*
 747          * Configure McBSP threshold based on either:
 748          * packet_size, when the sDMA is in packet mode, or based on the
 749          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
 750          * for mono streams.
 751          */
 752         if (packet_size)
 753                 words = packet_size;
 754         else
 755                 words = 1;
 756
 757         /* Configure McBSP internal buffer usage */
 758         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 759                 omap_mcbsp_set_tx_threshold(mcbsp, words);
 760         else
 761                 omap_mcbsp_set_rx_threshold(mcbsp, words);
 762 }
 763
 764 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 765                                     struct snd_pcm_hw_rule *rule)
 766 {
 767         struct snd_interval *buffer_size = hw_param_interval(params,
 768                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 769         struct snd_interval *channels = hw_param_interval(params,
 770                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 771         struct omap_mcbsp *mcbsp = rule->private;
 772         struct snd_interval frames;
 773         int size;
 774
 775         snd_interval_any(&frames);
 776         size = mcbsp->pdata->buffer_size;
 777
 778         frames.min = size / channels->min;
 779         frames.integer = 1;
 780         return snd_interval_refine(buffer_size, &frames);
 781 }
 782
 783 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 784                                   struct snd_soc_dai *cpu_dai)
 785 {
 786         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 787         int err = 0;
 788
 789         if (!cpu_dai->active)
 790                 err = omap_mcbsp_request(mcbsp);
 791
 792         /*
 793          * OMAP3 McBSP FIFO is word structured.
 794          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 795          * McBSP1,3,4,5 has 128 word long buffer
 796          * This means that the size of the FIFO depends on the sample format.
 797          * For example on McBSP3:
 798          * 16bit samples: size is 128 * 2 = 256 bytes
 799          * 32bit samples: size is 128 * 4 = 512 bytes
 800          * It is simpler to place constraint for buffer and period based on
 801          * channels.
 802          * McBSP3 as example again (16 or 32 bit samples):
 803          * 1 channel (mono): size is 128 frames (128 words)
 804          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 805          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 806          */
 807         if (mcbsp->pdata->buffer_size) {
 808                 /*
 809                 * Rule for the buffer size. We should not allow
 810                 * smaller buffer than the FIFO size to avoid underruns.
 811                 * This applies only for the playback stream.
 812                 */
 813                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 814                         snd_pcm_hw_rule_add(substream->runtime, 0,
 815                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 816                                             omap_mcbsp_hwrule_min_buffersize,
 817                                             mcbsp,
 818                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 819
 820                 /* Make sure, that the period size is always even */
 821                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 822                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 823         }
 824
 825         return err;
 826 }
 827
 828 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 829                                     struct snd_soc_dai *cpu_dai)
 830 {
 831         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 832         int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 833         int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 834         int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 835
 836         if (mcbsp->latency[stream2])
 837                 pm_qos_update_request(&mcbsp->pm_qos_req,
 838                                       mcbsp->latency[stream2]);
 839         else if (mcbsp->latency[stream1])
 840                 pm_qos_remove_request(&mcbsp->pm_qos_req);
 841
 842         mcbsp->latency[stream1] = 0;
 843
 844         if (!cpu_dai->active) {
 845                 omap_mcbsp_free(mcbsp);
 846                 mcbsp->configured = 0;
 847         }
 848 }
 849
 850 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
 851                                   struct snd_soc_dai *cpu_dai)
 852 {
 853         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 854         struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
 855         int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 856         int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 857         int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 858         int latency = mcbsp->latency[stream2];
 859
 860         /* Prevent omap hardware from hitting off between FIFO fills */
 861         if (!latency || mcbsp->latency[stream1] < latency)
 862                 latency = mcbsp->latency[stream1];
 863
 864         if (pm_qos_request_active(pm_qos_req))
 865                 pm_qos_update_request(pm_qos_req, latency);
 866         else if (latency)
 867                 pm_qos_add_request(pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency);
 868
 869         return 0;
 870 }
 871
 872 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 873                                   struct snd_soc_dai *cpu_dai)
 874 {
 875         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 876
 877         switch (cmd) {
 878         case SNDRV_PCM_TRIGGER_START:
 879         case SNDRV_PCM_TRIGGER_RESUME:
 880         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 881                 mcbsp->active++;
 882                 omap_mcbsp_start(mcbsp, substream->stream);
 883                 break;
 884
 885         case SNDRV_PCM_TRIGGER_STOP:
 886         case SNDRV_PCM_TRIGGER_SUSPEND:
 887         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 888                 omap_mcbsp_stop(mcbsp, substream->stream);
 889                 mcbsp->active--;
 890                 break;
 891         default:
 892                 return -EINVAL;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 899                         struct snd_pcm_substream *substream,
 900                         struct snd_soc_dai *dai)
 901 {
 902         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 903         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 904         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 905         u16 fifo_use;
 906         snd_pcm_sframes_t delay;
 907
 908         /* No need to proceed further if McBSP does not have FIFO */
 909         if (mcbsp->pdata->buffer_size == 0)
 910                 return 0;
 911
 912         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 913                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 914         else
 915                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 916
 917         /*
 918          * Divide the used locations with the channel count to get the
 919          * FIFO usage in samples (don't care about partial samples in the
 920          * buffer).
 921          */
 922         delay = fifo_use / substream->runtime->channels;
 923
 924         return delay;
 925 }
 926
 927 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 928                                     struct snd_pcm_hw_params *params,
 929                                     struct snd_soc_dai *cpu_dai)
 930 {
 931         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 932         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 933         struct snd_dmaengine_dai_dma_data *dma_data;
 934         int wlen, channels, wpf;
 935         int pkt_size = 0;
 936         unsigned int format, div, framesize, master;
 937         unsigned int buffer_size = mcbsp->pdata->buffer_size;
 938
 939         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 940         channels = params_channels(params);
 941
 942         switch (params_format(params)) {
 943         case SNDRV_PCM_FORMAT_S16_LE:
 944                 wlen = 16;
 945                 break;
 946         case SNDRV_PCM_FORMAT_S32_LE:
 947                 wlen = 32;
 948                 break;
 949         default:
 950                 return -EINVAL;
 951         }
 952         if (buffer_size) {
 953                 int latency;
 954
 955                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 956                         int period_words, max_thrsh;
 957                         int divider = 0;
 958
 959                         period_words = params_period_bytes(params) / (wlen / 8);
 960                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 961                                 max_thrsh = mcbsp->max_tx_thres;
 962                         else
 963                                 max_thrsh = mcbsp->max_rx_thres;
 964                         /*
 965                          * Use sDMA packet mode if McBSP is in threshold mode:
 966                          * If period words less than the FIFO size the packet
 967                          * size is set to the number of period words, otherwise
 968                          * Look for the biggest threshold value which divides
 969                          * the period size evenly.
 970                          */
 971                         divider = period_words / max_thrsh;
 972                         if (period_words % max_thrsh)
 973                                 divider++;
 974                         while (period_words % divider &&
 975                                 divider < period_words)
 976                                 divider++;
 977                         if (divider == period_words)
 978                                 return -EINVAL;
 979
 980                         pkt_size = period_words / divider;
 981                 } else if (channels > 1) {
 982                         /* Use packet mode for non mono streams */
 983                         pkt_size = channels;
 984                 }
 985
 986                 latency = (buffer_size - pkt_size) / channels;
 987                 latency = latency * USEC_PER_SEC /
 988                           (params->rate_num / params->rate_den);
 989                 mcbsp->latency[substream->stream] = latency;
 990
 991                 omap_mcbsp_set_threshold(substream, pkt_size);
 992         }
 993
 994         dma_data->maxburst = pkt_size;
 995
 996         if (mcbsp->configured) {
 997                 /* McBSP already configured by another stream */
 998                 return 0;
 999         }
1000
1001         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
1002         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
1003         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
1004         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
1005         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1006         wpf = channels;
1007         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
1008                               format == SND_SOC_DAIFMT_LEFT_J)) {
1009                 /* Use dual-phase frames */
1010                 regs->rcr2      |= RPHASE;
1011                 regs->xcr2      |= XPHASE;
1012                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
1013                 wpf--;
1014                 regs->rcr2      |= RFRLEN2(wpf - 1);
1015                 regs->xcr2      |= XFRLEN2(wpf - 1);
1016         }
1017
1018         regs->rcr1      |= RFRLEN1(wpf - 1);
1019         regs->xcr1      |= XFRLEN1(wpf - 1);
1020
1021         switch (params_format(params)) {
1022         case SNDRV_PCM_FORMAT_S16_LE:
1023                 /* Set word lengths */
1024                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
1025                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
1026                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
1027                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
1028                 break;
1029         case SNDRV_PCM_FORMAT_S32_LE:
1030                 /* Set word lengths */
1031                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
1032                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
1033                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
1034                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
1035                 break;
1036         default:
1037                 /* Unsupported PCM format */
1038                 return -EINVAL;
1039         }
1040
1041         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1042          * by _counting_ BCLKs. Calculate frame size in BCLKs */
1043         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1044         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
1045                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1046                 framesize = (mcbsp->in_freq / div) / params_rate(params);
1047
1048                 if (framesize < wlen * channels) {
1049                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1050                                         "channels\n", __func__);
1051                         return -EINVAL;
1052                 }
1053         } else
1054                 framesize = wlen * channels;
1055
1056         /* Set FS period and length in terms of bit clock periods */
1057         regs->srgr2     &= ~FPER(0xfff);
1058         regs->srgr1     &= ~FWID(0xff);
1059         switch (format) {
1060         case SND_SOC_DAIFMT_I2S:
1061         case SND_SOC_DAIFMT_LEFT_J:
1062                 regs->srgr2     |= FPER(framesize - 1);
1063                 regs->srgr1     |= FWID((framesize >> 1) - 1);
1064                 break;
1065         case SND_SOC_DAIFMT_DSP_A:
1066         case SND_SOC_DAIFMT_DSP_B:
1067                 regs->srgr2     |= FPER(framesize - 1);
1068                 regs->srgr1     |= FWID(0);
1069                 break;
1070         }
1071
1072         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1073         mcbsp->wlen = wlen;
1074         mcbsp->configured = 1;
1075
1076         return 0;
1077 }
1078
1079 /*
1080  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1081  * cache is initialized here
1082  */
1083 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1084                                       unsigned int fmt)
1085 {
1086         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1087         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1088         bool inv_fs = false;
1089
1090         if (mcbsp->configured)
1091                 return 0;
1092
1093         mcbsp->fmt = fmt;
1094         memset(regs, 0, sizeof(*regs));
1095         /* Generic McBSP register settings */
1096         regs->spcr2     |= XINTM(3) | FREE;
1097         regs->spcr1     |= RINTM(3);
1098         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1099         if (!mcbsp->pdata->has_ccr) {
1100                 regs->rcr2      |= RFIG;
1101                 regs->xcr2      |= XFIG;
1102         }
1103
1104         /* Configure XCCR/RCCR only for revisions which have ccr registers */
1105         if (mcbsp->pdata->has_ccr) {
1106                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1107                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1108         }
1109
1110         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1111         case SND_SOC_DAIFMT_I2S:
1112                 /* 1-bit data delay */
1113                 regs->rcr2      |= RDATDLY(1);
1114                 regs->xcr2      |= XDATDLY(1);
1115                 break;
1116         case SND_SOC_DAIFMT_LEFT_J:
1117                 /* 0-bit data delay */
1118                 regs->rcr2      |= RDATDLY(0);
1119                 regs->xcr2      |= XDATDLY(0);
1120                 regs->spcr1     |= RJUST(2);
1121                 /* Invert FS polarity configuration */
1122                 inv_fs = true;
1123                 break;
1124         case SND_SOC_DAIFMT_DSP_A:
1125                 /* 1-bit data delay */
1126                 regs->rcr2      |= RDATDLY(1);
1127                 regs->xcr2      |= XDATDLY(1);
1128                 /* Invert FS polarity configuration */
1129                 inv_fs = true;
1130                 break;
1131         case SND_SOC_DAIFMT_DSP_B:
1132                 /* 0-bit data delay */
1133                 regs->rcr2      |= RDATDLY(0);
1134                 regs->xcr2      |= XDATDLY(0);
1135                 /* Invert FS polarity configuration */
1136                 inv_fs = true;
1137                 break;
1138         default:
1139                 /* Unsupported data format */
1140                 return -EINVAL;
1141         }
1142
1143         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1144         case SND_SOC_DAIFMT_CBS_CFS:
1145                 /* McBSP master. Set FS and bit clocks as outputs */
1146                 regs->pcr0      |= FSXM | FSRM |
1147                                    CLKXM | CLKRM;
1148                 /* Sample rate generator drives the FS */
1149                 regs->srgr2     |= FSGM;
1150                 break;
1151         case SND_SOC_DAIFMT_CBM_CFS:
1152                 /* McBSP slave. FS clock as output */
1153                 regs->srgr2     |= FSGM;
1154                 regs->pcr0      |= FSXM | FSRM;
1155                 break;
1156         case SND_SOC_DAIFMT_CBM_CFM:
1157                 /* McBSP slave */
1158                 break;
1159         default:
1160                 /* Unsupported master/slave configuration */
1161                 return -EINVAL;
1162         }
1163
1164         /* Set bit clock (CLKX/CLKR) and FS polarities */
1165         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1166         case SND_SOC_DAIFMT_NB_NF:
1167                 /*
1168                  * Normal BCLK + FS.
1169                  * FS active low. TX data driven on falling edge of bit clock
1170                  * and RX data sampled on rising edge of bit clock.
1171                  */
1172                 regs->pcr0      |= FSXP | FSRP |
1173                                    CLKXP | CLKRP;
1174                 break;
1175         case SND_SOC_DAIFMT_NB_IF:
1176                 regs->pcr0      |= CLKXP | CLKRP;
1177                 break;
1178         case SND_SOC_DAIFMT_IB_NF:
1179                 regs->pcr0      |= FSXP | FSRP;
1180                 break;
1181         case SND_SOC_DAIFMT_IB_IF:
1182                 break;
1183         default:
1184                 return -EINVAL;
1185         }
1186         if (inv_fs == true)
1187                 regs->pcr0 ^= FSXP | FSRP;
1188
1189         return 0;
1190 }
1191
1192 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1193                                      int div_id, int div)
1194 {
1195         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1196         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1197
1198         if (div_id != OMAP_MCBSP_CLKGDV)
1199                 return -ENODEV;
1200
1201         mcbsp->clk_div = div;
1202         regs->srgr1     &= ~CLKGDV(0xff);
1203         regs->srgr1     |= CLKGDV(div - 1);
1204
1205         return 0;
1206 }
1207
1208 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1209                                          int clk_id, unsigned int freq,
1210                                          int dir)
1211 {
1212         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1213         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1214         int err = 0;
1215
1216         if (mcbsp->active) {
1217                 if (freq == mcbsp->in_freq)
1218                         return 0;
1219                 else
1220                         return -EBUSY;
1221         }
1222
1223         mcbsp->in_freq = freq;
1224         regs->srgr2 &= ~CLKSM;
1225         regs->pcr0 &= ~SCLKME;
1226
1227         switch (clk_id) {
1228         case OMAP_MCBSP_SYSCLK_CLK:
1229                 regs->srgr2     |= CLKSM;
1230                 break;
1231         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1232                 if (mcbsp_omap1()) {
1233                         err = -EINVAL;
1234                         break;
1235                 }
1236                 err = omap2_mcbsp_set_clks_src(mcbsp,
1237                                                MCBSP_CLKS_PRCM_SRC);
1238                 break;
1239         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1240                 if (mcbsp_omap1()) {
1241                         err = 0;
1242                         break;
1243                 }
1244                 err = omap2_mcbsp_set_clks_src(mcbsp,
1245                                                MCBSP_CLKS_PAD_SRC);
1246                 break;
1247
1248         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1249                 regs->srgr2     |= CLKSM;
1250                 regs->pcr0      |= SCLKME;
1251                 /*
1252                  * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1253                  * disable output on those pins. This enables to inject the
1254                  * reference clock through CLKX/CLKR. For this to work
1255                  * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1256                  */
1257                 regs->pcr0      &= ~CLKXM;
1258                 break;
1259         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1260                 regs->pcr0      |= SCLKME;
1261                 /* Disable ouput on CLKR pin in master mode */
1262                 regs->pcr0      &= ~CLKRM;
1263                 break;
1264         default:
1265                 err = -ENODEV;
1266         }
1267
1268         return err;
1269 }
1270
1271 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1272         .startup        = omap_mcbsp_dai_startup,
1273         .shutdown       = omap_mcbsp_dai_shutdown,
1274         .prepare        = omap_mcbsp_dai_prepare,
1275         .trigger        = omap_mcbsp_dai_trigger,
1276         .delay          = omap_mcbsp_dai_delay,
1277         .hw_params      = omap_mcbsp_dai_hw_params,
1278         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
1279         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
1280         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
1281 };
1282
1283 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1284 {
1285         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1286
1287         pm_runtime_enable(mcbsp->dev);
1288
1289         snd_soc_dai_init_dma_data(dai,
1290                                   &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1291                                   &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1292
1293         return 0;
1294 }
1295
1296 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1297 {
1298         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1299
1300         pm_runtime_disable(mcbsp->dev);
1301
1302         return 0;
1303 }
1304
1305 static struct snd_soc_dai_driver omap_mcbsp_dai = {
1306         .probe = omap_mcbsp_probe,
1307         .remove = omap_mcbsp_remove,
1308         .playback = {
1309                 .channels_min = 1,
1310                 .channels_max = 16,
1311                 .rates = OMAP_MCBSP_RATES,
1312                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1313         },
1314         .capture = {
1315                 .channels_min = 1,
1316                 .channels_max = 16,
1317                 .rates = OMAP_MCBSP_RATES,
1318                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1319         },
1320         .ops = &mcbsp_dai_ops,
1321 };
1322
1323 static const struct snd_soc_component_driver omap_mcbsp_component = {
1324         .name           = "omap-mcbsp",
1325 };
1326
1327 static struct omap_mcbsp_platform_data omap2420_pdata = {
1328         .reg_step = 4,
1329         .reg_size = 2,
1330 };
1331
1332 static struct omap_mcbsp_platform_data omap2430_pdata = {
1333         .reg_step = 4,
1334         .reg_size = 4,
1335         .has_ccr = true,
1336 };
1337
1338 static struct omap_mcbsp_platform_data omap3_pdata = {
1339         .reg_step = 4,
1340         .reg_size = 4,
1341         .has_ccr = true,
1342         .has_wakeup = true,
1343 };
1344
1345 static struct omap_mcbsp_platform_data omap4_pdata = {
1346         .reg_step = 4,
1347         .reg_size = 4,
1348         .has_ccr = true,
1349         .has_wakeup = true,
1350 };
1351
1352 static const struct of_device_id omap_mcbsp_of_match[] = {
1353         {
1354                 .compatible = "ti,omap2420-mcbsp",
1355                 .data = &omap2420_pdata,
1356         },
1357         {
1358                 .compatible = "ti,omap2430-mcbsp",
1359                 .data = &omap2430_pdata,
1360         },
1361         {
1362                 .compatible = "ti,omap3-mcbsp",
1363                 .data = &omap3_pdata,
1364         },
1365         {
1366                 .compatible = "ti,omap4-mcbsp",
1367                 .data = &omap4_pdata,
1368         },
1369         { },
1370 };
1371 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1372
1373 static int asoc_mcbsp_probe(struct platform_device *pdev)
1374 {
1375         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1376         struct omap_mcbsp *mcbsp;
1377         const struct of_device_id *match;
1378         int ret;
1379
1380         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1381         if (match) {
1382                 struct device_node *node = pdev->dev.of_node;
1383                 struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1384                 int buffer_size;
1385
1386                 pdata = devm_kzalloc(&pdev->dev,
1387                                      sizeof(struct omap_mcbsp_platform_data),
1388                                      GFP_KERNEL);
1389                 if (!pdata)
1390                         return -ENOMEM;
1391
1392                 memcpy(pdata, match->data, sizeof(*pdata));
1393                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1394                         pdata->buffer_size = buffer_size;
1395                 if (pdata_quirk)
1396                         pdata->force_ick_on = pdata_quirk->force_ick_on;
1397         } else if (!pdata) {
1398                 dev_err(&pdev->dev, "missing platform data.\n");
1399                 return -EINVAL;
1400         }
1401         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1402         if (!mcbsp)
1403                 return -ENOMEM;
1404
1405         mcbsp->id = pdev->id;
1406         mcbsp->pdata = pdata;
1407         mcbsp->dev = &pdev->dev;
1408         platform_set_drvdata(pdev, mcbsp);
1409
1410         ret = omap_mcbsp_init(pdev);
1411         if (ret)
1412                 return ret;
1413
1414         if (mcbsp->pdata->reg_size == 2) {
1415                 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1416                 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1417         }
1418
1419         ret = devm_snd_soc_register_component(&pdev->dev,
1420                                               &omap_mcbsp_component,
1421                                               &omap_mcbsp_dai, 1);
1422         if (ret)
1423                 return ret;
1424
1425         return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1426 }
1427
1428 static int asoc_mcbsp_remove(struct platform_device *pdev)
1429 {
1430         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1431
1432         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1433                 mcbsp->pdata->ops->free(mcbsp->id);
1434
1435         if (pm_qos_request_active(&mcbsp->pm_qos_req))
1436                 pm_qos_remove_request(&mcbsp->pm_qos_req);
1437
1438         if (mcbsp->pdata->buffer_size)
1439                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1440
1441         omap_mcbsp_st_cleanup(pdev);
1442
1443         return 0;
1444 }
1445
1446 static struct platform_driver asoc_mcbsp_driver = {
1447         .driver = {
1448                         .name = "omap-mcbsp",
1449                         .of_match_table = omap_mcbsp_of_match,
1450         },
1451
1452         .probe = asoc_mcbsp_probe,
1453         .remove = asoc_mcbsp_remove,
1454 };
1455
1456 module_platform_driver(asoc_mcbsp_driver);
1457
1458 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1459 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1460 MODULE_LICENSE("GPL");
1461 MODULE_ALIAS("platform:omap-mcbsp");