1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra_asoc_utils.c - Harmony machine ASoC driver
5 * Author: Stephen Warren <swarren@nvidia.com>
6 * Copyright (C) 2010,2012 - NVIDIA, Inc.
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
16 #include "tegra_asoc_utils.h"
18 int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
30 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
31 new_baseclock = 56448000;
32 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
33 new_baseclock = 564480000;
35 new_baseclock = 282240000;
43 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
44 new_baseclock = 73728000;
45 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
46 new_baseclock = 552960000;
48 new_baseclock = 368640000;
54 clk_change = ((new_baseclock != data->set_baseclock) ||
55 (mclk != data->set_mclk));
59 data->set_baseclock = 0;
62 clk_disable_unprepare(data->clk_cdev1);
63 clk_disable_unprepare(data->clk_pll_a_out0);
64 clk_disable_unprepare(data->clk_pll_a);
66 err = clk_set_rate(data->clk_pll_a, new_baseclock);
68 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
72 err = clk_set_rate(data->clk_pll_a_out0, mclk);
74 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
78 /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
80 err = clk_prepare_enable(data->clk_pll_a);
82 dev_err(data->dev, "Can't enable pll_a: %d\n", err);
86 err = clk_prepare_enable(data->clk_pll_a_out0);
88 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
92 err = clk_prepare_enable(data->clk_cdev1);
94 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
98 data->set_baseclock = new_baseclock;
99 data->set_mclk = mclk;
103 EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
105 int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
107 const int pll_rate = 73728000;
108 const int ac97_rate = 24576000;
111 clk_disable_unprepare(data->clk_cdev1);
112 clk_disable_unprepare(data->clk_pll_a_out0);
113 clk_disable_unprepare(data->clk_pll_a);
116 * AC97 rate is fixed at 24.576MHz and is used for both the host
117 * controller and the external codec
119 err = clk_set_rate(data->clk_pll_a, pll_rate);
121 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
125 err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);
127 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
131 /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
133 err = clk_prepare_enable(data->clk_pll_a);
135 dev_err(data->dev, "Can't enable pll_a: %d\n", err);
139 err = clk_prepare_enable(data->clk_pll_a_out0);
141 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
145 err = clk_prepare_enable(data->clk_cdev1);
147 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
151 data->set_baseclock = pll_rate;
152 data->set_mclk = ac97_rate;
156 EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
158 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
165 if (of_machine_is_compatible("nvidia,tegra20"))
166 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
167 else if (of_machine_is_compatible("nvidia,tegra30"))
168 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
169 else if (of_machine_is_compatible("nvidia,tegra114"))
170 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114;
171 else if (of_machine_is_compatible("nvidia,tegra124"))
172 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA124;
174 dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
178 data->clk_pll_a = clk_get(dev, "pll_a");
179 if (IS_ERR(data->clk_pll_a)) {
180 dev_err(data->dev, "Can't retrieve clk pll_a\n");
181 ret = PTR_ERR(data->clk_pll_a);
185 data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0");
186 if (IS_ERR(data->clk_pll_a_out0)) {
187 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
188 ret = PTR_ERR(data->clk_pll_a_out0);
192 data->clk_cdev1 = clk_get(dev, "mclk");
193 if (IS_ERR(data->clk_cdev1)) {
194 dev_err(data->dev, "Can't retrieve clk cdev1\n");
195 ret = PTR_ERR(data->clk_cdev1);
196 goto err_put_pll_a_out0;
199 ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
206 clk_put(data->clk_cdev1);
208 clk_put(data->clk_pll_a_out0);
210 clk_put(data->clk_pll_a);
214 EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
216 void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
218 clk_put(data->clk_cdev1);
219 clk_put(data->clk_pll_a_out0);
220 clk_put(data->clk_pll_a);
222 EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
224 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
225 MODULE_DESCRIPTION("Tegra ASoC utility code");
226 MODULE_LICENSE("GPL");