sound/soc/tegra/tegra210_ahub.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // tegra210_ahub.c - Tegra210 AHUB driver
   4 //
   5 // Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
   6
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/module.h>
  10 #include <linux/of_platform.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/regmap.h>
  14 #include <sound/soc.h>
  15 #include "tegra210_ahub.h"
  16
  17 static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl,
  18                                      struct snd_ctl_elem_value *uctl)
  19 {
  20         struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
  21         struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
  22         struct soc_enum *e = (struct soc_enum *)kctl->private_value;
  23         unsigned int reg, i, bit_pos = 0;
  24
  25         /*
  26          * Find the bit position of current MUX input.
  27          * If nothing is set, position would be 0 and it corresponds to 'None'.
  28          */
  29         for (i = 0; i < ahub->soc_data->reg_count; i++) {
  30                 unsigned int reg_val;
  31
  32                 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
  33                 reg_val = snd_soc_component_read(cmpnt, reg);
  34                 reg_val &= ahub->soc_data->mask[i];
  35
  36                 if (reg_val) {
  37                         bit_pos = ffs(reg_val) +
  38                                   (8 * cmpnt->val_bytes * i);
  39                         break;
  40                 }
  41         }
  42
  43         /* Find index related to the item in array *_ahub_mux_texts[] */
  44         for (i = 0; i < e->items; i++) {
  45                 if (bit_pos == e->values[i]) {
  46                         uctl->value.enumerated.item[0] = i;
  47                         break;
  48                 }
  49         }
  50
  51         return 0;
  52 }
  53
  54 static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl,
  55                                      struct snd_ctl_elem_value *uctl)
  56 {
  57         struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
  58         struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
  59         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl);
  60         struct soc_enum *e = (struct soc_enum *)kctl->private_value;
  61         struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { };
  62         unsigned int *item = uctl->value.enumerated.item;
  63         unsigned int value = e->values[item[0]];
  64         unsigned int i, bit_pos, reg_idx = 0, reg_val = 0;
  65         int change = 0;
  66
  67         if (item[0] >= e->items)
  68                 return -EINVAL;
  69
  70         if (value) {
  71                 /* Get the register index and value to set */
  72                 reg_idx = (value - 1) / (8 * cmpnt->val_bytes);
  73                 bit_pos = (value - 1) % (8 * cmpnt->val_bytes);
  74                 reg_val = BIT(bit_pos);
  75         }
  76
  77         /*
  78          * Run through all parts of a MUX register to find the state changes.
  79          * There will be an additional update if new MUX input value is from
  80          * different part of the MUX register.
  81          */
  82         for (i = 0; i < ahub->soc_data->reg_count; i++) {
  83                 update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
  84                 update[i].val = (i == reg_idx) ? reg_val : 0;
  85                 update[i].mask = ahub->soc_data->mask[i];
  86                 update[i].kcontrol = kctl;
  87
  88                 /* Update widget power if state has changed */
  89                 if (snd_soc_component_test_bits(cmpnt, update[i].reg,
  90                                                 update[i].mask,
  91                                                 update[i].val))
  92                         change |= snd_soc_dapm_mux_update_power(dapm, kctl,
  93                                                                 item[0], e,
  94                                                                 &update[i]);
  95         }
  96
  97         return change;
  98 }
  99
 100 static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
 101         DAI(ADMAIF1),
 102         DAI(ADMAIF2),
 103         DAI(ADMAIF3),
 104         DAI(ADMAIF4),
 105         DAI(ADMAIF5),
 106         DAI(ADMAIF6),
 107         DAI(ADMAIF7),
 108         DAI(ADMAIF8),
 109         DAI(ADMAIF9),
 110         DAI(ADMAIF10),
 111         /* XBAR <-> I2S <-> Codec */
 112         DAI(I2S1),
 113         DAI(I2S2),
 114         DAI(I2S3),
 115         DAI(I2S4),
 116         DAI(I2S5),
 117         /* XBAR <- DMIC <- Codec */
 118         DAI(DMIC1),
 119         DAI(DMIC2),
 120         DAI(DMIC3),
 121         /* XBAR -> SFC -> XBAR */
 122         DAI(SFC1 RX),
 123         DAI(SFC1 TX),
 124         DAI(SFC2 RX),
 125         DAI(SFC2 TX),
 126         DAI(SFC3 RX),
 127         DAI(SFC3 TX),
 128         DAI(SFC4 RX),
 129         DAI(SFC4 TX),
 130         /* XBAR -> MVC -> XBAR */
 131         DAI(MVC1 RX),
 132         DAI(MVC1 TX),
 133         DAI(MVC2 RX),
 134         DAI(MVC2 TX),
 135         /* XBAR -> AMX(4:1) -> XBAR */
 136         DAI(AMX1 RX1),
 137         DAI(AMX1 RX2),
 138         DAI(AMX1 RX3),
 139         DAI(AMX1 RX4),
 140         DAI(AMX1),
 141         DAI(AMX2 RX1),
 142         DAI(AMX2 RX2),
 143         DAI(AMX2 RX3),
 144         DAI(AMX2 RX4),
 145         DAI(AMX2),
 146         /* XBAR -> ADX(1:4) -> XBAR */
 147         DAI(ADX1),
 148         DAI(ADX1 TX1),
 149         DAI(ADX1 TX2),
 150         DAI(ADX1 TX3),
 151         DAI(ADX1 TX4),
 152         DAI(ADX2),
 153         DAI(ADX2 TX1),
 154         DAI(ADX2 TX2),
 155         DAI(ADX2 TX3),
 156         DAI(ADX2 TX4),
 157         /* XBAR -> MIXER(10:5) -> XBAR */
 158         DAI(MIXER1 RX1),
 159         DAI(MIXER1 RX2),
 160         DAI(MIXER1 RX3),
 161         DAI(MIXER1 RX4),
 162         DAI(MIXER1 RX5),
 163         DAI(MIXER1 RX6),
 164         DAI(MIXER1 RX7),
 165         DAI(MIXER1 RX8),
 166         DAI(MIXER1 RX9),
 167         DAI(MIXER1 RX10),
 168         DAI(MIXER1 TX1),
 169         DAI(MIXER1 TX2),
 170         DAI(MIXER1 TX3),
 171         DAI(MIXER1 TX4),
 172         DAI(MIXER1 TX5),
 173         /* XBAR -> OPE -> XBAR */
 174         DAI(OPE1 RX),
 175         DAI(OPE1 TX),
 176         DAI(OPE2 RX),
 177         DAI(OPE2 TX),
 178 };
 179
 180 static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
 181         DAI(ADMAIF1),
 182         DAI(ADMAIF2),
 183         DAI(ADMAIF3),
 184         DAI(ADMAIF4),
 185         DAI(ADMAIF5),
 186         DAI(ADMAIF6),
 187         DAI(ADMAIF7),
 188         DAI(ADMAIF8),
 189         DAI(ADMAIF9),
 190         DAI(ADMAIF10),
 191         DAI(ADMAIF11),
 192         DAI(ADMAIF12),
 193         DAI(ADMAIF13),
 194         DAI(ADMAIF14),
 195         DAI(ADMAIF15),
 196         DAI(ADMAIF16),
 197         DAI(ADMAIF17),
 198         DAI(ADMAIF18),
 199         DAI(ADMAIF19),
 200         DAI(ADMAIF20),
 201         /* XBAR <-> I2S <-> Codec */
 202         DAI(I2S1),
 203         DAI(I2S2),
 204         DAI(I2S3),
 205         DAI(I2S4),
 206         DAI(I2S5),
 207         DAI(I2S6),
 208         /* XBAR <- DMIC <- Codec */
 209         DAI(DMIC1),
 210         DAI(DMIC2),
 211         DAI(DMIC3),
 212         DAI(DMIC4),
 213         /* XBAR -> DSPK -> Codec */
 214         DAI(DSPK1),
 215         DAI(DSPK2),
 216         /* XBAR -> SFC -> XBAR */
 217         DAI(SFC1 RX),
 218         DAI(SFC1 TX),
 219         DAI(SFC2 RX),
 220         DAI(SFC2 TX),
 221         DAI(SFC3 RX),
 222         DAI(SFC3 TX),
 223         DAI(SFC4 RX),
 224         DAI(SFC4 TX),
 225         /* XBAR -> MVC -> XBAR */
 226         DAI(MVC1 RX),
 227         DAI(MVC1 TX),
 228         DAI(MVC2 RX),
 229         DAI(MVC2 TX),
 230         /* XBAR -> AMX(4:1) -> XBAR */
 231         DAI(AMX1 RX1),
 232         DAI(AMX1 RX2),
 233         DAI(AMX1 RX3),
 234         DAI(AMX1 RX4),
 235         DAI(AMX1),
 236         DAI(AMX2 RX1),
 237         DAI(AMX2 RX2),
 238         DAI(AMX2 RX3),
 239         DAI(AMX2 RX4),
 240         DAI(AMX2),
 241         DAI(AMX3 RX1),
 242         DAI(AMX3 RX2),
 243         DAI(AMX3 RX3),
 244         DAI(AMX3 RX4),
 245         DAI(AMX3),
 246         DAI(AMX4 RX1),
 247         DAI(AMX4 RX2),
 248         DAI(AMX4 RX3),
 249         DAI(AMX4 RX4),
 250         DAI(AMX4),
 251         /* XBAR -> ADX(1:4) -> XBAR */
 252         DAI(ADX1),
 253         DAI(ADX1 TX1),
 254         DAI(ADX1 TX2),
 255         DAI(ADX1 TX3),
 256         DAI(ADX1 TX4),
 257         DAI(ADX2),
 258         DAI(ADX2 TX1),
 259         DAI(ADX2 TX2),
 260         DAI(ADX2 TX3),
 261         DAI(ADX2 TX4),
 262         DAI(ADX3),
 263         DAI(ADX3 TX1),
 264         DAI(ADX3 TX2),
 265         DAI(ADX3 TX3),
 266         DAI(ADX3 TX4),
 267         DAI(ADX4),
 268         DAI(ADX4 TX1),
 269         DAI(ADX4 TX2),
 270         DAI(ADX4 TX3),
 271         DAI(ADX4 TX4),
 272         /* XBAR -> MIXER1(10:5) -> XBAR */
 273         DAI(MIXER1 RX1),
 274         DAI(MIXER1 RX2),
 275         DAI(MIXER1 RX3),
 276         DAI(MIXER1 RX4),
 277         DAI(MIXER1 RX5),
 278         DAI(MIXER1 RX6),
 279         DAI(MIXER1 RX7),
 280         DAI(MIXER1 RX8),
 281         DAI(MIXER1 RX9),
 282         DAI(MIXER1 RX10),
 283         DAI(MIXER1 TX1),
 284         DAI(MIXER1 TX2),
 285         DAI(MIXER1 TX3),
 286         DAI(MIXER1 TX4),
 287         DAI(MIXER1 TX5),
 288         /* XBAR -> ASRC -> XBAR */
 289         DAI(ASRC1 RX1),
 290         DAI(ASRC1 TX1),
 291         DAI(ASRC1 RX2),
 292         DAI(ASRC1 TX2),
 293         DAI(ASRC1 RX3),
 294         DAI(ASRC1 TX3),
 295         DAI(ASRC1 RX4),
 296         DAI(ASRC1 TX4),
 297         DAI(ASRC1 RX5),
 298         DAI(ASRC1 TX5),
 299         DAI(ASRC1 RX6),
 300         DAI(ASRC1 TX6),
 301         DAI(ASRC1 RX7),
 302         /* XBAR -> OPE -> XBAR */
 303         DAI(OPE1 RX),
 304         DAI(OPE1 TX),
 305 };
 306
 307 static const char * const tegra210_ahub_mux_texts[] = {
 308         "None",
 309         "ADMAIF1",
 310         "ADMAIF2",
 311         "ADMAIF3",
 312         "ADMAIF4",
 313         "ADMAIF5",
 314         "ADMAIF6",
 315         "ADMAIF7",
 316         "ADMAIF8",
 317         "ADMAIF9",
 318         "ADMAIF10",
 319         "I2S1",
 320         "I2S2",
 321         "I2S3",
 322         "I2S4",
 323         "I2S5",
 324         "DMIC1",
 325         "DMIC2",
 326         "DMIC3",
 327         "SFC1",
 328         "SFC2",
 329         "SFC3",
 330         "SFC4",
 331         "MVC1",
 332         "MVC2",
 333         "AMX1",
 334         "AMX2",
 335         "ADX1 TX1",
 336         "ADX1 TX2",
 337         "ADX1 TX3",
 338         "ADX1 TX4",
 339         "ADX2 TX1",
 340         "ADX2 TX2",
 341         "ADX2 TX3",
 342         "ADX2 TX4",
 343         "MIXER1 TX1",
 344         "MIXER1 TX2",
 345         "MIXER1 TX3",
 346         "MIXER1 TX4",
 347         "MIXER1 TX5",
 348         "OPE1",
 349         "OPE2",
 350 };
 351
 352 static const char * const tegra186_ahub_mux_texts[] = {
 353         "None",
 354         "ADMAIF1",
 355         "ADMAIF2",
 356         "ADMAIF3",
 357         "ADMAIF4",
 358         "ADMAIF5",
 359         "ADMAIF6",
 360         "ADMAIF7",
 361         "ADMAIF8",
 362         "ADMAIF9",
 363         "ADMAIF10",
 364         "ADMAIF11",
 365         "ADMAIF12",
 366         "ADMAIF13",
 367         "ADMAIF14",
 368         "ADMAIF15",
 369         "ADMAIF16",
 370         "I2S1",
 371         "I2S2",
 372         "I2S3",
 373         "I2S4",
 374         "I2S5",
 375         "I2S6",
 376         "ADMAIF17",
 377         "ADMAIF18",
 378         "ADMAIF19",
 379         "ADMAIF20",
 380         "DMIC1",
 381         "DMIC2",
 382         "DMIC3",
 383         "DMIC4",
 384         "SFC1",
 385         "SFC2",
 386         "SFC3",
 387         "SFC4",
 388         "MVC1",
 389         "MVC2",
 390         "AMX1",
 391         "AMX2",
 392         "AMX3",
 393         "AMX4",
 394         "ADX1 TX1",
 395         "ADX1 TX2",
 396         "ADX1 TX3",
 397         "ADX1 TX4",
 398         "ADX2 TX1",
 399         "ADX2 TX2",
 400         "ADX2 TX3",
 401         "ADX2 TX4",
 402         "ADX3 TX1",
 403         "ADX3 TX2",
 404         "ADX3 TX3",
 405         "ADX3 TX4",
 406         "ADX4 TX1",
 407         "ADX4 TX2",
 408         "ADX4 TX3",
 409         "ADX4 TX4",
 410         "MIXER1 TX1",
 411         "MIXER1 TX2",
 412         "MIXER1 TX3",
 413         "MIXER1 TX4",
 414         "MIXER1 TX5",
 415         "ASRC1 TX1",
 416         "ASRC1 TX2",
 417         "ASRC1 TX3",
 418         "ASRC1 TX4",
 419         "ASRC1 TX5",
 420         "ASRC1 TX6",
 421         "OPE1",
 422 };
 423
 424 static const unsigned int tegra210_ahub_mux_values[] = {
 425         0,
 426         /* ADMAIF */
 427         MUX_VALUE(0, 0),
 428         MUX_VALUE(0, 1),
 429         MUX_VALUE(0, 2),
 430         MUX_VALUE(0, 3),
 431         MUX_VALUE(0, 4),
 432         MUX_VALUE(0, 5),
 433         MUX_VALUE(0, 6),
 434         MUX_VALUE(0, 7),
 435         MUX_VALUE(0, 8),
 436         MUX_VALUE(0, 9),
 437         /* I2S */
 438         MUX_VALUE(0, 16),
 439         MUX_VALUE(0, 17),
 440         MUX_VALUE(0, 18),
 441         MUX_VALUE(0, 19),
 442         MUX_VALUE(0, 20),
 443         /* DMIC */
 444         MUX_VALUE(2, 18),
 445         MUX_VALUE(2, 19),
 446         MUX_VALUE(2, 20),
 447         /* SFC */
 448         MUX_VALUE(0, 24),
 449         MUX_VALUE(0, 25),
 450         MUX_VALUE(0, 26),
 451         MUX_VALUE(0, 27),
 452         /* MVC */
 453         MUX_VALUE(2, 8),
 454         MUX_VALUE(2, 9),
 455         /* AMX */
 456         MUX_VALUE(1, 8),
 457         MUX_VALUE(1, 9),
 458         /* ADX */
 459         MUX_VALUE(2, 24),
 460         MUX_VALUE(2, 25),
 461         MUX_VALUE(2, 26),
 462         MUX_VALUE(2, 27),
 463         MUX_VALUE(2, 28),
 464         MUX_VALUE(2, 29),
 465         MUX_VALUE(2, 30),
 466         MUX_VALUE(2, 31),
 467         /* MIXER */
 468         MUX_VALUE(1, 0),
 469         MUX_VALUE(1, 1),
 470         MUX_VALUE(1, 2),
 471         MUX_VALUE(1, 3),
 472         MUX_VALUE(1, 4),
 473         /* OPE */
 474         MUX_VALUE(2, 0),
 475         MUX_VALUE(2, 1),
 476 };
 477
 478 static const unsigned int tegra186_ahub_mux_values[] = {
 479         0,
 480         /* ADMAIF */
 481         MUX_VALUE(0, 0),
 482         MUX_VALUE(0, 1),
 483         MUX_VALUE(0, 2),
 484         MUX_VALUE(0, 3),
 485         MUX_VALUE(0, 4),
 486         MUX_VALUE(0, 5),
 487         MUX_VALUE(0, 6),
 488         MUX_VALUE(0, 7),
 489         MUX_VALUE(0, 8),
 490         MUX_VALUE(0, 9),
 491         MUX_VALUE(0, 10),
 492         MUX_VALUE(0, 11),
 493         MUX_VALUE(0, 12),
 494         MUX_VALUE(0, 13),
 495         MUX_VALUE(0, 14),
 496         MUX_VALUE(0, 15),
 497         /* I2S */
 498         MUX_VALUE(0, 16),
 499         MUX_VALUE(0, 17),
 500         MUX_VALUE(0, 18),
 501         MUX_VALUE(0, 19),
 502         MUX_VALUE(0, 20),
 503         MUX_VALUE(0, 21),
 504         /* ADMAIF */
 505         MUX_VALUE(3, 16),
 506         MUX_VALUE(3, 17),
 507         MUX_VALUE(3, 18),
 508         MUX_VALUE(3, 19),
 509         /* DMIC */
 510         MUX_VALUE(2, 18),
 511         MUX_VALUE(2, 19),
 512         MUX_VALUE(2, 20),
 513         MUX_VALUE(2, 21),
 514         /* SFC */
 515         MUX_VALUE(0, 24),
 516         MUX_VALUE(0, 25),
 517         MUX_VALUE(0, 26),
 518         MUX_VALUE(0, 27),
 519         /* MVC */
 520         MUX_VALUE(2, 8),
 521         MUX_VALUE(2, 9),
 522         /* AMX */
 523         MUX_VALUE(1, 8),
 524         MUX_VALUE(1, 9),
 525         MUX_VALUE(1, 10),
 526         MUX_VALUE(1, 11),
 527         /* ADX */
 528         MUX_VALUE(2, 24),
 529         MUX_VALUE(2, 25),
 530         MUX_VALUE(2, 26),
 531         MUX_VALUE(2, 27),
 532         MUX_VALUE(2, 28),
 533         MUX_VALUE(2, 29),
 534         MUX_VALUE(2, 30),
 535         MUX_VALUE(2, 31),
 536         MUX_VALUE(3, 0),
 537         MUX_VALUE(3, 1),
 538         MUX_VALUE(3, 2),
 539         MUX_VALUE(3, 3),
 540         MUX_VALUE(3, 4),
 541         MUX_VALUE(3, 5),
 542         MUX_VALUE(3, 6),
 543         MUX_VALUE(3, 7),
 544         /* MIXER */
 545         MUX_VALUE(1, 0),
 546         MUX_VALUE(1, 1),
 547         MUX_VALUE(1, 2),
 548         MUX_VALUE(1, 3),
 549         MUX_VALUE(1, 4),
 550         /* ASRC */
 551         MUX_VALUE(3, 24),
 552         MUX_VALUE(3, 25),
 553         MUX_VALUE(3, 26),
 554         MUX_VALUE(3, 27),
 555         MUX_VALUE(3, 28),
 556         MUX_VALUE(3, 29),
 557         /* OPE */
 558         MUX_VALUE(2, 0),
 559 };
 560
 561 /* Controls for t210 */
 562 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00);
 563 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01);
 564 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02);
 565 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03);
 566 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04);
 567 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05);
 568 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06);
 569 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07);
 570 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08);
 571 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09);
 572 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10);
 573 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
 574 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
 575 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
 576 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
 577 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18);
 578 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19);
 579 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a);
 580 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b);
 581 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48);
 582 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49);
 583 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50);
 584 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51);
 585 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52);
 586 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53);
 587 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54);
 588 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55);
 589 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56);
 590 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57);
 591 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58);
 592 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59);
 593 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20);
 594 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21);
 595 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22);
 596 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23);
 597 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24);
 598 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25);
 599 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26);
 600 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27);
 601 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28);
 602 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29);
 603 MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40);
 604 MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41);
 605
 606 /* Controls for t186 */
 607 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
 608 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01);
 609 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02);
 610 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03);
 611 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04);
 612 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05);
 613 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06);
 614 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07);
 615 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08);
 616 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09);
 617 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10);
 618 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11);
 619 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12);
 620 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13);
 621 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14);
 622 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a);
 623 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b);
 624 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c);
 625 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d);
 626 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e);
 627 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f);
 628 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15);
 629 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30);
 630 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31);
 631 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
 632 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
 633 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
 634 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
 635 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18);
 636 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19);
 637 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a);
 638 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b);
 639 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48);
 640 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49);
 641 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50);
 642 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51);
 643 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52);
 644 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53);
 645 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54);
 646 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55);
 647 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56);
 648 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57);
 649 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58);
 650 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59);
 651 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a);
 652 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b);
 653 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64);
 654 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65);
 655 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66);
 656 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67);
 657 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60);
 658 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61);
 659 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62);
 660 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63);
 661 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20);
 662 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21);
 663 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22);
 664 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23);
 665 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24);
 666 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25);
 667 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26);
 668 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27);
 669 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28);
 670 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29);
 671 MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c);
 672 MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d);
 673 MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e);
 674 MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f);
 675 MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70);
 676 MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71);
 677 MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72);
 678 MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40);
 679
 680 /* Controls for t234 */
 681 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44);
 682 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45);
 683 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48);
 684 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49);
 685 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a);
 686 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b);
 687 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c);
 688 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d);
 689 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e);
 690 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f);
 691 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50);
 692 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51);
 693 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52);
 694 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53);
 695 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58);
 696 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59);
 697 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a);
 698 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b);
 699 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c);
 700 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d);
 701 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e);
 702 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f);
 703 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60);
 704 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61);
 705 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62);
 706 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63);
 707 MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64);
 708 MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65);
 709 MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66);
 710 MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67);
 711 MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68);
 712 MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69);
 713 MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a);
 714
 715 static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
 716         WIDGETS("ADMAIF1", t210_admaif1_tx),
 717         WIDGETS("ADMAIF2", t210_admaif2_tx),
 718         WIDGETS("ADMAIF3", t210_admaif3_tx),
 719         WIDGETS("ADMAIF4", t210_admaif4_tx),
 720         WIDGETS("ADMAIF5", t210_admaif5_tx),
 721         WIDGETS("ADMAIF6", t210_admaif6_tx),
 722         WIDGETS("ADMAIF7", t210_admaif7_tx),
 723         WIDGETS("ADMAIF8", t210_admaif8_tx),
 724         WIDGETS("ADMAIF9", t210_admaif9_tx),
 725         WIDGETS("ADMAIF10", t210_admaif10_tx),
 726         WIDGETS("I2S1", t210_i2s1_tx),
 727         WIDGETS("I2S2", t210_i2s2_tx),
 728         WIDGETS("I2S3", t210_i2s3_tx),
 729         WIDGETS("I2S4", t210_i2s4_tx),
 730         WIDGETS("I2S5", t210_i2s5_tx),
 731         TX_WIDGETS("DMIC1"),
 732         TX_WIDGETS("DMIC2"),
 733         TX_WIDGETS("DMIC3"),
 734         WIDGETS("SFC1", t210_sfc1_tx),
 735         WIDGETS("SFC2", t210_sfc2_tx),
 736         WIDGETS("SFC3", t210_sfc3_tx),
 737         WIDGETS("SFC4", t210_sfc4_tx),
 738         WIDGETS("MVC1", t210_mvc1_tx),
 739         WIDGETS("MVC2", t210_mvc2_tx),
 740         WIDGETS("AMX1 RX1", t210_amx11_tx),
 741         WIDGETS("AMX1 RX2", t210_amx12_tx),
 742         WIDGETS("AMX1 RX3", t210_amx13_tx),
 743         WIDGETS("AMX1 RX4", t210_amx14_tx),
 744         WIDGETS("AMX2 RX1", t210_amx21_tx),
 745         WIDGETS("AMX2 RX2", t210_amx22_tx),
 746         WIDGETS("AMX2 RX3", t210_amx23_tx),
 747         WIDGETS("AMX2 RX4", t210_amx24_tx),
 748         TX_WIDGETS("AMX1"),
 749         TX_WIDGETS("AMX2"),
 750         WIDGETS("ADX1", t210_adx1_tx),
 751         WIDGETS("ADX2", t210_adx2_tx),
 752         TX_WIDGETS("ADX1 TX1"),
 753         TX_WIDGETS("ADX1 TX2"),
 754         TX_WIDGETS("ADX1 TX3"),
 755         TX_WIDGETS("ADX1 TX4"),
 756         TX_WIDGETS("ADX2 TX1"),
 757         TX_WIDGETS("ADX2 TX2"),
 758         TX_WIDGETS("ADX2 TX3"),
 759         TX_WIDGETS("ADX2 TX4"),
 760         WIDGETS("MIXER1 RX1", t210_mixer11_tx),
 761         WIDGETS("MIXER1 RX2", t210_mixer12_tx),
 762         WIDGETS("MIXER1 RX3", t210_mixer13_tx),
 763         WIDGETS("MIXER1 RX4", t210_mixer14_tx),
 764         WIDGETS("MIXER1 RX5", t210_mixer15_tx),
 765         WIDGETS("MIXER1 RX6", t210_mixer16_tx),
 766         WIDGETS("MIXER1 RX7", t210_mixer17_tx),
 767         WIDGETS("MIXER1 RX8", t210_mixer18_tx),
 768         WIDGETS("MIXER1 RX9", t210_mixer19_tx),
 769         WIDGETS("MIXER1 RX10", t210_mixer110_tx),
 770         TX_WIDGETS("MIXER1 TX1"),
 771         TX_WIDGETS("MIXER1 TX2"),
 772         TX_WIDGETS("MIXER1 TX3"),
 773         TX_WIDGETS("MIXER1 TX4"),
 774         TX_WIDGETS("MIXER1 TX5"),
 775         WIDGETS("OPE1", t210_ope1_tx),
 776         WIDGETS("OPE2", t210_ope2_tx),
 777 };
 778
 779 static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
 780         WIDGETS("ADMAIF1", t186_admaif1_tx),
 781         WIDGETS("ADMAIF2", t186_admaif2_tx),
 782         WIDGETS("ADMAIF3", t186_admaif3_tx),
 783         WIDGETS("ADMAIF4", t186_admaif4_tx),
 784         WIDGETS("ADMAIF5", t186_admaif5_tx),
 785         WIDGETS("ADMAIF6", t186_admaif6_tx),
 786         WIDGETS("ADMAIF7", t186_admaif7_tx),
 787         WIDGETS("ADMAIF8", t186_admaif8_tx),
 788         WIDGETS("ADMAIF9", t186_admaif9_tx),
 789         WIDGETS("ADMAIF10", t186_admaif10_tx),
 790         WIDGETS("ADMAIF11", t186_admaif11_tx),
 791         WIDGETS("ADMAIF12", t186_admaif12_tx),
 792         WIDGETS("ADMAIF13", t186_admaif13_tx),
 793         WIDGETS("ADMAIF14", t186_admaif14_tx),
 794         WIDGETS("ADMAIF15", t186_admaif15_tx),
 795         WIDGETS("ADMAIF16", t186_admaif16_tx),
 796         WIDGETS("ADMAIF17", t186_admaif17_tx),
 797         WIDGETS("ADMAIF18", t186_admaif18_tx),
 798         WIDGETS("ADMAIF19", t186_admaif19_tx),
 799         WIDGETS("ADMAIF20", t186_admaif20_tx),
 800         WIDGETS("I2S1", t186_i2s1_tx),
 801         WIDGETS("I2S2", t186_i2s2_tx),
 802         WIDGETS("I2S3", t186_i2s3_tx),
 803         WIDGETS("I2S4", t186_i2s4_tx),
 804         WIDGETS("I2S5", t186_i2s5_tx),
 805         WIDGETS("I2S6", t186_i2s6_tx),
 806         TX_WIDGETS("DMIC1"),
 807         TX_WIDGETS("DMIC2"),
 808         TX_WIDGETS("DMIC3"),
 809         TX_WIDGETS("DMIC4"),
 810         WIDGETS("DSPK1", t186_dspk1_tx),
 811         WIDGETS("DSPK2", t186_dspk2_tx),
 812         WIDGETS("SFC1", t186_sfc1_tx),
 813         WIDGETS("SFC2", t186_sfc2_tx),
 814         WIDGETS("SFC3", t186_sfc3_tx),
 815         WIDGETS("SFC4", t186_sfc4_tx),
 816         WIDGETS("MVC1", t186_mvc1_tx),
 817         WIDGETS("MVC2", t186_mvc2_tx),
 818         WIDGETS("AMX1 RX1", t186_amx11_tx),
 819         WIDGETS("AMX1 RX2", t186_amx12_tx),
 820         WIDGETS("AMX1 RX3", t186_amx13_tx),
 821         WIDGETS("AMX1 RX4", t186_amx14_tx),
 822         WIDGETS("AMX2 RX1", t186_amx21_tx),
 823         WIDGETS("AMX2 RX2", t186_amx22_tx),
 824         WIDGETS("AMX2 RX3", t186_amx23_tx),
 825         WIDGETS("AMX2 RX4", t186_amx24_tx),
 826         WIDGETS("AMX3 RX1", t186_amx31_tx),
 827         WIDGETS("AMX3 RX2", t186_amx32_tx),
 828         WIDGETS("AMX3 RX3", t186_amx33_tx),
 829         WIDGETS("AMX3 RX4", t186_amx34_tx),
 830         WIDGETS("AMX4 RX1", t186_amx41_tx),
 831         WIDGETS("AMX4 RX2", t186_amx42_tx),
 832         WIDGETS("AMX4 RX3", t186_amx43_tx),
 833         WIDGETS("AMX4 RX4", t186_amx44_tx),
 834         TX_WIDGETS("AMX1"),
 835         TX_WIDGETS("AMX2"),
 836         TX_WIDGETS("AMX3"),
 837         TX_WIDGETS("AMX4"),
 838         WIDGETS("ADX1", t186_adx1_tx),
 839         WIDGETS("ADX2", t186_adx2_tx),
 840         WIDGETS("ADX3", t186_adx3_tx),
 841         WIDGETS("ADX4", t186_adx4_tx),
 842         TX_WIDGETS("ADX1 TX1"),
 843         TX_WIDGETS("ADX1 TX2"),
 844         TX_WIDGETS("ADX1 TX3"),
 845         TX_WIDGETS("ADX1 TX4"),
 846         TX_WIDGETS("ADX2 TX1"),
 847         TX_WIDGETS("ADX2 TX2"),
 848         TX_WIDGETS("ADX2 TX3"),
 849         TX_WIDGETS("ADX2 TX4"),
 850         TX_WIDGETS("ADX3 TX1"),
 851         TX_WIDGETS("ADX3 TX2"),
 852         TX_WIDGETS("ADX3 TX3"),
 853         TX_WIDGETS("ADX3 TX4"),
 854         TX_WIDGETS("ADX4 TX1"),
 855         TX_WIDGETS("ADX4 TX2"),
 856         TX_WIDGETS("ADX4 TX3"),
 857         TX_WIDGETS("ADX4 TX4"),
 858         WIDGETS("MIXER1 RX1", t186_mixer11_tx),
 859         WIDGETS("MIXER1 RX2", t186_mixer12_tx),
 860         WIDGETS("MIXER1 RX3", t186_mixer13_tx),
 861         WIDGETS("MIXER1 RX4", t186_mixer14_tx),
 862         WIDGETS("MIXER1 RX5", t186_mixer15_tx),
 863         WIDGETS("MIXER1 RX6", t186_mixer16_tx),
 864         WIDGETS("MIXER1 RX7", t186_mixer17_tx),
 865         WIDGETS("MIXER1 RX8", t186_mixer18_tx),
 866         WIDGETS("MIXER1 RX9", t186_mixer19_tx),
 867         WIDGETS("MIXER1 RX10", t186_mixer110_tx),
 868         TX_WIDGETS("MIXER1 TX1"),
 869         TX_WIDGETS("MIXER1 TX2"),
 870         TX_WIDGETS("MIXER1 TX3"),
 871         TX_WIDGETS("MIXER1 TX4"),
 872         TX_WIDGETS("MIXER1 TX5"),
 873         WIDGETS("ASRC1 RX1", t186_asrc11_tx),
 874         WIDGETS("ASRC1 RX2", t186_asrc12_tx),
 875         WIDGETS("ASRC1 RX3", t186_asrc13_tx),
 876         WIDGETS("ASRC1 RX4", t186_asrc14_tx),
 877         WIDGETS("ASRC1 RX5", t186_asrc15_tx),
 878         WIDGETS("ASRC1 RX6", t186_asrc16_tx),
 879         WIDGETS("ASRC1 RX7", t186_asrc17_tx),
 880         TX_WIDGETS("ASRC1 TX1"),
 881         TX_WIDGETS("ASRC1 TX2"),
 882         TX_WIDGETS("ASRC1 TX3"),
 883         TX_WIDGETS("ASRC1 TX4"),
 884         TX_WIDGETS("ASRC1 TX5"),
 885         TX_WIDGETS("ASRC1 TX6"),
 886         WIDGETS("OPE1", t186_ope1_tx),
 887 };
 888
 889 static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
 890         WIDGETS("ADMAIF1", t186_admaif1_tx),
 891         WIDGETS("ADMAIF2", t186_admaif2_tx),
 892         WIDGETS("ADMAIF3", t186_admaif3_tx),
 893         WIDGETS("ADMAIF4", t186_admaif4_tx),
 894         WIDGETS("ADMAIF5", t186_admaif5_tx),
 895         WIDGETS("ADMAIF6", t186_admaif6_tx),
 896         WIDGETS("ADMAIF7", t186_admaif7_tx),
 897         WIDGETS("ADMAIF8", t186_admaif8_tx),
 898         WIDGETS("ADMAIF9", t186_admaif9_tx),
 899         WIDGETS("ADMAIF10", t186_admaif10_tx),
 900         WIDGETS("ADMAIF11", t186_admaif11_tx),
 901         WIDGETS("ADMAIF12", t186_admaif12_tx),
 902         WIDGETS("ADMAIF13", t186_admaif13_tx),
 903         WIDGETS("ADMAIF14", t186_admaif14_tx),
 904         WIDGETS("ADMAIF15", t186_admaif15_tx),
 905         WIDGETS("ADMAIF16", t186_admaif16_tx),
 906         WIDGETS("ADMAIF17", t234_admaif17_tx),
 907         WIDGETS("ADMAIF18", t234_admaif18_tx),
 908         WIDGETS("ADMAIF19", t234_admaif19_tx),
 909         WIDGETS("ADMAIF20", t234_admaif20_tx),
 910         WIDGETS("I2S1", t186_i2s1_tx),
 911         WIDGETS("I2S2", t186_i2s2_tx),
 912         WIDGETS("I2S3", t186_i2s3_tx),
 913         WIDGETS("I2S4", t186_i2s4_tx),
 914         WIDGETS("I2S5", t186_i2s5_tx),
 915         WIDGETS("I2S6", t186_i2s6_tx),
 916         TX_WIDGETS("DMIC1"),
 917         TX_WIDGETS("DMIC2"),
 918         TX_WIDGETS("DMIC3"),
 919         TX_WIDGETS("DMIC4"),
 920         WIDGETS("DSPK1", t186_dspk1_tx),
 921         WIDGETS("DSPK2", t186_dspk2_tx),
 922         WIDGETS("SFC1", t186_sfc1_tx),
 923         WIDGETS("SFC2", t186_sfc2_tx),
 924         WIDGETS("SFC3", t186_sfc3_tx),
 925         WIDGETS("SFC4", t186_sfc4_tx),
 926         WIDGETS("MVC1", t234_mvc1_tx),
 927         WIDGETS("MVC2", t234_mvc2_tx),
 928         WIDGETS("AMX1 RX1", t234_amx11_tx),
 929         WIDGETS("AMX1 RX2", t234_amx12_tx),
 930         WIDGETS("AMX1 RX3", t234_amx13_tx),
 931         WIDGETS("AMX1 RX4", t234_amx14_tx),
 932         WIDGETS("AMX2 RX1", t234_amx21_tx),
 933         WIDGETS("AMX2 RX2", t234_amx22_tx),
 934         WIDGETS("AMX2 RX3", t234_amx23_tx),
 935         WIDGETS("AMX2 RX4", t234_amx24_tx),
 936         WIDGETS("AMX3 RX1", t234_amx31_tx),
 937         WIDGETS("AMX3 RX2", t234_amx32_tx),
 938         WIDGETS("AMX3 RX3", t234_amx33_tx),
 939         WIDGETS("AMX3 RX4", t234_amx34_tx),
 940         WIDGETS("AMX4 RX1", t234_amx41_tx),
 941         WIDGETS("AMX4 RX2", t234_amx42_tx),
 942         WIDGETS("AMX4 RX3", t234_amx43_tx),
 943         WIDGETS("AMX4 RX4", t234_amx44_tx),
 944         TX_WIDGETS("AMX1"),
 945         TX_WIDGETS("AMX2"),
 946         TX_WIDGETS("AMX3"),
 947         TX_WIDGETS("AMX4"),
 948         WIDGETS("ADX1", t234_adx1_tx),
 949         WIDGETS("ADX2", t234_adx2_tx),
 950         WIDGETS("ADX3", t234_adx3_tx),
 951         WIDGETS("ADX4", t234_adx4_tx),
 952         TX_WIDGETS("ADX1 TX1"),
 953         TX_WIDGETS("ADX1 TX2"),
 954         TX_WIDGETS("ADX1 TX3"),
 955         TX_WIDGETS("ADX1 TX4"),
 956         TX_WIDGETS("ADX2 TX1"),
 957         TX_WIDGETS("ADX2 TX2"),
 958         TX_WIDGETS("ADX2 TX3"),
 959         TX_WIDGETS("ADX2 TX4"),
 960         TX_WIDGETS("ADX3 TX1"),
 961         TX_WIDGETS("ADX3 TX2"),
 962         TX_WIDGETS("ADX3 TX3"),
 963         TX_WIDGETS("ADX3 TX4"),
 964         TX_WIDGETS("ADX4 TX1"),
 965         TX_WIDGETS("ADX4 TX2"),
 966         TX_WIDGETS("ADX4 TX3"),
 967         TX_WIDGETS("ADX4 TX4"),
 968         WIDGETS("MIXER1 RX1", t186_mixer11_tx),
 969         WIDGETS("MIXER1 RX2", t186_mixer12_tx),
 970         WIDGETS("MIXER1 RX3", t186_mixer13_tx),
 971         WIDGETS("MIXER1 RX4", t186_mixer14_tx),
 972         WIDGETS("MIXER1 RX5", t186_mixer15_tx),
 973         WIDGETS("MIXER1 RX6", t186_mixer16_tx),
 974         WIDGETS("MIXER1 RX7", t186_mixer17_tx),
 975         WIDGETS("MIXER1 RX8", t186_mixer18_tx),
 976         WIDGETS("MIXER1 RX9", t186_mixer19_tx),
 977         WIDGETS("MIXER1 RX10", t186_mixer110_tx),
 978         TX_WIDGETS("MIXER1 TX1"),
 979         TX_WIDGETS("MIXER1 TX2"),
 980         TX_WIDGETS("MIXER1 TX3"),
 981         TX_WIDGETS("MIXER1 TX4"),
 982         TX_WIDGETS("MIXER1 TX5"),
 983         WIDGETS("ASRC1 RX1", t234_asrc11_tx),
 984         WIDGETS("ASRC1 RX2", t234_asrc12_tx),
 985         WIDGETS("ASRC1 RX3", t234_asrc13_tx),
 986         WIDGETS("ASRC1 RX4", t234_asrc14_tx),
 987         WIDGETS("ASRC1 RX5", t234_asrc15_tx),
 988         WIDGETS("ASRC1 RX6", t234_asrc16_tx),
 989         WIDGETS("ASRC1 RX7", t234_asrc17_tx),
 990         TX_WIDGETS("ASRC1 TX1"),
 991         TX_WIDGETS("ASRC1 TX2"),
 992         TX_WIDGETS("ASRC1 TX3"),
 993         TX_WIDGETS("ASRC1 TX4"),
 994         TX_WIDGETS("ASRC1 TX5"),
 995         TX_WIDGETS("ASRC1 TX6"),
 996         WIDGETS("OPE1", t186_ope1_tx),
 997 };
 998
 999 #define TEGRA_COMMON_MUX_ROUTES(name)                                   \
1000         { name " XBAR-TX",       NULL,          name " Mux" },          \
1001         { name " Mux",          "ADMAIF1",      "ADMAIF1 XBAR-RX" },    \
1002         { name " Mux",          "ADMAIF2",      "ADMAIF2 XBAR-RX" },    \
1003         { name " Mux",          "ADMAIF3",      "ADMAIF3 XBAR-RX" },    \
1004         { name " Mux",          "ADMAIF4",      "ADMAIF4 XBAR-RX" },    \
1005         { name " Mux",          "ADMAIF5",      "ADMAIF5 XBAR-RX" },    \
1006         { name " Mux",          "ADMAIF6",      "ADMAIF6 XBAR-RX" },    \
1007         { name " Mux",          "ADMAIF7",      "ADMAIF7 XBAR-RX" },    \
1008         { name " Mux",          "ADMAIF8",      "ADMAIF8 XBAR-RX" },    \
1009         { name " Mux",          "ADMAIF9",      "ADMAIF9 XBAR-RX" },    \
1010         { name " Mux",          "ADMAIF10",     "ADMAIF10 XBAR-RX" },   \
1011         { name " Mux",          "I2S1",         "I2S1 XBAR-RX" },       \
1012         { name " Mux",          "I2S2",         "I2S2 XBAR-RX" },       \
1013         { name " Mux",          "I2S3",         "I2S3 XBAR-RX" },       \
1014         { name " Mux",          "I2S4",         "I2S4 XBAR-RX" },       \
1015         { name " Mux",          "I2S5",         "I2S5 XBAR-RX" },       \
1016         { name " Mux",          "DMIC1",        "DMIC1 XBAR-RX" },      \
1017         { name " Mux",          "DMIC2",        "DMIC2 XBAR-RX" },      \
1018         { name " Mux",          "DMIC3",        "DMIC3 XBAR-RX" },      \
1019         { name " Mux",          "SFC1",         "SFC1 XBAR-RX" },       \
1020         { name " Mux",          "SFC2",         "SFC2 XBAR-RX" },       \
1021         { name " Mux",          "SFC3",         "SFC3 XBAR-RX" },       \
1022         { name " Mux",          "SFC4",         "SFC4 XBAR-RX" },       \
1023         { name " Mux",          "MVC1",         "MVC1 XBAR-RX" },       \
1024         { name " Mux",          "MVC2",         "MVC2 XBAR-RX" },       \
1025         { name " Mux",          "AMX1",         "AMX1 XBAR-RX" },       \
1026         { name " Mux",          "AMX2",         "AMX2 XBAR-RX" },       \
1027         { name " Mux",          "ADX1 TX1",     "ADX1 TX1 XBAR-RX" },   \
1028         { name " Mux",          "ADX1 TX2",     "ADX1 TX2 XBAR-RX" },   \
1029         { name " Mux",          "ADX1 TX3",     "ADX1 TX3 XBAR-RX" },   \
1030         { name " Mux",          "ADX1 TX4",     "ADX1 TX4 XBAR-RX" },   \
1031         { name " Mux",          "ADX2 TX1",     "ADX2 TX1 XBAR-RX" },   \
1032         { name " Mux",          "ADX2 TX2",     "ADX2 TX2 XBAR-RX" },   \
1033         { name " Mux",          "ADX2 TX3",     "ADX2 TX3 XBAR-RX" },   \
1034         { name " Mux",          "ADX2 TX4",     "ADX2 TX4 XBAR-RX" },   \
1035         { name " Mux",          "MIXER1 TX1",   "MIXER1 TX1 XBAR-RX" }, \
1036         { name " Mux",          "MIXER1 TX2",   "MIXER1 TX2 XBAR-RX" }, \
1037         { name " Mux",          "MIXER1 TX3",   "MIXER1 TX3 XBAR-RX" }, \
1038         { name " Mux",          "MIXER1 TX4",   "MIXER1 TX4 XBAR-RX" }, \
1039         { name " Mux",          "MIXER1 TX5",   "MIXER1 TX5 XBAR-RX" }, \
1040         { name " Mux",          "OPE1",         "OPE1 XBAR-RX" },
1041
1042 #define TEGRA210_ONLY_MUX_ROUTES(name)                                  \
1043         { name " Mux",          "OPE2",         "OPE2 XBAR-RX" },
1044
1045 #define TEGRA186_ONLY_MUX_ROUTES(name)                                  \
1046         { name " Mux",          "ADMAIF11",     "ADMAIF11 XBAR-RX" },   \
1047         { name " Mux",          "ADMAIF12",     "ADMAIF12 XBAR-RX" },   \
1048         { name " Mux",          "ADMAIF13",     "ADMAIF13 XBAR-RX" },   \
1049         { name " Mux",          "ADMAIF14",     "ADMAIF14 XBAR-RX" },   \
1050         { name " Mux",          "ADMAIF15",     "ADMAIF15 XBAR-RX" },   \
1051         { name " Mux",          "ADMAIF16",     "ADMAIF16 XBAR-RX" },   \
1052         { name " Mux",          "ADMAIF17",     "ADMAIF17 XBAR-RX" },   \
1053         { name " Mux",          "ADMAIF18",     "ADMAIF18 XBAR-RX" },   \
1054         { name " Mux",          "ADMAIF19",     "ADMAIF19 XBAR-RX" },   \
1055         { name " Mux",          "ADMAIF20",     "ADMAIF20 XBAR-RX" },   \
1056         { name " Mux",          "I2S6",         "I2S6 XBAR-RX" },       \
1057         { name " Mux",          "DMIC4",        "DMIC4 XBAR-RX" },      \
1058         { name " Mux",          "AMX3",         "AMX3 XBAR-RX" },       \
1059         { name " Mux",          "AMX4",         "AMX4 XBAR-RX" },       \
1060         { name " Mux",          "ADX3 TX1",     "ADX3 TX1 XBAR-RX" },   \
1061         { name " Mux",          "ADX3 TX2",     "ADX3 TX2 XBAR-RX" },   \
1062         { name " Mux",          "ADX3 TX3",     "ADX3 TX3 XBAR-RX" },   \
1063         { name " Mux",          "ADX3 TX4",     "ADX3 TX4 XBAR-RX" },   \
1064         { name " Mux",          "ADX4 TX1",     "ADX4 TX1 XBAR-RX" },   \
1065         { name " Mux",          "ADX4 TX2",     "ADX4 TX2 XBAR-RX" },   \
1066         { name " Mux",          "ADX4 TX3",     "ADX4 TX3 XBAR-RX" },   \
1067         { name " Mux",          "ADX4 TX4",     "ADX4 TX4 XBAR-RX" },   \
1068         { name " Mux",          "ASRC1 TX1",    "ASRC1 TX1 XBAR-RX" },  \
1069         { name " Mux",          "ASRC1 TX2",    "ASRC1 TX2 XBAR-RX" },  \
1070         { name " Mux",          "ASRC1 TX3",    "ASRC1 TX3 XBAR-RX" },  \
1071         { name " Mux",          "ASRC1 TX4",    "ASRC1 TX4 XBAR-RX" },  \
1072         { name " Mux",          "ASRC1 TX5",    "ASRC1 TX5 XBAR-RX" },  \
1073         { name " Mux",          "ASRC1 TX6",    "ASRC1 TX6 XBAR-RX" },
1074
1075 #define TEGRA210_MUX_ROUTES(name)                                       \
1076         TEGRA_COMMON_MUX_ROUTES(name)                                   \
1077         TEGRA210_ONLY_MUX_ROUTES(name)
1078
1079 #define TEGRA186_MUX_ROUTES(name)                                       \
1080         TEGRA_COMMON_MUX_ROUTES(name)                                   \
1081         TEGRA186_ONLY_MUX_ROUTES(name)
1082
1083 /* Connect FEs with XBAR */
1084 #define TEGRA_FE_ROUTES(name) \
1085         { name " XBAR-Playback",        NULL,   name " Playback" },     \
1086         { name " XBAR-RX",              NULL,   name " XBAR-Playback"}, \
1087         { name " XBAR-Capture",         NULL,   name " XBAR-TX" },      \
1088         { name " Capture",              NULL,   name " XBAR-Capture" },
1089
1090 static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
1091         TEGRA_FE_ROUTES("ADMAIF1")
1092         TEGRA_FE_ROUTES("ADMAIF2")
1093         TEGRA_FE_ROUTES("ADMAIF3")
1094         TEGRA_FE_ROUTES("ADMAIF4")
1095         TEGRA_FE_ROUTES("ADMAIF5")
1096         TEGRA_FE_ROUTES("ADMAIF6")
1097         TEGRA_FE_ROUTES("ADMAIF7")
1098         TEGRA_FE_ROUTES("ADMAIF8")
1099         TEGRA_FE_ROUTES("ADMAIF9")
1100         TEGRA_FE_ROUTES("ADMAIF10")
1101         TEGRA210_MUX_ROUTES("ADMAIF1")
1102         TEGRA210_MUX_ROUTES("ADMAIF2")
1103         TEGRA210_MUX_ROUTES("ADMAIF3")
1104         TEGRA210_MUX_ROUTES("ADMAIF4")
1105         TEGRA210_MUX_ROUTES("ADMAIF5")
1106         TEGRA210_MUX_ROUTES("ADMAIF6")
1107         TEGRA210_MUX_ROUTES("ADMAIF7")
1108         TEGRA210_MUX_ROUTES("ADMAIF8")
1109         TEGRA210_MUX_ROUTES("ADMAIF9")
1110         TEGRA210_MUX_ROUTES("ADMAIF10")
1111         TEGRA210_MUX_ROUTES("I2S1")
1112         TEGRA210_MUX_ROUTES("I2S2")
1113         TEGRA210_MUX_ROUTES("I2S3")
1114         TEGRA210_MUX_ROUTES("I2S4")
1115         TEGRA210_MUX_ROUTES("I2S5")
1116         TEGRA210_MUX_ROUTES("SFC1")
1117         TEGRA210_MUX_ROUTES("SFC2")
1118         TEGRA210_MUX_ROUTES("SFC3")
1119         TEGRA210_MUX_ROUTES("SFC4")
1120         TEGRA210_MUX_ROUTES("MVC1")
1121         TEGRA210_MUX_ROUTES("MVC2")
1122         TEGRA210_MUX_ROUTES("AMX1 RX1")
1123         TEGRA210_MUX_ROUTES("AMX1 RX2")
1124         TEGRA210_MUX_ROUTES("AMX1 RX3")
1125         TEGRA210_MUX_ROUTES("AMX1 RX4")
1126         TEGRA210_MUX_ROUTES("AMX2 RX1")
1127         TEGRA210_MUX_ROUTES("AMX2 RX2")
1128         TEGRA210_MUX_ROUTES("AMX2 RX3")
1129         TEGRA210_MUX_ROUTES("AMX2 RX4")
1130         TEGRA210_MUX_ROUTES("ADX1")
1131         TEGRA210_MUX_ROUTES("ADX2")
1132         TEGRA210_MUX_ROUTES("MIXER1 RX1")
1133         TEGRA210_MUX_ROUTES("MIXER1 RX2")
1134         TEGRA210_MUX_ROUTES("MIXER1 RX3")
1135         TEGRA210_MUX_ROUTES("MIXER1 RX4")
1136         TEGRA210_MUX_ROUTES("MIXER1 RX5")
1137         TEGRA210_MUX_ROUTES("MIXER1 RX6")
1138         TEGRA210_MUX_ROUTES("MIXER1 RX7")
1139         TEGRA210_MUX_ROUTES("MIXER1 RX8")
1140         TEGRA210_MUX_ROUTES("MIXER1 RX9")
1141         TEGRA210_MUX_ROUTES("MIXER1 RX10")
1142         TEGRA210_MUX_ROUTES("OPE1")
1143         TEGRA210_MUX_ROUTES("OPE2")
1144 };
1145
1146 static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
1147         TEGRA_FE_ROUTES("ADMAIF1")
1148         TEGRA_FE_ROUTES("ADMAIF2")
1149         TEGRA_FE_ROUTES("ADMAIF3")
1150         TEGRA_FE_ROUTES("ADMAIF4")
1151         TEGRA_FE_ROUTES("ADMAIF5")
1152         TEGRA_FE_ROUTES("ADMAIF6")
1153         TEGRA_FE_ROUTES("ADMAIF7")
1154         TEGRA_FE_ROUTES("ADMAIF8")
1155         TEGRA_FE_ROUTES("ADMAIF9")
1156         TEGRA_FE_ROUTES("ADMAIF10")
1157         TEGRA_FE_ROUTES("ADMAIF11")
1158         TEGRA_FE_ROUTES("ADMAIF12")
1159         TEGRA_FE_ROUTES("ADMAIF13")
1160         TEGRA_FE_ROUTES("ADMAIF14")
1161         TEGRA_FE_ROUTES("ADMAIF15")
1162         TEGRA_FE_ROUTES("ADMAIF16")
1163         TEGRA_FE_ROUTES("ADMAIF17")
1164         TEGRA_FE_ROUTES("ADMAIF18")
1165         TEGRA_FE_ROUTES("ADMAIF19")
1166         TEGRA_FE_ROUTES("ADMAIF20")
1167         TEGRA186_MUX_ROUTES("ADMAIF1")
1168         TEGRA186_MUX_ROUTES("ADMAIF2")
1169         TEGRA186_MUX_ROUTES("ADMAIF3")
1170         TEGRA186_MUX_ROUTES("ADMAIF4")
1171         TEGRA186_MUX_ROUTES("ADMAIF5")
1172         TEGRA186_MUX_ROUTES("ADMAIF6")
1173         TEGRA186_MUX_ROUTES("ADMAIF7")
1174         TEGRA186_MUX_ROUTES("ADMAIF8")
1175         TEGRA186_MUX_ROUTES("ADMAIF9")
1176         TEGRA186_MUX_ROUTES("ADMAIF10")
1177         TEGRA186_MUX_ROUTES("ADMAIF11")
1178         TEGRA186_MUX_ROUTES("ADMAIF12")
1179         TEGRA186_MUX_ROUTES("ADMAIF13")
1180         TEGRA186_MUX_ROUTES("ADMAIF14")
1181         TEGRA186_MUX_ROUTES("ADMAIF15")
1182         TEGRA186_MUX_ROUTES("ADMAIF16")
1183         TEGRA186_MUX_ROUTES("ADMAIF17")
1184         TEGRA186_MUX_ROUTES("ADMAIF18")
1185         TEGRA186_MUX_ROUTES("ADMAIF19")
1186         TEGRA186_MUX_ROUTES("ADMAIF20")
1187         TEGRA186_MUX_ROUTES("I2S1")
1188         TEGRA186_MUX_ROUTES("I2S2")
1189         TEGRA186_MUX_ROUTES("I2S3")
1190         TEGRA186_MUX_ROUTES("I2S4")
1191         TEGRA186_MUX_ROUTES("I2S5")
1192         TEGRA186_MUX_ROUTES("I2S6")
1193         TEGRA186_MUX_ROUTES("DSPK1")
1194         TEGRA186_MUX_ROUTES("DSPK2")
1195         TEGRA186_MUX_ROUTES("SFC1")
1196         TEGRA186_MUX_ROUTES("SFC2")
1197         TEGRA186_MUX_ROUTES("SFC3")
1198         TEGRA186_MUX_ROUTES("SFC4")
1199         TEGRA186_MUX_ROUTES("MVC1")
1200         TEGRA186_MUX_ROUTES("MVC2")
1201         TEGRA186_MUX_ROUTES("AMX1 RX1")
1202         TEGRA186_MUX_ROUTES("AMX1 RX2")
1203         TEGRA186_MUX_ROUTES("AMX1 RX3")
1204         TEGRA186_MUX_ROUTES("AMX1 RX4")
1205         TEGRA186_MUX_ROUTES("AMX2 RX1")
1206         TEGRA186_MUX_ROUTES("AMX2 RX2")
1207         TEGRA186_MUX_ROUTES("AMX2 RX3")
1208         TEGRA186_MUX_ROUTES("AMX2 RX4")
1209         TEGRA186_MUX_ROUTES("AMX3 RX1")
1210         TEGRA186_MUX_ROUTES("AMX3 RX2")
1211         TEGRA186_MUX_ROUTES("AMX3 RX3")
1212         TEGRA186_MUX_ROUTES("AMX3 RX4")
1213         TEGRA186_MUX_ROUTES("AMX4 RX1")
1214         TEGRA186_MUX_ROUTES("AMX4 RX2")
1215         TEGRA186_MUX_ROUTES("AMX4 RX3")
1216         TEGRA186_MUX_ROUTES("AMX4 RX4")
1217         TEGRA186_MUX_ROUTES("ADX1")
1218         TEGRA186_MUX_ROUTES("ADX2")
1219         TEGRA186_MUX_ROUTES("ADX3")
1220         TEGRA186_MUX_ROUTES("ADX4")
1221         TEGRA186_MUX_ROUTES("MIXER1 RX1")
1222         TEGRA186_MUX_ROUTES("MIXER1 RX2")
1223         TEGRA186_MUX_ROUTES("MIXER1 RX3")
1224         TEGRA186_MUX_ROUTES("MIXER1 RX4")
1225         TEGRA186_MUX_ROUTES("MIXER1 RX5")
1226         TEGRA186_MUX_ROUTES("MIXER1 RX6")
1227         TEGRA186_MUX_ROUTES("MIXER1 RX7")
1228         TEGRA186_MUX_ROUTES("MIXER1 RX8")
1229         TEGRA186_MUX_ROUTES("MIXER1 RX9")
1230         TEGRA186_MUX_ROUTES("MIXER1 RX10")
1231         TEGRA186_MUX_ROUTES("ASRC1 RX1")
1232         TEGRA186_MUX_ROUTES("ASRC1 RX2")
1233         TEGRA186_MUX_ROUTES("ASRC1 RX3")
1234         TEGRA186_MUX_ROUTES("ASRC1 RX4")
1235         TEGRA186_MUX_ROUTES("ASRC1 RX5")
1236         TEGRA186_MUX_ROUTES("ASRC1 RX6")
1237         TEGRA186_MUX_ROUTES("ASRC1 RX7")
1238         TEGRA186_MUX_ROUTES("OPE1")
1239 };
1240
1241 static const struct snd_soc_component_driver tegra210_ahub_component = {
1242         .dapm_widgets           = tegra210_ahub_widgets,
1243         .num_dapm_widgets       = ARRAY_SIZE(tegra210_ahub_widgets),
1244         .dapm_routes            = tegra210_ahub_routes,
1245         .num_dapm_routes        = ARRAY_SIZE(tegra210_ahub_routes),
1246 };
1247
1248 static const struct snd_soc_component_driver tegra186_ahub_component = {
1249         .dapm_widgets = tegra186_ahub_widgets,
1250         .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets),
1251         .dapm_routes = tegra186_ahub_routes,
1252         .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
1253 };
1254
1255 static const struct snd_soc_component_driver tegra234_ahub_component = {
1256         .dapm_widgets           = tegra234_ahub_widgets,
1257         .num_dapm_widgets       = ARRAY_SIZE(tegra234_ahub_widgets),
1258         .dapm_routes            = tegra186_ahub_routes,
1259         .num_dapm_routes        = ARRAY_SIZE(tegra186_ahub_routes),
1260 };
1261
1262 static const struct regmap_config tegra210_ahub_regmap_config = {
1263         .reg_bits               = 32,
1264         .val_bits               = 32,
1265         .reg_stride             = 4,
1266         .max_register           = TEGRA210_MAX_REGISTER_ADDR,
1267         .cache_type             = REGCACHE_FLAT,
1268 };
1269
1270 static const struct regmap_config tegra186_ahub_regmap_config = {
1271         .reg_bits               = 32,
1272         .val_bits               = 32,
1273         .reg_stride             = 4,
1274         .max_register           = TEGRA186_MAX_REGISTER_ADDR,
1275         .cache_type             = REGCACHE_FLAT,
1276 };
1277
1278 static const struct tegra_ahub_soc_data soc_data_tegra210 = {
1279         .cmpnt_drv      = &tegra210_ahub_component,
1280         .dai_drv        = tegra210_ahub_dais,
1281         .num_dais       = ARRAY_SIZE(tegra210_ahub_dais),
1282         .regmap_config  = &tegra210_ahub_regmap_config,
1283         .mask[0]        = TEGRA210_XBAR_REG_MASK_0,
1284         .mask[1]        = TEGRA210_XBAR_REG_MASK_1,
1285         .mask[2]        = TEGRA210_XBAR_REG_MASK_2,
1286         .mask[3]        = TEGRA210_XBAR_REG_MASK_3,
1287         .reg_count      = TEGRA210_XBAR_UPDATE_MAX_REG,
1288 };
1289
1290 static const struct tegra_ahub_soc_data soc_data_tegra186 = {
1291         .cmpnt_drv      = &tegra186_ahub_component,
1292         .dai_drv        = tegra186_ahub_dais,
1293         .num_dais       = ARRAY_SIZE(tegra186_ahub_dais),
1294         .regmap_config  = &tegra186_ahub_regmap_config,
1295         .mask[0]        = TEGRA186_XBAR_REG_MASK_0,
1296         .mask[1]        = TEGRA186_XBAR_REG_MASK_1,
1297         .mask[2]        = TEGRA186_XBAR_REG_MASK_2,
1298         .mask[3]        = TEGRA186_XBAR_REG_MASK_3,
1299         .reg_count      = TEGRA186_XBAR_UPDATE_MAX_REG,
1300 };
1301
1302 static const struct tegra_ahub_soc_data soc_data_tegra234 = {
1303         .cmpnt_drv      = &tegra234_ahub_component,
1304         .dai_drv        = tegra186_ahub_dais,
1305         .num_dais       = ARRAY_SIZE(tegra186_ahub_dais),
1306         .regmap_config  = &tegra186_ahub_regmap_config,
1307         .mask[0]        = TEGRA186_XBAR_REG_MASK_0,
1308         .mask[1]        = TEGRA186_XBAR_REG_MASK_1,
1309         .mask[2]        = TEGRA186_XBAR_REG_MASK_2,
1310         .mask[3]        = TEGRA186_XBAR_REG_MASK_3,
1311         .reg_count      = TEGRA186_XBAR_UPDATE_MAX_REG,
1312 };
1313
1314 static const struct of_device_id tegra_ahub_of_match[] = {
1315         { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
1316         { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
1317         { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 },
1318         {},
1319 };
1320 MODULE_DEVICE_TABLE(of, tegra_ahub_of_match);
1321
1322 static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev)
1323 {
1324         struct tegra_ahub *ahub = dev_get_drvdata(dev);
1325
1326         regcache_cache_only(ahub->regmap, true);
1327         regcache_mark_dirty(ahub->regmap);
1328
1329         clk_disable_unprepare(ahub->clk);
1330
1331         return 0;
1332 }
1333
1334 static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev)
1335 {
1336         struct tegra_ahub *ahub = dev_get_drvdata(dev);
1337         int err;
1338
1339         err = clk_prepare_enable(ahub->clk);
1340         if (err) {
1341                 dev_err(dev, "failed to enable AHUB clock, err: %d\n", err);
1342                 return err;
1343         }
1344
1345         regcache_cache_only(ahub->regmap, false);
1346         regcache_sync(ahub->regmap);
1347
1348         return 0;
1349 }
1350
1351 static int tegra_ahub_probe(struct platform_device *pdev)
1352 {
1353         struct tegra_ahub *ahub;
1354         void __iomem *regs;
1355         int err;
1356
1357         ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL);
1358         if (!ahub)
1359                 return -ENOMEM;
1360
1361         ahub->soc_data = of_device_get_match_data(&pdev->dev);
1362
1363         platform_set_drvdata(pdev, ahub);
1364
1365         ahub->clk = devm_clk_get(&pdev->dev, "ahub");
1366         if (IS_ERR(ahub->clk)) {
1367                 dev_err(&pdev->dev, "can't retrieve AHUB clock\n");
1368                 return PTR_ERR(ahub->clk);
1369         }
1370
1371         regs = devm_platform_ioremap_resource(pdev, 0);
1372         if (IS_ERR(regs))
1373                 return PTR_ERR(regs);
1374
1375         ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1376                                              ahub->soc_data->regmap_config);
1377         if (IS_ERR(ahub->regmap)) {
1378                 dev_err(&pdev->dev, "regmap init failed\n");
1379                 return PTR_ERR(ahub->regmap);
1380         }
1381
1382         regcache_cache_only(ahub->regmap, true);
1383
1384         err = devm_snd_soc_register_component(&pdev->dev,
1385                                               ahub->soc_data->cmpnt_drv,
1386                                               ahub->soc_data->dai_drv,
1387                                               ahub->soc_data->num_dais);
1388         if (err) {
1389                 dev_err(&pdev->dev, "can't register AHUB component, err: %d\n",
1390                         err);
1391                 return err;
1392         }
1393
1394         err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
1395         if (err)
1396                 return err;
1397
1398         pm_runtime_enable(&pdev->dev);
1399
1400         return 0;
1401 }
1402
1403 static void tegra_ahub_remove(struct platform_device *pdev)
1404 {
1405         pm_runtime_disable(&pdev->dev);
1406 }
1407
1408 static const struct dev_pm_ops tegra_ahub_pm_ops = {
1409         SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend,
1410                            tegra_ahub_runtime_resume, NULL)
1411         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1412                                 pm_runtime_force_resume)
1413 };
1414
1415 static struct platform_driver tegra_ahub_driver = {
1416         .probe = tegra_ahub_probe,
1417         .remove_new = tegra_ahub_remove,
1418         .driver = {
1419                 .name = "tegra210-ahub",
1420                 .of_match_table = tegra_ahub_of_match,
1421                 .pm = &tegra_ahub_pm_ops,
1422         },
1423 };
1424 module_platform_driver(tegra_ahub_driver);
1425
1426 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
1427 MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
1428 MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver");
1429 MODULE_LICENSE("GPL v2");