2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 * License terms: GPL V2.0.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/module.h>
23 #include <linux/of_platform.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
27 #include <sound/dmaengine_pcm.h>
28 #include <sound/pcm_params.h>
30 /* SPDIF-rx Register Map */
31 #define STM32_SPDIFRX_CR 0x00
32 #define STM32_SPDIFRX_IMR 0x04
33 #define STM32_SPDIFRX_SR 0x08
34 #define STM32_SPDIFRX_IFCR 0x0C
35 #define STM32_SPDIFRX_DR 0x10
36 #define STM32_SPDIFRX_CSR 0x14
37 #define STM32_SPDIFRX_DIR 0x18
39 /* Bit definition for SPDIF_CR register */
40 #define SPDIFRX_CR_SPDIFEN_SHIFT 0
41 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
42 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
44 #define SPDIFRX_CR_RXDMAEN BIT(2)
45 #define SPDIFRX_CR_RXSTEO BIT(3)
47 #define SPDIFRX_CR_DRFMT_SHIFT 4
48 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
49 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
51 #define SPDIFRX_CR_PMSK BIT(6)
52 #define SPDIFRX_CR_VMSK BIT(7)
53 #define SPDIFRX_CR_CUMSK BIT(8)
54 #define SPDIFRX_CR_PTMSK BIT(9)
55 #define SPDIFRX_CR_CBDMAEN BIT(10)
56 #define SPDIFRX_CR_CHSEL_SHIFT 11
57 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
59 #define SPDIFRX_CR_NBTR_SHIFT 12
60 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
61 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
63 #define SPDIFRX_CR_WFA BIT(14)
65 #define SPDIFRX_CR_INSEL_SHIFT 16
66 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
67 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
69 #define SPDIFRX_CR_CKSEN_SHIFT 20
70 #define SPDIFRX_CR_CKSEN BIT(20)
71 #define SPDIFRX_CR_CKSBKPEN BIT(21)
73 /* Bit definition for SPDIFRX_IMR register */
74 #define SPDIFRX_IMR_RXNEI BIT(0)
75 #define SPDIFRX_IMR_CSRNEIE BIT(1)
76 #define SPDIFRX_IMR_PERRIE BIT(2)
77 #define SPDIFRX_IMR_OVRIE BIT(3)
78 #define SPDIFRX_IMR_SBLKIE BIT(4)
79 #define SPDIFRX_IMR_SYNCDIE BIT(5)
80 #define SPDIFRX_IMR_IFEIE BIT(6)
82 #define SPDIFRX_XIMR_MASK GENMASK(6, 0)
84 /* Bit definition for SPDIFRX_SR register */
85 #define SPDIFRX_SR_RXNE BIT(0)
86 #define SPDIFRX_SR_CSRNE BIT(1)
87 #define SPDIFRX_SR_PERR BIT(2)
88 #define SPDIFRX_SR_OVR BIT(3)
89 #define SPDIFRX_SR_SBD BIT(4)
90 #define SPDIFRX_SR_SYNCD BIT(5)
91 #define SPDIFRX_SR_FERR BIT(6)
92 #define SPDIFRX_SR_SERR BIT(7)
93 #define SPDIFRX_SR_TERR BIT(8)
95 #define SPDIFRX_SR_WIDTH5_SHIFT 16
96 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
97 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
99 /* Bit definition for SPDIFRX_IFCR register */
100 #define SPDIFRX_IFCR_PERRCF BIT(2)
101 #define SPDIFRX_IFCR_OVRCF BIT(3)
102 #define SPDIFRX_IFCR_SBDCF BIT(4)
103 #define SPDIFRX_IFCR_SYNCDCF BIT(5)
105 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
107 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
108 #define SPDIFRX_DR0_DR_SHIFT 0
109 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
110 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
112 #define SPDIFRX_DR0_PE BIT(24)
114 #define SPDIFRX_DR0_V BIT(25)
115 #define SPDIFRX_DR0_U BIT(26)
116 #define SPDIFRX_DR0_C BIT(27)
118 #define SPDIFRX_DR0_PT_SHIFT 28
119 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
120 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
122 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
123 #define SPDIFRX_DR1_PE BIT(0)
124 #define SPDIFRX_DR1_V BIT(1)
125 #define SPDIFRX_DR1_U BIT(2)
126 #define SPDIFRX_DR1_C BIT(3)
128 #define SPDIFRX_DR1_PT_SHIFT 4
129 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
130 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
132 #define SPDIFRX_DR1_DR_SHIFT 8
133 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
134 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
136 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
137 #define SPDIFRX_DR1_DRNL1_SHIFT 0
138 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
139 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
141 #define SPDIFRX_DR1_DRNL2_SHIFT 16
142 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
143 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
145 /* Bit definition for SPDIFRX_CSR register */
146 #define SPDIFRX_CSR_USR_SHIFT 0
147 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
148 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
149 >> SPDIFRX_CSR_USR_SHIFT)
151 #define SPDIFRX_CSR_CS_SHIFT 16
152 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
153 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
154 >> SPDIFRX_CSR_CS_SHIFT)
156 #define SPDIFRX_CSR_SOB BIT(24)
158 /* Bit definition for SPDIFRX_DIR register */
159 #define SPDIFRX_DIR_THI_SHIFT 0
160 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
161 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
163 #define SPDIFRX_DIR_TLO_SHIFT 16
164 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
165 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
167 #define SPDIFRX_SPDIFEN_DISABLE 0x0
168 #define SPDIFRX_SPDIFEN_SYNC 0x1
169 #define SPDIFRX_SPDIFEN_ENABLE 0x3
171 #define SPDIFRX_IN1 0x1
172 #define SPDIFRX_IN2 0x2
173 #define SPDIFRX_IN3 0x3
174 #define SPDIFRX_IN4 0x4
175 #define SPDIFRX_IN5 0x5
176 #define SPDIFRX_IN6 0x6
177 #define SPDIFRX_IN7 0x7
178 #define SPDIFRX_IN8 0x8
180 #define SPDIFRX_NBTR_NONE 0x0
181 #define SPDIFRX_NBTR_3 0x1
182 #define SPDIFRX_NBTR_15 0x2
183 #define SPDIFRX_NBTR_63 0x3
185 #define SPDIFRX_DRFMT_RIGHT 0x0
186 #define SPDIFRX_DRFMT_LEFT 0x1
187 #define SPDIFRX_DRFMT_PACKED 0x2
189 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
190 #define SPDIFRX_CS_BYTES_NB 24
191 #define SPDIFRX_UB_BYTES_NB 48
194 * CSR register is retrieved as a 32 bits word
195 * It contains 1 channel status byte and 2 user data bytes
196 * 2 S/PDIF frames are acquired to get all CS/UB bits
198 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
201 * struct stm32_spdifrx_data - private data of SPDIFRX
202 * @pdev: device data pointer
203 * @base: mmio register base virtual address
204 * @regmap: SPDIFRX register map pointer
205 * @regmap_conf: SPDIFRX register map configuration pointer
206 * @cs_completion: channel status retrieving completion
207 * @kclk: kernel clock feeding the SPDIFRX clock generator
208 * @dma_params: dma configuration data for rx channel
209 * @substream: PCM substream data pointer
210 * @dmab: dma buffer info pointer
211 * @ctrl_chan: dma channel for S/PDIF control bits
212 * @desc:dma async transaction descriptor
213 * @slave_config: dma slave channel runtime config pointer
214 * @phys_addr: SPDIFRX registers physical base address
215 * @lock: synchronization enabling lock
216 * @irq_lock: prevent race condition with IRQ on stream state
217 * @cs: channel status buffer
218 * @ub: user data buffer
219 * @irq: SPDIFRX interrupt line
220 * @refcount: keep count of opened DMA channels
222 struct stm32_spdifrx_data {
223 struct platform_device *pdev;
225 struct regmap *regmap;
226 const struct regmap_config *regmap_conf;
227 struct completion cs_completion;
229 struct snd_dmaengine_dai_dma_data dma_params;
230 struct snd_pcm_substream *substream;
231 struct snd_dma_buffer *dmab;
232 struct dma_chan *ctrl_chan;
233 struct dma_async_tx_descriptor *desc;
234 struct dma_slave_config slave_config;
235 dma_addr_t phys_addr;
236 spinlock_t lock; /* Sync enabling lock */
237 spinlock_t irq_lock; /* Prevent race condition on stream state */
238 unsigned char cs[SPDIFRX_CS_BYTES_NB];
239 unsigned char ub[SPDIFRX_UB_BYTES_NB];
244 static void stm32_spdifrx_dma_complete(void *data)
246 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
247 struct platform_device *pdev = spdifrx->pdev;
248 u32 *p_start = (u32 *)spdifrx->dmab->area;
249 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
251 u16 *ub_ptr = (short *)spdifrx->ub;
254 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
256 (unsigned int)~SPDIFRX_CR_CBDMAEN);
258 if (!spdifrx->dmab->area)
261 while (ptr <= p_end) {
262 if (*ptr & SPDIFRX_CSR_SOB)
268 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
272 while (i < SPDIFRX_CS_BYTES_NB) {
273 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
274 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
276 dev_err(&pdev->dev, "Failed to get channel status\n");
282 complete(&spdifrx->cs_completion);
285 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
290 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
292 SPDIFRX_CSR_BUF_LENGTH,
298 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
299 spdifrx->desc->callback_param = spdifrx;
300 cookie = dmaengine_submit(spdifrx->desc);
301 err = dma_submit_error(cookie);
305 dma_async_issue_pending(spdifrx->ctrl_chan);
310 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
312 dmaengine_terminate_async(spdifrx->ctrl_chan);
315 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
317 int cr, cr_mask, imr, ret;
321 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
322 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
326 spin_lock_irqsave(&spdifrx->lock, flags);
330 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
332 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
334 * Start sync if SPDIFRX is still in idle state.
335 * SPDIFRX reception enabled when sync done
337 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
340 * SPDIFRX configuration:
341 * Wait for activity before starting sync process. This avoid
342 * to issue sync errors when spdif signal is missing on input.
343 * Preamble, CS, user, validity and parity error bits not copied
346 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
347 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
350 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
351 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
352 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
355 dev_err(&spdifrx->pdev->dev,
356 "Failed to start synchronization\n");
359 spin_unlock_irqrestore(&spdifrx->lock, flags);
364 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
366 int cr, cr_mask, reg;
369 spin_lock_irqsave(&spdifrx->lock, flags);
371 if (--spdifrx->refcount) {
372 spin_unlock_irqrestore(&spdifrx->lock, flags);
376 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
377 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
379 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
381 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
382 SPDIFRX_XIMR_MASK, 0);
384 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
385 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
387 /* dummy read to clear CSRNE and RXNE in status register */
388 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
389 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
391 spin_unlock_irqrestore(&spdifrx->lock, flags);
394 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
395 struct stm32_spdifrx_data *spdifrx)
399 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
400 if (IS_ERR(spdifrx->ctrl_chan)) {
401 dev_err(dev, "dma_request_slave_channel failed\n");
402 return PTR_ERR(spdifrx->ctrl_chan);
405 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
410 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
411 spdifrx->dmab->dev.dev = dev;
412 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
413 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
415 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
419 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
420 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
422 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
423 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
424 spdifrx->slave_config.src_maxburst = 1;
426 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
427 &spdifrx->slave_config);
429 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
430 spdifrx->ctrl_chan = NULL;
436 static const char * const spdifrx_enum_input[] = {
437 "in0", "in1", "in2", "in3"
440 /* By default CS bits are retrieved from channel A */
441 static const char * const spdifrx_enum_cs_channel[] = {
445 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
446 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
449 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
450 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
451 spdifrx_enum_cs_channel);
453 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
454 struct snd_ctl_elem_info *uinfo)
456 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
462 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_info *uinfo)
465 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
471 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
475 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
476 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
478 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
482 ret = clk_prepare_enable(spdifrx->kclk);
484 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
488 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
489 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
493 ret = stm32_spdifrx_start_sync(spdifrx);
497 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
498 msecs_to_jiffies(100))
500 dev_err(&spdifrx->pdev->dev, "Failed to get control data\n");
504 stm32_spdifrx_stop(spdifrx);
505 stm32_spdifrx_dma_ctrl_stop(spdifrx);
508 clk_disable_unprepare(spdifrx->kclk);
513 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
514 struct snd_ctl_elem_value *ucontrol)
516 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
517 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
519 stm32_spdifrx_get_ctrl_data(spdifrx);
521 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
522 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
523 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
524 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
525 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
530 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_value *ucontrol)
533 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
534 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
536 stm32_spdifrx_get_ctrl_data(spdifrx);
538 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
539 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
540 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
541 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
542 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
547 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
548 /* Channel status control */
550 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
551 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
552 .access = SNDRV_CTL_ELEM_ACCESS_READ |
553 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
554 .info = stm32_spdifrx_info,
555 .get = stm32_spdifrx_capture_get,
557 /* User bits control */
559 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
560 .name = "IEC958 User Bit Capture Default",
561 .access = SNDRV_CTL_ELEM_ACCESS_READ |
562 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
563 .info = stm32_spdifrx_ub_info,
564 .get = stm32_spdif_user_bits_get,
568 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
569 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
570 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
573 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
577 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
578 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
582 return snd_soc_add_component_controls(cpu_dai->component,
584 ARRAY_SIZE(stm32_spdifrx_ctrls));
587 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
589 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
591 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
593 spdifrx->dma_params.maxburst = 1;
595 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
597 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
600 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
603 case STM32_SPDIFRX_CR:
604 case STM32_SPDIFRX_IMR:
605 case STM32_SPDIFRX_SR:
606 case STM32_SPDIFRX_IFCR:
607 case STM32_SPDIFRX_DR:
608 case STM32_SPDIFRX_CSR:
609 case STM32_SPDIFRX_DIR:
616 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
618 if (reg == STM32_SPDIFRX_DR)
624 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
627 case STM32_SPDIFRX_CR:
628 case STM32_SPDIFRX_IMR:
629 case STM32_SPDIFRX_IFCR:
636 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
640 .max_register = STM32_SPDIFRX_DIR,
641 .readable_reg = stm32_spdifrx_readable_reg,
642 .volatile_reg = stm32_spdifrx_volatile_reg,
643 .writeable_reg = stm32_spdifrx_writeable_reg,
647 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
649 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
650 struct platform_device *pdev = spdifrx->pdev;
651 unsigned int cr, mask, sr, imr;
653 int err = 0, err_xrun = 0;
655 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
656 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
658 mask = imr & SPDIFRX_XIMR_MASK;
659 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
660 if (mask & SPDIFRX_IMR_IFEIE)
661 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
665 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
671 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
672 SPDIFRX_XIFCR_MASK, flags);
674 if (flags & SPDIFRX_SR_PERR) {
675 dev_dbg(&pdev->dev, "Parity error\n");
679 if (flags & SPDIFRX_SR_OVR) {
680 dev_dbg(&pdev->dev, "Overrun error\n");
684 if (flags & SPDIFRX_SR_SBD)
685 dev_dbg(&pdev->dev, "Synchronization block detected\n");
687 if (flags & SPDIFRX_SR_SYNCD) {
688 dev_dbg(&pdev->dev, "Synchronization done\n");
691 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
692 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
693 SPDIFRX_CR_SPDIFEN_MASK, cr);
696 if (flags & SPDIFRX_SR_FERR) {
697 dev_dbg(&pdev->dev, "Frame error\n");
701 if (flags & SPDIFRX_SR_SERR) {
702 dev_dbg(&pdev->dev, "Synchronization error\n");
706 if (flags & SPDIFRX_SR_TERR) {
707 dev_dbg(&pdev->dev, "Timeout error\n");
712 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */
713 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
714 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
715 SPDIFRX_CR_SPDIFEN_MASK, cr);
717 spin_lock(&spdifrx->irq_lock);
718 if (spdifrx->substream)
719 snd_pcm_stop(spdifrx->substream,
720 SNDRV_PCM_STATE_DISCONNECTED);
721 spin_unlock(&spdifrx->irq_lock);
726 spin_lock(&spdifrx->irq_lock);
727 if (err_xrun && spdifrx->substream)
728 snd_pcm_stop_xrun(spdifrx->substream);
729 spin_unlock(&spdifrx->irq_lock);
734 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
735 struct snd_soc_dai *cpu_dai)
737 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
741 spin_lock_irqsave(&spdifrx->irq_lock, flags);
742 spdifrx->substream = substream;
743 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
745 ret = clk_prepare_enable(spdifrx->kclk);
747 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
752 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
753 struct snd_pcm_hw_params *params,
754 struct snd_soc_dai *cpu_dai)
756 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
757 int data_size = params_width(params);
762 fmt = SPDIFRX_DRFMT_PACKED;
765 fmt = SPDIFRX_DRFMT_LEFT;
768 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
773 * Set buswidth to 4 bytes for all data formats.
774 * Packed format: transfer 2 x 2 bytes samples
775 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
777 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
778 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
780 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
781 SPDIFRX_CR_DRFMT_MASK,
782 SPDIFRX_CR_DRFMTSET(fmt));
785 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
786 struct snd_soc_dai *cpu_dai)
788 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
792 case SNDRV_PCM_TRIGGER_START:
793 case SNDRV_PCM_TRIGGER_RESUME:
794 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
795 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
796 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
798 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
799 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
801 ret = stm32_spdifrx_start_sync(spdifrx);
803 case SNDRV_PCM_TRIGGER_SUSPEND:
804 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
805 case SNDRV_PCM_TRIGGER_STOP:
806 stm32_spdifrx_stop(spdifrx);
815 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
816 struct snd_soc_dai *cpu_dai)
818 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
821 spin_lock_irqsave(&spdifrx->irq_lock, flags);
822 spdifrx->substream = NULL;
823 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
825 clk_disable_unprepare(spdifrx->kclk);
828 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
829 .startup = stm32_spdifrx_startup,
830 .hw_params = stm32_spdifrx_hw_params,
831 .trigger = stm32_spdifrx_trigger,
832 .shutdown = stm32_spdifrx_shutdown,
835 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
837 .probe = stm32_spdifrx_dai_probe,
839 .stream_name = "CPU-Capture",
842 .rates = SNDRV_PCM_RATE_8000_192000,
843 .formats = SNDRV_PCM_FMTBIT_S32_LE |
844 SNDRV_PCM_FMTBIT_S16_LE,
846 .ops = &stm32_spdifrx_pcm_dai_ops,
850 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
851 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
852 .buffer_bytes_max = 8 * PAGE_SIZE,
853 .period_bytes_max = 2048, /* MDMA constraint */
858 static const struct snd_soc_component_driver stm32_spdifrx_component = {
859 .name = "stm32-spdifrx",
862 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
863 .pcm_hardware = &stm32_spdifrx_pcm_hw,
864 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
867 static const struct of_device_id stm32_spdifrx_ids[] = {
869 .compatible = "st,stm32h7-spdifrx",
870 .data = &stm32_h7_spdifrx_regmap_conf
875 static int stm32_spdifrx_parse_of(struct platform_device *pdev,
876 struct stm32_spdifrx_data *spdifrx)
878 struct device_node *np = pdev->dev.of_node;
879 const struct of_device_id *of_id;
880 struct resource *res;
885 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
887 spdifrx->regmap_conf =
888 (const struct regmap_config *)of_id->data;
892 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
893 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
894 if (IS_ERR(spdifrx->base))
895 return PTR_ERR(spdifrx->base);
897 spdifrx->phys_addr = res->start;
899 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
900 if (IS_ERR(spdifrx->kclk)) {
901 dev_err(&pdev->dev, "Could not get kclk\n");
902 return PTR_ERR(spdifrx->kclk);
905 spdifrx->irq = platform_get_irq(pdev, 0);
906 if (spdifrx->irq < 0) {
907 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name);
914 static int stm32_spdifrx_probe(struct platform_device *pdev)
916 struct stm32_spdifrx_data *spdifrx;
917 struct reset_control *rst;
918 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
921 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
925 spdifrx->pdev = pdev;
926 init_completion(&spdifrx->cs_completion);
927 spin_lock_init(&spdifrx->lock);
928 spin_lock_init(&spdifrx->irq_lock);
930 platform_set_drvdata(pdev, spdifrx);
932 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
936 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
938 spdifrx->regmap_conf);
939 if (IS_ERR(spdifrx->regmap)) {
940 dev_err(&pdev->dev, "Regmap init failed\n");
941 return PTR_ERR(spdifrx->regmap);
944 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
945 dev_name(&pdev->dev), spdifrx);
947 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
951 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
953 reset_control_assert(rst);
955 reset_control_deassert(rst);
958 ret = devm_snd_soc_register_component(&pdev->dev,
959 &stm32_spdifrx_component,
961 ARRAY_SIZE(stm32_spdifrx_dai));
965 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
969 pcm_config = &stm32_spdifrx_pcm_config;
970 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
972 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
979 if (!IS_ERR(spdifrx->ctrl_chan))
980 dma_release_channel(spdifrx->ctrl_chan);
982 snd_dma_free_pages(spdifrx->dmab);
987 static int stm32_spdifrx_remove(struct platform_device *pdev)
989 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
991 if (spdifrx->ctrl_chan)
992 dma_release_channel(spdifrx->ctrl_chan);
995 snd_dma_free_pages(spdifrx->dmab);
1000 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
1002 static struct platform_driver stm32_spdifrx_driver = {
1004 .name = "st,stm32-spdifrx",
1005 .of_match_table = stm32_spdifrx_ids,
1007 .probe = stm32_spdifrx_probe,
1008 .remove = stm32_spdifrx_remove,
1011 module_platform_driver(stm32_spdifrx_driver);
1013 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1014 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1015 MODULE_ALIAS("platform:stm32-spdifrx");
1016 MODULE_LICENSE("GPL v2");