2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 * License terms: GPL V2.0.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
19 #include <linux/clk.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/regmap.h>
26 #include <sound/asoundef.h>
27 #include <sound/core.h>
28 #include <sound/dmaengine_pcm.h>
29 #include <sound/pcm_params.h>
31 #include "stm32_sai.h"
33 #define SAI_FREE_PROTOCOL 0x0
34 #define SAI_SPDIF_PROTOCOL 0x1
36 #define SAI_SLOT_SIZE_AUTO 0x0
37 #define SAI_SLOT_SIZE_16 0x1
38 #define SAI_SLOT_SIZE_32 0x2
40 #define SAI_DATASIZE_8 0x2
41 #define SAI_DATASIZE_10 0x3
42 #define SAI_DATASIZE_16 0x4
43 #define SAI_DATASIZE_20 0x5
44 #define SAI_DATASIZE_24 0x6
45 #define SAI_DATASIZE_32 0x7
47 #define STM_SAI_FIFO_SIZE 8
48 #define STM_SAI_DAI_NAME_SIZE 15
50 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
51 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
53 #define STM_SAI_A_ID 0x0
54 #define STM_SAI_B_ID 0x1
56 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
57 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
58 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
60 #define SAI_SYNC_NONE 0x0
61 #define SAI_SYNC_INTERNAL 0x1
62 #define SAI_SYNC_EXTERNAL 0x2
64 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
65 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif)
66 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
68 #define SAI_IEC60958_BLOCK_FRAMES 192
69 #define SAI_IEC60958_STATUS_BYTES 24
72 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
73 * @pdev: device data pointer
74 * @regmap: SAI register map pointer
75 * @regmap_config: SAI sub block register map configuration pointer
76 * @dma_params: dma configuration data for rx or tx channel
77 * @cpu_dai_drv: DAI driver data pointer
78 * @cpu_dai: DAI runtime data pointer
79 * @substream: PCM substream data pointer
80 * @pdata: SAI block parent data pointer
81 * @np_sync_provider: synchronization provider node
82 * @sai_ck: kernel clock feeding the SAI clock generator
83 * @phys_addr: SAI registers physical base address
84 * @mclk_rate: SAI block master clock frequency (Hz). set at init
85 * @id: SAI sub block id corresponding to sub-block A or B
86 * @dir: SAI block direction (playback or capture). set at init
87 * @master: SAI block mode flag. (true=master, false=slave) set at init
88 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
89 * @fmt: SAI block format. relevant only for custom protocols. set at init
90 * @sync: SAI block synchronization mode. (none, internal or external)
91 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
92 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
93 * @fs_length: frame synchronization length. depends on protocol settings
94 * @slots: rx or tx slot number
95 * @slot_width: rx or tx slot width in bits
96 * @slot_mask: rx or tx active slots mask. set at init or at runtime
97 * @data_size: PCM data width. corresponds to PCM substream width.
98 * @spdif_frm_cnt: S/PDIF playback frame counter
99 * @iec958: iec958 data
100 * @ctrl_lock: control lock
102 struct stm32_sai_sub_data {
103 struct platform_device *pdev;
104 struct regmap *regmap;
105 const struct regmap_config *regmap_config;
106 struct snd_dmaengine_dai_dma_data dma_params;
107 struct snd_soc_dai_driver *cpu_dai_drv;
108 struct snd_soc_dai *cpu_dai;
109 struct snd_pcm_substream *substream;
110 struct stm32_sai_data *pdata;
111 struct device_node *np_sync_provider;
113 dma_addr_t phys_addr;
114 unsigned int mclk_rate;
128 unsigned int spdif_frm_cnt;
129 struct snd_aes_iec958 iec958;
130 struct mutex ctrl_lock; /* protect resources accessed by controls */
133 enum stm32_sai_fifo_th {
134 STM_SAI_FIFO_TH_EMPTY,
135 STM_SAI_FIFO_TH_QUARTER,
136 STM_SAI_FIFO_TH_HALF,
137 STM_SAI_FIFO_TH_3_QUARTER,
138 STM_SAI_FIFO_TH_FULL,
141 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
144 case STM_SAI_CR1_REGX:
145 case STM_SAI_CR2_REGX:
146 case STM_SAI_FRCR_REGX:
147 case STM_SAI_SLOTR_REGX:
148 case STM_SAI_IMR_REGX:
149 case STM_SAI_SR_REGX:
150 case STM_SAI_CLRFR_REGX:
151 case STM_SAI_DR_REGX:
152 case STM_SAI_PDMCR_REGX:
153 case STM_SAI_PDMLY_REGX:
160 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
163 case STM_SAI_DR_REGX:
170 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
173 case STM_SAI_CR1_REGX:
174 case STM_SAI_CR2_REGX:
175 case STM_SAI_FRCR_REGX:
176 case STM_SAI_SLOTR_REGX:
177 case STM_SAI_IMR_REGX:
178 case STM_SAI_SR_REGX:
179 case STM_SAI_CLRFR_REGX:
180 case STM_SAI_DR_REGX:
181 case STM_SAI_PDMCR_REGX:
182 case STM_SAI_PDMLY_REGX:
189 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
193 .max_register = STM_SAI_DR_REGX,
194 .readable_reg = stm32_sai_sub_readable_reg,
195 .volatile_reg = stm32_sai_sub_volatile_reg,
196 .writeable_reg = stm32_sai_sub_writeable_reg,
200 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
204 .max_register = STM_SAI_PDMLY_REGX,
205 .readable_reg = stm32_sai_sub_readable_reg,
206 .volatile_reg = stm32_sai_sub_volatile_reg,
207 .writeable_reg = stm32_sai_sub_writeable_reg,
211 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
212 struct snd_ctl_elem_info *uinfo)
214 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
220 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *uctl)
223 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
225 mutex_lock(&sai->ctrl_lock);
226 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
227 mutex_unlock(&sai->ctrl_lock);
232 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *uctl)
235 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
237 mutex_lock(&sai->ctrl_lock);
238 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
239 mutex_unlock(&sai->ctrl_lock);
244 static const struct snd_kcontrol_new iec958_ctls = {
245 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
246 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
247 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
248 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
249 .info = snd_pcm_iec958_info,
250 .get = snd_pcm_iec958_get,
251 .put = snd_pcm_iec958_put,
254 static irqreturn_t stm32_sai_isr(int irq, void *devid)
256 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
257 struct platform_device *pdev = sai->pdev;
258 unsigned int sr, imr, flags;
259 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
261 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
262 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
268 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
271 if (!sai->substream) {
272 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
276 if (flags & SAI_XIMR_OVRUDRIE) {
277 dev_err(&pdev->dev, "IRQ %s\n",
278 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
279 status = SNDRV_PCM_STATE_XRUN;
282 if (flags & SAI_XIMR_MUTEDETIE)
283 dev_dbg(&pdev->dev, "IRQ mute detected\n");
285 if (flags & SAI_XIMR_WCKCFGIE) {
286 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
287 status = SNDRV_PCM_STATE_DISCONNECTED;
290 if (flags & SAI_XIMR_CNRDYIE)
291 dev_err(&pdev->dev, "IRQ Codec not ready\n");
293 if (flags & SAI_XIMR_AFSDETIE) {
294 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
295 status = SNDRV_PCM_STATE_XRUN;
298 if (flags & SAI_XIMR_LFSDETIE) {
299 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
300 status = SNDRV_PCM_STATE_XRUN;
303 if (status != SNDRV_PCM_STATE_RUNNING)
304 snd_pcm_stop_xrun(sai->substream);
309 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
310 int clk_id, unsigned int freq, int dir)
312 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
315 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) {
316 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
318 (unsigned int)~SAI_XCR1_NODIV);
322 sai->mclk_rate = freq;
323 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
329 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
330 u32 rx_mask, int slots, int slot_width)
332 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
333 int slotr, slotr_mask, slot_size;
335 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
336 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
340 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
341 tx_mask, rx_mask, slots, slot_width);
343 switch (slot_width) {
345 slot_size = SAI_SLOT_SIZE_16;
348 slot_size = SAI_SLOT_SIZE_32;
351 slot_size = SAI_SLOT_SIZE_AUTO;
355 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
356 SAI_XSLOTR_NBSLOT_SET(slots - 1);
357 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
359 /* tx/rx mask set in machine init, if slot number defined in DT */
360 if (STM_SAI_IS_PLAYBACK(sai)) {
361 sai->slot_mask = tx_mask;
362 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
365 if (STM_SAI_IS_CAPTURE(sai)) {
366 sai->slot_mask = rx_mask;
367 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
370 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
372 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
374 sai->slot_width = slot_width;
380 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
382 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
384 int cr1_mask, frcr_mask = 0;
387 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
389 /* Do not generate master by default */
390 cr1 = SAI_XCR1_NODIV;
391 cr1_mask = SAI_XCR1_NODIV;
393 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
394 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
395 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
399 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
401 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
402 /* SCK active high for all protocols */
403 case SND_SOC_DAIFMT_I2S:
404 cr1 |= SAI_XCR1_CKSTR;
405 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
408 case SND_SOC_DAIFMT_MSB:
409 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
411 /* Right justified */
412 case SND_SOC_DAIFMT_LSB:
413 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
415 case SND_SOC_DAIFMT_DSP_A:
416 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
418 case SND_SOC_DAIFMT_DSP_B:
419 frcr |= SAI_XFRCR_FSPOL;
422 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
423 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
427 cr1_mask |= SAI_XCR1_CKSTR;
428 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
431 /* DAI clock strobing. Invert setting previously set */
432 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
433 case SND_SOC_DAIFMT_NB_NF:
435 case SND_SOC_DAIFMT_IB_NF:
436 cr1 ^= SAI_XCR1_CKSTR;
438 case SND_SOC_DAIFMT_NB_IF:
439 frcr ^= SAI_XFRCR_FSPOL;
441 case SND_SOC_DAIFMT_IB_IF:
442 /* Invert fs & sck */
443 cr1 ^= SAI_XCR1_CKSTR;
444 frcr ^= SAI_XFRCR_FSPOL;
447 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
448 fmt & SND_SOC_DAIFMT_INV_MASK);
451 cr1_mask |= SAI_XCR1_CKSTR;
452 frcr_mask |= SAI_XFRCR_FSPOL;
454 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
456 /* DAI clock master masks */
457 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
458 case SND_SOC_DAIFMT_CBM_CFM:
459 /* codec is master */
460 cr1 |= SAI_XCR1_SLAVE;
463 case SND_SOC_DAIFMT_CBS_CFS:
467 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
468 fmt & SND_SOC_DAIFMT_MASTER_MASK);
472 /* Set slave mode if sub-block is synchronized with another SAI */
474 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
475 cr1 |= SAI_XCR1_SLAVE;
479 cr1_mask |= SAI_XCR1_SLAVE;
482 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
484 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
493 static int stm32_sai_startup(struct snd_pcm_substream *substream,
494 struct snd_soc_dai *cpu_dai)
496 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
499 sai->substream = substream;
501 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
502 snd_pcm_hw_constraint_mask64(substream->runtime,
503 SNDRV_PCM_HW_PARAM_FORMAT,
504 SNDRV_PCM_FMTBIT_S32_LE);
505 snd_pcm_hw_constraint_single(substream->runtime,
506 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
509 ret = clk_prepare_enable(sai->sai_ck);
511 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
517 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
518 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
520 imr = SAI_XIMR_OVRUDRIE;
521 if (STM_SAI_IS_CAPTURE(sai)) {
522 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
523 if (cr2 & SAI_XCR2_MUTECNT_MASK)
524 imr |= SAI_XIMR_MUTEDETIE;
528 imr |= SAI_XIMR_WCKCFGIE;
530 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
532 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
538 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
539 struct snd_pcm_substream *substream,
540 struct snd_pcm_hw_params *params)
542 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
543 int cr1, cr1_mask, ret;
546 * DMA bursts increment is set to 4 words.
547 * SAI fifo threshold is set to half fifo, to keep enough space
548 * for DMA incoming bursts.
550 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX,
551 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
553 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
555 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
556 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
557 sai->spdif_frm_cnt = 0;
561 /* Mode, data format and channel config */
562 cr1_mask = SAI_XCR1_DS_MASK;
563 switch (params_format(params)) {
564 case SNDRV_PCM_FORMAT_S8:
565 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
567 case SNDRV_PCM_FORMAT_S16_LE:
568 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
570 case SNDRV_PCM_FORMAT_S32_LE:
571 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
574 dev_err(cpu_dai->dev, "Data format not supported");
578 cr1_mask |= SAI_XCR1_MONO;
579 if ((sai->slots == 2) && (params_channels(params) == 1))
580 cr1 |= SAI_XCR1_MONO;
582 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
584 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
591 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
593 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
596 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
599 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
600 * By default slot width = data size, if not forced from DT
602 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
603 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
604 sai->slot_width = sai->data_size;
606 if (sai->slot_width < sai->data_size) {
607 dev_err(cpu_dai->dev,
608 "Data size %d larger than slot width\n",
613 /* Slot number is set to 2, if not specified in DT */
617 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
618 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
619 SAI_XSLOTR_NBSLOT_MASK,
620 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
622 /* Set default slots mask if not already set from DT */
623 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
624 sai->slot_mask = (1 << sai->slots) - 1;
625 regmap_update_bits(sai->regmap,
626 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
627 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
630 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
631 sai->slots, sai->slot_width);
636 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
638 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
639 int fs_active, offset, format;
642 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
643 sai->fs_length = sai->slot_width * sai->slots;
645 fs_active = sai->fs_length / 2;
646 if ((format == SND_SOC_DAIFMT_DSP_A) ||
647 (format == SND_SOC_DAIFMT_DSP_B))
650 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
651 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
652 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
654 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
655 sai->fs_length, fs_active);
657 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
659 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
660 offset = sai->slot_width - sai->data_size;
662 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
663 SAI_XSLOTR_FBOFF_MASK,
664 SAI_XSLOTR_FBOFF_SET(offset));
668 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
670 unsigned char *cs = sai->iec958.status;
672 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
673 cs[1] = IEC958_AES1_CON_GENERAL;
674 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
675 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
678 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
679 struct snd_pcm_runtime *runtime)
684 /* Force the sample rate according to runtime rate */
685 mutex_lock(&sai->ctrl_lock);
686 switch (runtime->rate) {
688 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
691 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
694 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
697 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
700 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
703 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
706 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
709 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
712 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
715 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
718 mutex_unlock(&sai->ctrl_lock);
721 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
722 struct snd_pcm_hw_params *params)
724 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
725 int cr1, mask, div = 0;
726 int sai_clk_rate, mclk_ratio, den, ret;
727 int version = sai->pdata->conf->version;
728 unsigned int rate = params_rate(params);
730 if (!sai->mclk_rate) {
731 dev_err(cpu_dai->dev, "Mclk rate is null\n");
736 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
738 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
739 sai_clk_rate = clk_get_rate(sai->sai_ck);
741 if (STM_SAI_IS_F4(sai->pdata)) {
743 * mclk_rate = 256 * fs
744 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
745 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
747 if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
748 div = DIV_ROUND_CLOSEST(sai_clk_rate,
754 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
755 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
757 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
758 * Note: NOMCK/NODIV correspond to same bit.
760 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
761 div = DIV_ROUND_CLOSEST(sai_clk_rate,
762 (params_rate(params) * 128));
764 if (sai->mclk_rate) {
765 mclk_ratio = sai->mclk_rate / rate;
766 if (mclk_ratio == 512) {
769 } else if (mclk_ratio != 256) {
770 dev_err(cpu_dai->dev,
771 "Wrong mclk ratio %d\n",
775 div = DIV_ROUND_CLOSEST(sai_clk_rate,
778 /* mclk-fs not set, master clock not active */
779 den = sai->fs_length * params_rate(params);
780 div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
785 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
786 dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
789 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
791 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
792 cr1 = SAI_XCR1_MCKDIV_SET(div);
793 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
795 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
802 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
803 struct snd_pcm_hw_params *params,
804 struct snd_soc_dai *cpu_dai)
806 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
809 sai->data_size = params_width(params);
811 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
812 /* Rate not already set in runtime structure */
813 substream->runtime->rate = params_rate(params);
814 stm32_sai_set_iec958_status(sai, substream->runtime);
816 ret = stm32_sai_set_slots(cpu_dai);
819 stm32_sai_set_frame(cpu_dai);
822 ret = stm32_sai_set_config(cpu_dai, substream, params);
827 ret = stm32_sai_configure_clock(cpu_dai, params);
832 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
833 struct snd_soc_dai *cpu_dai)
835 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
839 case SNDRV_PCM_TRIGGER_START:
840 case SNDRV_PCM_TRIGGER_RESUME:
841 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
842 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
844 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
845 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
848 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
849 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
851 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
853 case SNDRV_PCM_TRIGGER_SUSPEND:
854 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
855 case SNDRV_PCM_TRIGGER_STOP:
856 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
858 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
861 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
863 (unsigned int)~SAI_XCR1_SAIEN);
865 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
867 (unsigned int)~SAI_XCR1_DMAEN);
869 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
871 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
872 sai->spdif_frm_cnt = 0;
881 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
882 struct snd_soc_dai *cpu_dai)
884 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
886 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
888 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
891 clk_disable_unprepare(sai->sai_ck);
892 sai->substream = NULL;
895 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
896 struct snd_soc_dai *cpu_dai)
898 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
899 struct snd_kcontrol_new knew = iec958_ctls;
901 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
902 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
903 knew.device = rtd->pcm->device;
904 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
910 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
912 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
913 int cr1 = 0, cr1_mask;
915 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
917 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
918 * as it allows bytes, half-word and words transfers. (See DMA fifos
921 sai->dma_params.maxburst = 4;
922 /* Buswidth will be set by framework at runtime */
923 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
925 if (STM_SAI_IS_PLAYBACK(sai))
926 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
928 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
930 /* Next settings are not relevant for spdif mode */
931 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
934 cr1_mask = SAI_XCR1_RX_TX;
935 if (STM_SAI_IS_CAPTURE(sai))
936 cr1 |= SAI_XCR1_RX_TX;
938 /* Configure synchronization */
939 if (sai->sync == SAI_SYNC_EXTERNAL) {
940 /* Configure synchro client and provider */
941 sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
942 sai->synco, sai->synci);
945 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
946 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
948 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
951 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
952 .set_sysclk = stm32_sai_set_sysclk,
953 .set_fmt = stm32_sai_set_dai_fmt,
954 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
955 .startup = stm32_sai_startup,
956 .hw_params = stm32_sai_hw_params,
957 .trigger = stm32_sai_trigger,
958 .shutdown = stm32_sai_shutdown,
961 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
962 int channel, unsigned long hwoff,
963 void *buf, unsigned long bytes)
965 struct snd_pcm_runtime *runtime = substream->runtime;
966 struct snd_soc_pcm_runtime *rtd = substream->private_data;
967 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
968 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
969 int *ptr = (int *)(runtime->dma_area + hwoff +
970 channel * (runtime->dma_bytes / runtime->channels));
971 ssize_t cnt = bytes_to_samples(runtime, bytes);
972 unsigned int frm_cnt = sai->spdif_frm_cnt;
977 *ptr = ((*ptr >> 8) & 0x00ffffff);
979 /* Set channel status bit */
981 mask = 1 << (frm_cnt - (byte << 3));
982 if (sai->iec958.status[byte] & mask)
989 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
992 sai->spdif_frm_cnt = frm_cnt;
997 /* No support of mmap in S/PDIF mode */
998 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
999 .info = SNDRV_PCM_INFO_INTERLEAVED,
1000 .buffer_bytes_max = 8 * PAGE_SIZE,
1001 .period_bytes_min = 1024,
1002 .period_bytes_max = PAGE_SIZE,
1007 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1008 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1009 .buffer_bytes_max = 8 * PAGE_SIZE,
1010 .period_bytes_min = 1024, /* 5ms at 48kHz */
1011 .period_bytes_max = PAGE_SIZE,
1016 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = {
1018 .probe = stm32_sai_dai_probe,
1019 .pcm_new = stm32_sai_pcm_new,
1020 .id = 1, /* avoid call to fmt_single_name() */
1026 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1027 /* DMA does not support 24 bits transfers */
1029 SNDRV_PCM_FMTBIT_S8 |
1030 SNDRV_PCM_FMTBIT_S16_LE |
1031 SNDRV_PCM_FMTBIT_S32_LE,
1033 .ops = &stm32_sai_pcm_dai_ops,
1037 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = {
1039 .probe = stm32_sai_dai_probe,
1040 .id = 1, /* avoid call to fmt_single_name() */
1046 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1047 /* DMA does not support 24 bits transfers */
1049 SNDRV_PCM_FMTBIT_S8 |
1050 SNDRV_PCM_FMTBIT_S16_LE |
1051 SNDRV_PCM_FMTBIT_S32_LE,
1053 .ops = &stm32_sai_pcm_dai_ops,
1057 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1058 .pcm_hardware = &stm32_sai_pcm_hw,
1059 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1062 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1063 .pcm_hardware = &stm32_sai_pcm_hw_spdif,
1064 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1065 .process = stm32_sai_pcm_process_spdif,
1068 static const struct snd_soc_component_driver stm32_component = {
1069 .name = "stm32-sai",
1072 static const struct of_device_id stm32_sai_sub_ids[] = {
1073 { .compatible = "st,stm32-sai-sub-a",
1074 .data = (void *)STM_SAI_A_ID},
1075 { .compatible = "st,stm32-sai-sub-b",
1076 .data = (void *)STM_SAI_B_ID},
1079 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1081 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1082 struct stm32_sai_sub_data *sai)
1084 struct device_node *np = pdev->dev.of_node;
1085 struct resource *res;
1087 struct of_phandle_args args;
1093 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094 base = devm_ioremap_resource(&pdev->dev, res);
1096 return PTR_ERR(base);
1098 sai->phys_addr = res->start;
1100 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1101 /* Note: PDM registers not available for H7 sub-block B */
1102 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
1103 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1105 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
1106 base, sai->regmap_config);
1107 if (IS_ERR(sai->regmap)) {
1108 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
1109 return PTR_ERR(sai->regmap);
1112 /* Get direction property */
1113 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1114 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1115 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1116 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1118 dev_err(&pdev->dev, "Unsupported direction\n");
1122 /* Get spdif iec60958 property */
1124 if (of_get_property(np, "st,iec60958", NULL)) {
1125 if (!STM_SAI_HAS_SPDIF(sai) ||
1126 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1127 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1130 stm32_sai_init_iec958_status(sai);
1135 /* Get synchronization property */
1137 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1138 if (ret < 0 && ret != -ENOENT) {
1139 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1143 sai->sync = SAI_SYNC_NONE;
1145 if (args.np == np) {
1146 dev_err(&pdev->dev, "%s sync own reference\n",
1148 of_node_put(args.np);
1152 sai->np_sync_provider = of_get_parent(args.np);
1153 if (!sai->np_sync_provider) {
1154 dev_err(&pdev->dev, "%s parent node not found\n",
1156 of_node_put(args.np);
1160 sai->sync = SAI_SYNC_INTERNAL;
1161 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1162 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1164 "External synchro not supported\n");
1165 of_node_put(args.np);
1168 sai->sync = SAI_SYNC_EXTERNAL;
1170 sai->synci = args.args[0];
1171 if (sai->synci < 1 ||
1172 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1173 dev_err(&pdev->dev, "Wrong SAI index\n");
1174 of_node_put(args.np);
1178 if (of_property_match_string(args.np, "compatible",
1179 "st,stm32-sai-sub-a") >= 0)
1180 sai->synco = STM_SAI_SYNC_OUT_A;
1182 if (of_property_match_string(args.np, "compatible",
1183 "st,stm32-sai-sub-b") >= 0)
1184 sai->synco = STM_SAI_SYNC_OUT_B;
1187 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1188 of_node_put(args.np);
1193 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1194 pdev->name, args.np->full_name);
1197 of_node_put(args.np);
1198 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1199 if (IS_ERR(sai->sai_ck)) {
1200 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
1201 return PTR_ERR(sai->sai_ck);
1207 static int stm32_sai_sub_dais_init(struct platform_device *pdev,
1208 struct stm32_sai_sub_data *sai)
1210 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev,
1211 sizeof(struct snd_soc_dai_driver),
1213 if (!sai->cpu_dai_drv)
1216 if (STM_SAI_IS_PLAYBACK(sai)) {
1217 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai,
1218 sizeof(stm32_sai_playback_dai));
1219 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name;
1221 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai,
1222 sizeof(stm32_sai_capture_dai));
1223 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name;
1225 sai->cpu_dai_drv->name = dev_name(&pdev->dev);
1230 static int stm32_sai_sub_probe(struct platform_device *pdev)
1232 struct stm32_sai_sub_data *sai;
1233 const struct of_device_id *of_id;
1234 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1237 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1241 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1244 sai->id = (uintptr_t)of_id->data;
1247 mutex_init(&sai->ctrl_lock);
1248 platform_set_drvdata(pdev, sai);
1250 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1252 dev_err(&pdev->dev, "Parent device data not available\n");
1256 ret = stm32_sai_sub_parse_of(pdev, sai);
1260 ret = stm32_sai_sub_dais_init(pdev, sai);
1264 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1265 IRQF_SHARED, dev_name(&pdev->dev), sai);
1267 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1271 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
1272 sai->cpu_dai_drv, 1);
1276 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1277 conf = &stm32_sai_pcm_config_spdif;
1279 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1281 dev_err(&pdev->dev, "Could not register pcm dma\n");
1288 static struct platform_driver stm32_sai_sub_driver = {
1290 .name = "st,stm32-sai-sub",
1291 .of_match_table = stm32_sai_sub_ids,
1293 .probe = stm32_sai_sub_probe,
1296 module_platform_driver(stm32_sai_sub_driver);
1298 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1299 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1300 MODULE_ALIAS("platform:st,stm32-sai-sub");
1301 MODULE_LICENSE("GPL v2");